Tristate Buffer Output if Input is High-Z?

[Jeff Walther]

If a tristate buffer is enabled by its control line, but the input to 
the buffer is at high-Z is there a typical output?

I checked the relevant datasheet, but this situation isn't covered. 
There's timing for when the buffer is enabled and the input switches 
from L to H or H to L, but nothing about the input at high-Z.

The truth table as written in the datasheet:

2OE	2A	2Y
H	H	H
H	L	L
L	X	Z

I need another row for

2OE	2A	2Y
H	Z	?

Where OE is the control, A is the input and Y is the output.

I'm still futzing about with this IIfx SIMM idea.   I plan to use a 
pair of SN74ABT241A octal buffers to make the 16M X 4 chips look as 
if they have separate Din and Dout pins.   And I planned to use the 
WE_ signal as the control to the buffers.

However, it occurred to me that the computer might hold WE high at 
all times except during writes.  This would leave the Dout path 
enabled almost all the time, which might interfere with other 
activity on the data bus.

Once CAS goes high, the Dout of the DRAM chips would go back to 
high-Z, so the computer designers would figure, leaving WE_ high most 
times is fine.  DRAM output is high-Z unless one just did a read with 
a CAS signal.

But if I'm feeding the DRAM output into a tristate buffer this might 
not work.  The high-Z from the DRAM goes to the buffer as input.  The 
WE_ signal enables the buffer.   What comes out the other end of the 
tristate buffer onto the data bus?  If the buffer drives the data bus 
in this situation, then this won't work.

I really don't want to add an AND gate and an inverter so I can 
change OE for the tristate buffer to WE*CAS'.

Of course, if WE_ is floating most of the time, it's not a problem. 
I just lightly tie OE to GND and when WE floats, the buffer outputs 
go to high-Z.  But I can't count on that.

Run off a set with spaces for all the possible control signals I can 
imagine and experiment?

Jeff Walther