SIMM, Address Lines Order?

[Jim Battle]

Scott Stevens wrote:

...
> The Z80 has DRAM refresh functionality built right into the processor,
> if I'm remembering right.

Except I think it only ran through 128 addresses, which was OK for 16K bit 
DRAMs.  I believe somebody made 64K bit DRAMs that were arranged with 128 rows 
so that Z80 refresh would still work.

And has been pointed out, systems that use CAS before RAS refresh don't care 
about this.