64 pin SIMM (Mac IIFX) Specs?

[Jeff Walther]

>Date: Wed, 7 Sep 2005 18:37:39 +0100 (BST)
>From: ard at p850ug1.demon.co.uk (Tony Duell)

>>  If the DIN and DOUT are common on the MB

>My guess is that if they are linked, they will be linked by short tracks
>near the SIMM sockets. And you'd be linking them with short tracks on the
>SIMM PCBs. Considering that a light-nanosecond (in free space) is about 1
>foot, and that the velocity factor of a PCB is going to be around 0.6, I
>would guess about 8" of length difference would give 1ns of timing skew.
>I don't know how fast that amachine runs, but I would think you'd have to
>have a right stupid layout for using both pins to matter much.

Well, darn it, they aren't linked.  It turns out that the memory 
controller on the IIfx buffers the writes, so that the CPU can go do 
something else after only 2 cycles instead of 6, unless, of course, 
the next operation is a memory access.

So the the data lines from the SIMMs are routed to 74F573 D-type 
latches.  It appears that the SIMM's DIN comes from the latches' 
outputs and DOUT goes to the latches' inputs.   I have not confirmed 
it yet (must pull the PGA 68030 to get access to the data lines) but 
I suspect that the bidirectional databus goes to the input lines of 
the latches.

So, on a read, the data would just come out of the memory straight to 
the bidirectional data bus.   On a write the data bus would take data 
to the latches' inputs where it would be buffered, and the memory 
controller presumably has control of the LE (latch enable) and OE 
(output enable) lines to the latches.

So, if I tied DIN and DOUT together, it looks like there are at least 
two potential trouble spots.

1)  If the memory controller does not switch the latches to High-Z 
(OE inactive) upon completion of Writes, then  on a Read, the data 
from the memory would be in contention with the data still held by 
the latches from the previous write.

2)  While the memory controller is buffering a Write, that data would 
feed back from the latches, along the tied together In and Out to the 
bidirectional data bus.

So, for example, the CPU signals a Write.  The memory controller 
takes over, and the data is buffered and held in the latches.  The 
CPU is done in 2 cycles, but the MC will need 6 cycles total to 
complete the write.  Now the CPU goes off to do something like an IO 
operation during which it will also need the data bus.  However, 
because the In and Out pins are tied together, the bidirectional 
portion of the data bus is being fed the data from the previous Write 
operation for four more cycles while the memory controller completes 
the write operation.  This will interfere with any other use of the 
data bus.

So unless the data bus to the memory is seperate from the data bus to 
the rest of the computer, I believe that tieing the In and Out pins 
together will screw things up.

Does my reasoning seem sound?  What did I miss?  Was that clear?

Jeff Walther