datasheets for 82S21 - Signetics 32x2 SRAM? : pdp2

[Tony Duell]

> 
> Tony Duell wrote:
> >>Ummm what about a 7480  :)
> > 
> > 
> > A gated full adder? (I had to look it up...). I have a data sheet which 
> > even includes a transistor-level schematic.
> > 
> Hmm that is not web ... drat .
> I am guessing that is about 15 ns delay.

It would seem to be a lot slower than that...

I have (typical/max in ns)

t(PLH) (Cn to Cn+1/) 13/17
t(PHL) (Cn to Cn+1/) 8/12
t(PLH) (Bc to Cn+1/) 18/25
t(PHL) (Bc to Cn+1/) 38/55
t(PLH) (Ac to S) 52/70
t(PHL) (Ac to S) 62/80
t(PLH) (Bc to S/) 38/55
t(PHL) (Bc to S/) 56/75
t(PLH) (A1 to A*) 48/65
t(PHL) (A1 to A*) 17/25
t(PLH) (B1 to B*) 48/65
t(PHL) (B1 to B*) 17/25

The A*, B* outputs laoded with 15pf, the others loaded with the standard 
TTL load network.

That's for a plain 7480, I can't find any other versions.



-tony