was Re: datasheets for 82S21 - Signetics 32x2 SRAM? now verilog

[Brad Parker]

"Dwight K. Elvey" wrote:
>
> Make the design race free.

If by "race free", you mean "delay invariant" I agree whole heartedly,
but I my first step is to simulate the old design w/o changes, so I'm
stuck with it's issues.

>I'm not sure if I understand you statement about accurate.
>A NAND gate is a NAND function. Anything else is incorrect.

I ment accurate in two ways.  First, correct behavior (which is not as
easy as I thought it would be) and second, "reasonably close timing".

I initially added delays to match the original ttl parts but I've since
backed off a bit and only added them in the memories.

>I hope you are not trying to do timing verification with verilog modeling?

No, not timing verification, but the design has some timing dependancies
- mostly in areas of long propagation delays (i.e. slow parts caused
problems).

Once I have the original netlist working I plan to rewrite it in a more
modern "vector" style, mostly for fun and as a learning exerience.  But I want
the original netlist as a baseline.

-brad