datasheets for 82S21 - Signetics 32x2 SRAM?

[Dwight K. Elvey]

>From: "Brad Parker" <brad at heeltoe.com>
>
>
>Tony Duell wrote:
>>
>>My experience with simulators suggests that's a massive _underestimate_ 
>>of the time it would take. 
>
>Well, I did manage to make a microcode simulator and it boots the lisp
>machine.
>
>I think there are a few very subtle bugs in the pipe, however, and I
>think the only way I'll find them is to watch the real hardware work.
>
>I think the timing on this machine, and the 74S/74LS parts it uses are
>slow enough that verilog will do fine.  In reality what I am saying is
>not about verilog, but the accuracy of the models I have created.  So,
>restated, I think I can make models which are accurate enough for this
>type of design.

Hi
 Make the design race free. I'm not sure if I understand
you statement about accurate. A NAND gate is a NAND function.
Anything else is incorrect.
 I hope you are not trying to do timing verification with
verilog modeling?
Dwight

>
>heh.  we'll see.
>
>-brad
>