FPGA VAX update

[woodelf]

Sean 'Captain Napalm' Conner wrote:

>  On my 500MHz station at work, each dataset would take 2 hours, and an
>entire run (which took the better part of a year when I did it lo' these
>many years ago) would take 41 days to complete.  I then did it on a
>quad-Pentium 2.4GHz machine we have at work and the results were ... um ...
>humbling: 45 *hours* to do an entire run.
>
>  
>
Well I just upgraded to a faster PC, with XP.  I have been using a CUPL 
compiler
for CPLD's and newer is not allways better.  Sure my designs  now  
compile faster
-- a few seconds but GUI interface crashes  more often so is it better?
With  what FPGA work I have done in the past , you only get about  80% 
of the
resources in a FPGA, after that you have long compile times, problems 
with pin locking
and sensitivity to logic design,
Ben alias woodelf