Pinout for SED9421

[Philip Pemberton]

In message <m1EfoPa-000IyHC at p850ug1>
          ard at p850ug1.demon.co.uk (Tony Duell) wrote:

> You're lucky. I normally have to start by producing the schematics (mind 
> you, for simple stuff, its quicker _for me_ to draw them out than either 
> to  do battle with the manufacturer or to download them and figure out 
> how to print them...)

If I didn't have the schematics, I'd be SOL - Asteroids and Battlezone arcade
PCBs are getting a bit thin on the ground...

> > Only thing I am trying to work out is why the hell the state machine jumps to
> > state 9 on startup, which is a DMALD microinstruction. Basically, when it
> > starts up, it pulls an address off the stack and jumps to it. Unless I'm
> 
> Are you sure it does? In particular, are you sure the output of the stack 
> is not tri-stated and the lines driven by something else?

I've just found another gate that I missed on my first look at the circuit...
The Y_LOW and Y_HI/OPCODE latches are cleared to zero on a reset. That means
the opcode being loaded on startup has a low LSB. That makes the read strobe
for the register file inactive, and the GATE lines for the two address
buffers (H6 and J6) active. They gate Y[11:0] onto the counter inputs and the
counter's LOAD input gets strobed by DMALD. Cute trick... 

This thing has logic tricks to rival Woz's IWM (Disk II) floppy controller...

> I've used the LS170 quite a bit (open-collector, not tri-state outputs), 
> and I am darn sure the power-up state is not guaranteed to be anything 
> special.

I thought as much. "Guaranteed poweron state: None, probably random crap".
Same as pretty much any ordinary SRAM really.

Thanks.
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