FPGA VAX update, now DIY TTL computers

[woodelf]

Allison wrote:

>>This is 18 bits ... 2  or 3 or 6 or  9  is needed here, not 2 or 4 or 8 
>>or blah! 16 :)
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>So throw away the excess bits.  It's still cheaper.  Also there is a 
>Single full adder TTL part the 7480.
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I just did that with the LS design ... dropped down from 40 to 26 chips 
for 2 bits.
Oh wait I was to buy FOOD today  ...  not doodle on quad paper. :)

>Well the punch is ahrd but a HS reader is trivial to build AS it's 
>been done many times.
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I guess I'll just have to use a ON-LINE punch then...

>as to putting it CPLD or FPGA, yes you could but I'm saying/staying in 
>TTL with available SSI and MSI functions it's possible to be chip count
>reasonable.
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>I have nearly 30 IDE drives all under 500mb I can build around.  Its
>easy to make them look like a RK05 or whatever to a PDP-8 databreak
>interface.  What MS does next year or even lsat years does not impact 
>me at all.
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But my CPLD software allways needs a new download ...

>Ah foo.
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PS. with the MATURE  LS line of products, who knows what will be 
produced in 5 years.

>Allison
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