FPGA VAX update, now DIY TTL computers

[Allison]

>
>Subject: Re: FPGA VAX update, now DIY TTL computers
>   From: Paul Koning <pkoning at equallogic.com>
>   Date: Fri, 04 Nov 2005 10:09:17 -0500
>     To: cctalk at classiccmp.org
>
>>>>>> "Kevin" == Kevin Handy <kth at srv.net> writes:
>
> Kevin> Allison wrote:
> >> If you ask me the real horror of parity memory is it only tells
> >> you disaster
> >> happend just as your about to crash.  ...
>
> Kevin> Parity depends on if you would prefer a crash to silently
> Kevin> generating incorrect results.
>
> Kevin> ECC tries to hide the errors, but can still cause a crash if
> Kevin> too many bits change.
>
>Correct.  And all error checking codes will fail to detect certain
>errors.
>
>Which is the right answer depends on what kind of errors you consider
>likely enough to worry about, and what recovery you require.
>
>       paul

There is also the matter of fault tolerence.  Parity doen't provide that
unless the OS can map out the offending bank and the offending bank
isn't in a critical location.  ECC can keep you going if you have a 
stuck bit but it's up to the user/maintence to fix asap.



Allison