That darn Intel jingle...

[Tony Duell]

> 
> On 11/3/2005 at 6:45 PM Allison wrote:
> 
> >Z80 PIO.
> 
> 16 measily bits of I/O in a 40 pin package. :(  What a waste of real
> estate.

Well, there are 2 handshake lines for each port from what I remember. So 
that's 20 pins. Add another 8 for the host-side data bus and two for 
power, and you've accounted for 30 pins. That leaves 10 for register 
select, read/write, etc. Since there's no common package between 30 and 
40 pins, it seems reasonable to me.

> can't do sync in a single-channel 40 pin package yet.  The Z80 SIO and the
> Intel 8274 are essentially the same chip that should have probably been
> made part of the PC instead of the 8250.

I thiought there was an IBM I/O card for the PC with an 8274 on it. One 
of thr two synchonous ones mentioned in the TechRef. No, I've not seen it.

> 
> Speaking of which--I've got a bunch of Z80 DART chips.  I've been told that
> these are really derated Z80 SIO chips.  Will they do synchronous I/O or
> has that part been disabled?  I can't find my databook for the things any
> more.

>From what I remember, they are pin compatible with one version of the SIO 
(rememebr the SIO had 41 pins, really ;-)), and have the same register 
allocation. I was told they were actually SIOs that had failed on the 
synchronous side, but I don't know if that logic was disabled or just not 
used.

In any case the Z80 peripherals are very easy to link to the Z80, and 
harder to link to something else (there's no Wr/ pin, the chip assumes 
that an I/O cycle without Rd/ and without M1/ is a write, that sort of 
thing).

-tony