FPGA VAX update, now DIY TTL computers

[a.carlini at ntlworld.com]

der Mouse wrote:

> Because fake parity needs just 2*lg(N)-1 XOR gates (N being the
> number of data bits per word), one of them being NXOR if odd parity
> is used; real parity needs 2^M memory cells (M being the number of
> address lines).  For any memory configuration that made it out of the
> lab, fake parity is orders of magnitude less complicated a chip - and
> correspondingly cheaper.     

But the 9th memory chip already exists and costs thruppence
(with discounts for bulk) whereas a parity chip needed to
be designed and built and still come in cheaper. Maybe there
was one conveniently around (there would have to be an 
implementation just to do the actual parity checking in the 
system, but that could have been buried somewhere in a
PC chipset chip somewhere).

Obviously it must have been worth someone's while, I just
remember being a little surprised that this sort of chicanery
could be made to pay off (at least for a short while).

Antonio


-- 

Antonio carlini
arcarlini at iee.org