FPGA VAX update, now DIY TTL computers

[Allison]

>
>Subject: Re: FPGA VAX update, now DIY TTL computers
>   From: Sridhar Ayengar <ploopster at gmail.com>
>   Date: Thu, 03 Nov 2005 11:04:58 -0500
>     To: General Discussion: On-Topic and Off-Topic Posts <cctalk at classiccmp.org>
>
>woodelf wrote:
>> Chuck Guzis wrote:
>> 
>>> Consider the very old Packard Bell PB250--22 bit words, fewer than 400
>>> transistors and 2500 diodes, 63 instructions.  Power consumption about 40
>>> watts, exclusive of I/O:
>>>
>>> http://ed-thelen.org/comp-hist/BRL61-p.html 
>>> The trick, of course, is to use bit-serial methods.  It seems to me that
>>> one could greatly simplify construction of a homebrew machine that way.
>>> We're not doing this for speed, right?
>>>
>>>  
>>>
>> That is interesting reading.  Are there any of the large 48 bit 
>> processors still around?
>> Also TTL and memory is easy to use in 4 bit  sizes, a odd size like 18 
>> bits is not so
>> easy to work with.
>
>How does parity memory work?  Must one use the extra bit for parity or 
>could one use it as a ninth data bit?
>
>Peace...  Sridhar

Parity required an extra bit to stor the parity so that it could be compared 
on read. That bit may or may not have been part of the data path logic.

Allison