FPGA VAX update

[Chuck Guzis]

On 11/3/2005 at 9:49 AM Paul Koning wrote:

>If you're going to go the 3 address route, it sounds like you're well
>on your way towards reinventing the CDC 6000 architecture.  And of
>course that would be a fine thing to do -- if you're going to explore
>computer architectures, what better path to take than the one first
>walked by the foremost computer architecture genius of the 20th
>century?

...or one could use a MIPS chip...

To me, the genius (and unrecognized at the time) of the 6600 architecture
was Cray's discarding the idea of a "condition code" in the IBM sense,
wherein the state of a result is actually divorced from the result itself.
The 6600 had no compare instruction, nor condition codes.  To compare
registers X1 and X2 and branch on the result, one would subtract them and
test (via branch) the contents of the result register.  Three addresses and
no condition codes gave a huge amount of flexibility to placement of
instructions in the stream.  The 15-bit instruction length for the bulk of
instructions didn't hurt either.  I recall spending many hours hand-timing
loops for the 6600 to get to that magic goal of getting one issue per
cycle--and even better if the loop could be fully contained in the "stack"
(a 10-word local instruction cache). 

But I don't have rose-colored glasses either.  The "call" (return jump)
instruction implementation was an abomination because it actually stored
the return address as a jump instruction in program memory, rather than
putting it in a register.  There was no simple way to save all registers
(the actual code to do so was a marvel of arcane coding).   There was no
PC-relative addressing for jumps.   I still wonder about the utilitiy of
the "count the 1's" instruction.  I could go on...

I know this seems ridiculous with today's fast CPUs and the amount of
bloatware around, but getting tight code was a mark of pride back in those
days. 

I miss that.

Cheers,
Chuck