MITS 8800B CPU Board

[Tom Jennings]

On Tue, 14 Jun 2005, Randy McLaughlin wrote:

> Please note that by using current RAM chips that are >= 64K address decoding 
> is extremely simplified.  To carve out space from ROM not only butchers the 
> address map but adds complexity.
>
> As I already said either an I/O instruction or an address line can accomplish 
> the same task.

I think you missed the point, plus I left out one detail:

* It specifically doens't require carving the address space up AT
ALL.  The machine simply has 64K contiguous RAM, from 0000h to
ffffh.

* The EPROM board used PHANTOM to disable RAM when addressed -- I
left that little detail out!

* The "top 2K of the first 32K" description was distracting in
this example, sorry.  For completeness: That address was chosen
for this system because it used two 32K RAM cards; you could run
the EPROM monitor with only th elower one; plus in the S100 days a
common "convention" was to put floppy controller or whatever
address space "up high", and 7e00h avoided colliding; pressing
RESET smashed memory at that location, and not in any CP/M system
space (eg. 0 - 80h or 48K+). It obviously requires a CPU card
that does reset-vectoring, ala Cromemco ZPU.

A vanilla 8080 (eg. MITS) of course resets to 0000h; this trick is
even cleaner for that, since the "copy EPROM code to RAM" could do
so without bothering the RAM area overlaid by the EPROM during the
copy process.