TD100 delay line chip?

[Tony Duell]

> 
> 
> The question about the ttl oscillator jogged my memory.
> 
> Anyone recognize a line of "delay line" chips with names like TD25,
> TD50, TD100, etc...  The look they were expensive at the time, like $10
> around 1976.

Yes, I've used them. I think they're still available. Some had internal 
buffering and termination, others were just the delay line. 

An easy way to tell them apart, given the physcial device, is that the 
unbuffered ons show a low DC resistance between the output pins (they are 
taps on a coil inside), the buffered ones do not (they have amplifier 
circuits between the taps and the pins).

> 
> The TD100 pinout looks like this:
> 
>       +------+
> input | 1 14 | vcc
>       | 2 13 | 
>       | 3 12 | 20ns
> 40ns  | 4 11 | 
>       | 5 10 | 60s
> 80ns  | 6  9 | 
> gnd   | 7  8 | 100ns
>       +------+
> 
> I don't have an exact part number or mfg.  (I know where I can find one
> but it's not easy and will take some work)
> 
> I want to model these in verilog but I'm not exactly sure how they work.
> They are delay lines, but I'm not sure how they react.  The input seems
> to be a short pulse from high to low of about 40ns.  I'm assuming this
> produces an approx 40ns pulse after the prescibed delay, but I'm not
> entirely sure.

Yes. Basically, any transition on the input pin causes a similar 
transition on the output after the specified delay.

So if you feed in a 40ns-wide pulse, say +ve going then and look at, say, 
the 50ns output :

The input is a 0

It goes to 1. 

40nx later, it goes back to 0 and stays there

after a further 10ns (i.e. 50 ns from the start), the rising edge has 
'got to the output'. The output goes high.

And after another 40 ns (i.e. 90ns from the start), it goes low again.

 ----
-    ----------  Input

      ----
------    ----  Output (50ns delay)

Each '-' represents 10ns
 
-tony