6800 opcode $02

[Tony Duell]

> 
>     I'd suggest finding a VHDL or Verilog implementation, and see if 

I am not sure those are likely to be free, and if they are they would be 
'unofficial', which means they might well not implement all undocumented 
features correctly..

> that provides any insight.  Also, Google for '6800 undocumented opcodes' 
> (no quotes).  There are a number of hits.  Most seem to indicate that 
> the undocumented opcode (no value given) causes the processor to go into 
> a mode where there are no instruction fetchs, but the address bus runs 
> incrementing bus cycles.

That's the 'HCF' (Halt and Catch Fire) instruction I mentioned.

Let me explain where all this is coming from. I have an HP37201 HPIB 
Extender on the bench. It's basically a 6800-based microprocessor system 
with the right I/O chips (FWIW, the HPIB handshake is handled in 
firmware, there are about 5 6821 PIAs on the board to handle the HPIB 
lines, the V25 dialer port, status LEDs, etc).

Anyway, there's a link on the board labelled 'SA TEST'. I think that's 
'Signature Analyser Test', HP having a love of such instruments. From 
what I've figured out so far, when it's put in the 'SA TEST' position, it 
disables the data bus buffers (thsoe are the 6881 chips I was asking 
about the other day) and uses a '241 to force 0000 0010 onto the CPU data 
lines (at least during CPU read cycles). I would guess this gets the CPU 
to do something repetitive (incrementing the address bus at full speed 
would be an obvious choice), so that you get meaningful signatures on all 
the lines. 

When I get enough of the instrument back together to power it up, I will 
flip that link and look at all relevant signals with a logic analyser.

-tony