TD100 delay line chip?

[Dwight K. Elvey]

>From: "Brad Parker" <brad at heeltoe.com>
>
>
>The question about the ttl oscillator jogged my memory.
>
>Anyone recognize a line of "delay line" chips with names like TD25,
>TD50, TD100, etc...  The look they were expensive at the time, like $10
>around 1976.
>
>The TD100 pinout looks like this:
>
>      +------+
>input | 1 14 | vcc
>      | 2 13 | 
>      | 3 12 | 20ns
>40ns  | 4 11 | 
>      | 5 10 | 60s
>80ns  | 6  9 | 
>gnd   | 7  8 | 100ns
>      +------+
>
>I don't have an exact part number or mfg.  (I know where I can find one
>but it's not easy and will take some work)
>
>I want to model these in verilog but I'm not exactly sure how they work.
>They are delay lines, but I'm not sure how they react.  The input seems
>to be a short pulse from high to low of about 40ns.  I'm assuming this
>produces an approx 40ns pulse after the prescibed delay, but I'm not
>entirely sure.

Hi
 This is generally true. You can assume that the intent is
to delay any edge by the specified time. If the pulse was longer
or shorter, it is as though both edges took some time to get
to the output pins. For the longer delays, these used actual
delay lines, composed of inductance and capacitance. I would
assume that in verilog, it was just a # delay.
 The various taps delay events at the input by the specified
amounts.
Dwight

>
>I would love to see a few pages from a data book which describes how
>these react (enough to model them correctly).
>
>any pointers?
>
>-brad
>