Floppy controller questions

[Philip Pemberton]

In message <0ILO00FI3MXS1LM0 at vms048.mailsrvcs.net>
          Allison <ajp166 at bellatlantic.net> wrote:

> Write clock sets the write data rate and should corrospond to the 
> rate needed for media. Writeclock is 2x data rate.

Does this apply to both FM and MFM? The datasheet suggests a 500kHz WrClk for
FM and 1MHz for MFM mode, which would give a 250kHz FM data rate and a 500kHz
MFM data rate. Is that right?
And RdWindow from the datasep should cover the read frequency variations,
assuming the datasep can handle the variation in mode and frequency.

> the logic does things like Data Clock recovery, Write precompensation timing

I've heard the term "write precompensation" thrown about a bit - what's the
purpose of it?

> Using a 765 for _all_ data rates and both 3.5"/5.25"/8" floppy interfaces
> implemented with LSttl fills a S100 board completly.

That's why SPLDs (GALs) and CPLDs were invented I guess. Squish the address
decoder, interface logic, and the data separator into a few LSTTLs and GALs,
or just throw everything into a single CPLD :)

> Most designs implemented a subset for 8" or 5.25"/3.5" only 
> (jumper selected) with much lower parts cost.

That's what I wanted. I don't have any 8" drives, so adding support for them
is pointless. Ideally, I want a board that has a 6502-type interface on one
side and a 34-pin IDC connector on the other, with support for most common FM
and MFM 3.5" and 5.25" formats.

> Yes, it was done on the 1.2MB AT-class machines.  Reminder: every PC with 
> rare exceptions used a 765 or a derivitive based on the 765 core.

So I've noticed. I managed to get DMA-mode transfers working, but never
managed to get polled-mode or interrupt-mode transfers working. Guess I'll
have to learn fast when I start writing code to drive the FDC...

> For MFM is when the transiston occurs rather than how many. Generally the 
> Floppy generates what is by standard expected and the FDC external logic 
> will regenerate data pulses and data window (data window is a read clock).

Right. So with FM the datasep syncs to the high-frequency signal in Gap1,
then every time there's a 0 you'll pick up a 0/1/0/1 sequence for each read
window, and when there's a 1 you'll pick up a 1/1/1/1 sequence?

And with MFM, a 0 after a 0 would be 1/0, a 0 after a 1 would be 0/0 and a 1
would be 0/1?

0/1 taken to mean "first data window was empty, second had a pulse in it".

Thanks.
-- 
Phil.                              | Acorn RiscPC600 SA220 64MB+6GB 100baseT
philpem at philpem.me.uk              | Athlon64 3200+ A8VDeluxe R2 512MB+100GB
http://www.philpem.me.uk/          | Panasonic CF-25 Mk.2 Toughbook
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