# Rigel (1989)

Rigel (never known as RVAX) was DEC's third generation VAX microprocessor. Amnon Fischer ran the project; Bill Herrick was project lead for the P (CPU) chip (code name REX), Moshe Gavrielov for the F chip (code name KIWI), and Rebecca Stamm for the C chip (code name COW). Mike Uhler was the supervising architect and wrote most of the microcode.

Rigel was the third step in an architectural roadmap for VLSI VAX processors. This roadmap, first published in 1982, envisioned new VAX processors every two years, with a performance increase of 50% per year, as well as optically-compatible CMOS processes starting at 2u and advancing down to .75u. The microprocessors provided increased performance through higher clock rates but also through improved microarchitecture: half-folded pipeline for CVAX, fully-folded pipeline for Rigel, instruction macropipelining for NVAX.

Rigel was intended to advance the MicroVAX family by providing 2.5X the performance of CVAX. Interestingly, maintaining lower power levels was not a goal. Rigel was in most ways a CMOS knockoff of the highly successful VAX 8800. It included the 8800's autonomous, state-machine driven instruction parser; a fully folded microinstruction pipeline; read-and-run and write-and-run capability; simultaneous ALU and shift operations; support for a large external cache. The companion floating point unit provided a full floating point pipeline and multi-bit hardware divide. The pipeline was overkill for Rigel, but the design was intended to be reused in vector units, NVAX and RISC processors.

Like CVAX, Rigel had a family of support chips, including the Rigel System Support Chip (RSSC) and Ghidra, the VAX 4000 system interface chip. Ghidra included a memory controller and a bus adapter to the CVAX pin bus, thus allowing most CVAX peripheral chips to be reused.

Rigel was implemented in DEC's 1.5u double-metal CMOS process (CMOS2) and ran, depending on bin points, at 35Mhz-40Mhz.

Name | Number | Size | Transistors | Comments
Rigel CPU (REX) | DC520 | 475x475 | 320,000 | The Rigel CPU is a third generation VLSI VAX microprocessor. Compared to its predecessor, it offers 2X to 3X more performance. Key features include: High performance Macro-instruction prefetch Six stage micro-instruction pipeline 2KB on chip instruction/data cache (configurable as instruction only) 64 entry fully associative TLB Subset VAX architecture Sixteen 32b general purpose registers 181 instructions 21 addressing modes 6 data types Support for optional vector processor 224 pin custom ceramic package with 3.3V I/O Supports boundary scan and board-level continuity testing Power: 6W.
Rigel FPA (KIWI) | DC523 | 500x435 | 135,000 | The Rigel FPA is the companion floating point coprocessor to the Rigel CPU. Its key features are: High performance Four-stage pipelined design ADd/subtract/multiply implemented combinatorially Multi-bit per cycle hardware divider Acceleration of integer multiply f_, d_, and g_floating point format support VAX floating point instruction set Optimized external interface Dedicated CPU to FPA control bus Overlapped control and data transfers 224 pin custom ceramic package with 3.3V I/O Supports boundary scan and board-level continuity testing Power: 4W.
Rigel Cache Controller (COW) | DC592 | 425x425 | 220,000 | The Cache Controller (vector version) implements the tag store and cache controller for the Rigel second-level cache. Key features include: Tag store and controller for 128KB second-level cache Provides invalidate filtering mechanism with separate invalidate bus and primary cache tag store copy Asynchronous bus interface for passing instruction and control information to an optional vector unit 224 pin custom ceramic package with 3.3V I/O Supports boundary scan and board-level continuity testing Power: 2.5W
Rigel Clock | DC521 | 200x200 | 350 | The Rigel clock provides the clocks used by the Rigel chip set. Its features include: Precision clock generator for the Rigel chip set Provides two sources for the four-phase overlapping Rigel clocks Capable of driving up to four loads per clock source Extremely low clock skew (< 0.5ns at each receiver) 44-pin cerquad package Power: 2W.

Rigel shipped in mid-1989 in both the low-end VAX 4000 systems (the MicroVAX name was dropped) and the mid-range VAX 6400 multiprocessors. Rigel instantly made DEC's entire mid-range and high-end product family obsolete. Until the VAX 9000 shipped, Rigel (and Mariah) based systems were the fastest VAXen in the company's portfolio.

Rigel was the only VLSI VAX to support the VAX vector option. The chips for the vector unit were designed by Doug Williams' Mid-Range Systems VLSI team:

Name | Number | Size | Transistors | Comments
Vector Register Set (VERSE) | DC555 | 520x475 | 200,000 | The Vector Register set chip provides part of the register file for the Rigel VAX Vector option. It also contains the control logic required to pipeline vector instructions to the FAVOR chip. Key features include: Contains 1/4 of the storage for the VAX vector register set (16KB) Provides four ports on the register file Performs vector merge and logical instructions Contains pipeline registers for instructions and scalar operands as well as the vector mask register Provides a 64b port to the rest of the vector unit Interfaces between the vector FPU and the other logic on the vector unit Power: 3W
Vector Data Path (FAVOR) | DC556 | 522x460 | 135,000 | The Vector Data Path chip implements the data path for a VAX vector unit. Key features include: High performance Four-stage pipelined design ADd/subtract/multiply implemented combinatorially Multi-bit per cycle hardware divider Data-independent throughput f_, d_, g_floating point and longword integer support 164 pin custom ceramic package with 3.3V I/O Supports boundary scan and board-level continuity testing Power: 4W.

### Personal Narrative

Like CVAX, Rigel started as a meditation on a previous design, in this case, by key members of the V-11 team on how to do a multi-chip design that would significantly outperform a single-chip implementation. The team took the VAX 8600 as a starting point and elaborated from there. They proposed a four-chip set, with custom hybrid technology for the interconnect. By October, 1984, when I was named manager of the Microprocessor group, a full performance model was in place and undergoing analysis. But as a result of V-11 and J-11, I had developed a strong aversion to multi-chip implementations, due to the difficulty of partitioning and managing risks. I suggested (and then insisted) that Rigel instead be based on the VAX 8800, which would allow a single-chip CPU to be built. Matters came to a head in January of 1985, and the project was restarted. By mid 1985, the project was adequately staffed and finished with performance modeling. All chip specs were written by the end of 1985.

One of the key goals for Rigel was schedule predictability. Both MicroVAX and CVAX had met their functional and performance goals but had been three months late getting to tape-out. The Rigel management team, who were all new to their positions, accepted the challenge and developed a quantitative analysis methodology for measuring progress in schematic design, circuit design, and layout. This technique worked well, and Rigel kept to its development schedule without slips.

Midway through Rigel's implementation, the mini-supercomputer fad swept the industry, triggered by the success of startup Convex. Suddenly, vectors were a mandatory addition to every architecture: the VAX, the 360, DEC's RISC efforts... Adding vector instructions to the VAX architecture, in a way that was compatible with Rigel's already well-defined micro-architecture, was not easy. Dileep Bhandarkar, Tryggve Fossum, and I worked on this for much of 1986, eventually resulting in a vector spec that was acceptable to software, implementable in both microprocessors and mainframe class machines, and worthy of a few patents. The C chip, which had taped out much earlier than the other chips, was redesigned to provide an interface to the vector unit.

The Rigel C chip taped out in January 1987, the CPU chip October, 1987, the FPU in December, 1987 -- all on schedule. Thereafter, nothing seemed to go right. The Rigel CPU was substantially larger than any chip processed to date, and it wouldn't yield. This was a defect density issue with the new CMOS-2 process -- smaller chips like the Rigel Cache chip and the CMOS-2 shrink worked. The first seven months of prototyping yielded two fully functional P chip and seven fully functional F chips -- a serious impediment to debug! Late in 1988, the drought lifted, and serious debug and characterization got underway. To everyone's surprise, Rigel ran much faster than anticipated. Designed for 25Mhz worst case operation (40ns microcycle), its most frequent bin point was 35Mhz, with some parts running as fast as 40Mhz. CMOS-2 was a bear to get working, but once it worked, it was a great process! Rigel systems shipped in July, 1989.

Like CVAX, the Rigel chips were lavishly decorated at the die level. The CPU chip sported a dinosaur logo to match its code name, the F chip had a well dressed bird as well as a doodled space-alien, and the C chip a cow.

Rigel was presented at the 1989 International Solid State Circuits Conference.

Updated 24-Feb-2008 by Bob Supnik (simh AT trailing-edge DOT com - anti-spam encoded)