# Raven

## Introduction: The ECL Conundrum

From 1975, with the introduction of the KL10, until 1991, when NVAX was released, the highest performance processors at DEC were built with ECL (emitter coupled logic) technology. Fast, hot, and not very dense, ECL was the technology of choice for high-end systems, not just at DEC, but at computer companies world-wide. Then, in the space of just a few short years, it became obsolete. In 1985, DEC's ECL systems were 7 times faster than the fastest CMOS systems. In 1992, they were no faster.

The high-end design groups at DEC made numerous attempts to cope with this shift, or to overcome it. The most ambitious attempt was Aquarius (VAX 9000), which used cutting edge multi-chip module technology and leading edge ECL processes to build a VAX mainframe. But it proved no faster than a the single-chip NVAX, and it was 25 times more expensive.

## Raven: A Brief History

An alternate approach was Raven. Raven was started in 1988 by Doug Clark, Jim Keller, and Pete Bannon of DEC's Mid-Range Systems Group, following cancellation of their gate-array based system (Argonaut) in favor of the VAX 9000. They reasoned that ECL's native advantage over CMOS in gate speed was being negated by losses in interchip communications. If an ECL VAX CPU could be crammed onto a single chip, like a CMOS microprocessor, it should have a substantially higher clock rate and a performance advantage.

Raven was a simplified VAX design with a single chip CPU and a single chip FPU. Implemented in Fujitsu's ECL standard cells, it was intended to run at 250Mhz and deliver 50 "VUPS" of performance (about twice NVAX). Power dissipation would have been a startling (for the day) 150W.

Raven discarded the macropipelining of the VAX 9000 and NVAX in favor of a VAX 8800 style micropipeline with very few logic gates per stage. Microbranching was quite complicated, with condition select done in the cycle before the actual branch, based on conditions that had occurred many cycles earlier. Most non-32b memory operations required microcode assistance.

I became involved with Raven primarily for the fun of microcoding. Rigel was done, NVAX was in Mike Uhler's capable hands, Alpha hadn't really started, and I had time on my hands. I worked with the Raven team for 18 months, first on feasibility and then on implementation. Throughout the project, the technology specs, particularly from a density point of view, kept degrading. Although the team continually simplified the design, they eventually concluded that the CPU would have to be split into multiple chips. That negated the basic premise of the project, and in early 1990 Raven was cancelled.

Doug Clark left DEC to teach at Princeton University. Jim Keller and Pete Bannon joined Digital Semiconductor and worked on the second and third generation Alpha cores, EV-5 and EV-6. Today they are at Palo Alto Semiconductor, with Dan Dobberpuhl.

## Raven Microcode Sources

All that remains of Raven are the sources to the microcode. Some, but not all, of the features of the microarchitecture can be reconstructed from comments in the files.

- align.mic
- alloc.com
- b.com
- callret.mic
- console.mic
- cstring.mic
- ctrl.mic
- decrom.mic
- define.mic
- emulate.mic
- fpoint.mic
- intexc.mic
- intlogadr.mic
- macro.mic
- memmgt.mic
- misc.mic
- muldiv.mic
- opsys.mic
- powerup.mic
- queue.mic
- specifier.mic
- vector.mic
- vfield.mic
- vvax.mic

Updated 30-Jan-2007 by Bob Supnik (simh AT trailing-edge DOT com - anti-spam encoded)