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| A Constants

## Values of Constants

Appendix A defines the values of constants referenced in the preceding chapters. Where applicable, each constant description identifies the section where the constant is defined.

### 1. Miscellaneous Constants

The stack size defines the maximum number of sixteen-bit words contained in the evaluation stack. Notice that the stack pointer must represent values in the range [0..SS] inclusive §3.3.2.

#### cSS Stack Size

    cSS: CARDINAL = 14;

The minimum size of a state vector is defined by cSV (§9.5.3).It includes enough space for the control link used by the Load Stack instructions (LSK) and for the longest fault parameter (§10.4.3). The actual size is processor dependent (§10.4.2.1).

#### cSV State Vector Size

    cSV: CARDINAL = SIZE[StateVector] +
        MAX[SIZE[ControlLink], SIZE[FSlndex], SIZE[LONG POINTER]];

The contents of the wakeup mask register is processor dependent It records the interrupt levels reserved for internal use by the processor (§10:4.4).

#### cWM Wakeup Mask

    cWM: CARDINAL;

The maximum value of the wakeup disable counter is processor dependent, but must be greater than or equal to cWDC (§10.4.4).

### A Values of Constants

#### CWDC Wakeup Disable Counter

    cWDC: CARDINAL = 7;

The minimum and maximum durations of a tick, measured in milliseconds, are given by the following constants (§10.4.5).

#### cTick Mininum and Maximum Tick Size

    cTickMin: CARDINAL = 15;
    cTickMax: CARDINAL = 60;

### 2. Constant Memory Locations

The following constants define the locations of the fixed data structures of the architecture. Notice that the `MDS` data structures appear at the same relative location in each Main Data Space. To keep it from interfering with the booting process, the Process Data Area is located at the beginning of the second bank (§lO.l.1).

#### mPDA Process Data Area

    mPDA: LONG CARDINAL = 200000B;

The frame Allocation Vector starts at page one in each Main Data Space (§9.2.1).

#### mAV Allocation Vector

    mAV: CARDINAL = 400B;

The System Data table starts at page two in each Main Data Space (§9.5.1).

#### mSD System Data Table

    mSD: CARDINAL = 1000B;

The `ESC Trap table` begins at page three in each Main Data Space. It is a maximum of four pages long (§9.1.3.1).

#### mETT ESC Trap Table

    mETT: CARDINAL = 2000B;
    3. Fault Queue Indexes

Three of the possible eight entries in the fault vector are used by the processor. The remaining entries are reserved (§10.4.3).

### A qFQ Fault Queue Indexes

    qFrameFault: CARDINAL = 0B;
    qPageFault: CARDINAL = 1B;
    qWriteProtectFault: CARDINAL = 2B;

### 4. System Data Table Indexes

Fifteen of the possible 192 entries in the System Data table are used by the processor. Other entries in the range [0..37B) are reserved. The remaining entries are available for use by the software (§9.5.1). See also the `KFCB` instruction (§9.4.2).

#### SSD System Data Table Indexes

    sBoot: CARDINAL = 1B;
    sBreakTrap: CARDINAL = OB;
    sControlTrap: CARDINAL = 6B;
    sDivZeroTrap: CARDINAL = 12B;
    sOpcodeTrap: CARDINAL = 5B;
    SProcessTrap: CARDINAL = 15B;
    sStackError: CARDINAL = 2B;
    sXferTrap: CARDINAL = 4B;
    sBoundsTrap: CARDINAL = 16B;
    sCodeTrap: CARDINAL = 7B;
    sDivCheckTrap: CARDINAL = 13B;
    SInterruptError: CARDINAL = 14B;
    SPointerTrap: CARDINAL = 17B;
    sRescheduleError: CARDINAL = 3B;
    sUnboundTrap: CARDINAL = 11B;
    SHardwareError: CARDINAL = 10B;

Design Note: The location of sBoot must be equal to two modulo four, so that the initial XFER (§4.7) will interpret it as an indirect control link (§9.1.2).

### 5. Opcode Assignments

The opcode assignments, which are the same for each implementation of the processor, are under development.

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[last edited 4/11/99 1:13AM]