#c
A source file containing Boolean logic equations and high-level
PLPL expressions is converted into a sum-of-products form which
is then programmed into a programmable logic device.

A device name must be specified and should be of the form Pxxx,
as in P22V10.  Refer to the PLPL manual for information  on the
logic syntax.
~
#o
The sum-of-products equations produced by the logic compiler are
written to an intermediate file.  The  optimizer will attempt to
logically reduce the number of product terms in the equation  by
applying a modified Quine-McCluskey algorithm.

The optimized file can then be sent to the  JEDEC  map generator
to produce a fuse map file for programming.
~
#t
Test vectors generated by this command are used by the function
simulator.  These test  vectors are specified in  a truth table
and are attached to the end of the PLPL source file. Don't care
values (or X) default to 0; to set the default to  1,  use  the
option "-X" on the command line.
~
#j
The logic equations  in  an  intermediate or optimized file are
converted  into a JEDEC  standard device/fuse  map that  can be
loaded into a programmable logic device programmer.

The following features are provided in Software Version 2.2  of
the JEDEC Map Generator:

  (1) More extensive program documentation
  (2) A PLD programmer code file
  (3) A PLD "fitting" option

(1) - Program/Design Documentation

A documentation/list option is provided via the "-L" flag. This
flag instructs JM to list the  sum-of-products logic  equations
in  the  compiled  intermediate  file  (with  the  user-defined
variable names).  A  DIP chip diagram for the part is generated
for the design  showing  the  user-defined signal names and the
assigned pins on the DIP.

A  product term usage table is  also  generated which shows the
percentage utilization of the logic  product  terms in the PLD.
Control terms (e.g., reset, preset, enable) are not included in
this calculation.

To generate the documentation file without generating  a  JEDEC
map file, do not specify an output filename with the -O option.
In the  menu/control program, this  is  accomplished  by typing
<CR> when prompted for an output filename.

(2) - PLD Programmer Code File

A code file $___PLD.CDE is included; this contains a list of the
codes accepted by different PLD programmers.  This  list  can be
updated by the user by following the format:

     device_name
         PLD_programmer_name   code 
        [PLD_programmer_name   code] @
     $

The file is terminated by the $ character. Note that more than one
PLD programmer manufacturer can be listed for a single device.

(3) - Fitting Option

If the design does not fit in the PLD selected,  JM  will try to
rearrange  the  outputs to make the design fit.  If this  is not
possible, then different PLDs are tried. The order of the search
is listed in the file $_SEARCH.DBS.  JM  will  generate  a  list
showing the new pin assignment to make the design fit.

Note that the fitting procedure is based solely on the number of
product terms for an output.  No  attempt  is made to  rearrange
input pins assigned to IO pins, and control terms (e.g., enable)
for individual outputs that may be  swapped  around  will not be
moved.

- Appending a Test Vector file to a JEDEC Map File:

When the  append  'A'  option is selected,  two  arguments  are
expected: a JEDEC file and a test vector file. The test vectors
are generated using the 'T' command in the Main Menu.  The test
vector file is appended to the  JEDEC  file in preparation  for
downloading  to  and testing  on a  PLD  programmer.  All other
commands  (make  device/fuse map,  list  equations,  etc.)  are
overriden.

- Starting a New Design

PLPL V2.2 requires pin  architecture features specified in  the
source file. To simplify  the  architecture  definition, the JM
program can be run with the "-N" option.  This will display the
available features for a pin, and the user can set these in the
program.

When  all the pin  features have been set, the output of the JM
program is a PLPL source file template containing the pins that
the user  specified  along  with the corresponding architecture
features. The user then begins entering the logic design in the
equation section of the file.
~
#s
The simulator requires 2  files: a JEDEC map file and a JEDEC test
vector file. The  JEDEC  map  file defines the logic model  to  be
simulated. The JEDEC test vectors (generated from the user-defined
function table in the .PLD file by the  TESTV  program)  represent
the stimuli to exercise the model.

The simulator is a functional simulator, i.e., all set-up and hold
times are assumed to be observed. Every input and  output/feedback
signal in the vector is applied  to all  the  product terms in the
PLD. If the part is registered, then any clock signal specified is
applied to the registers to produce the  next  state output.  Note
that  the clock can be  specified as  C or K, depending on whether
the clock pulse is  a  positive  clock (0-1-0) or a negative clock
(1-0-1).

If the clock is also used an  input  signal to other product terms
in the device, the test vector  can  be  expanded  into  3 product
terms to explicitly show the clock signal.

   For example: The test vector (for a P22V10)
        V0003 C0000000000N0LLLLHHHHLLN*

   can be expanded to
        V0003 00000000000N0LHHHHLLLHHN*
        V0004 10000000000N0LLLLHHHHLLN*  <- clock the registers
        V0005 00000000000N0LHLLHHHHLLN*

The clock (C) is replaced by a discrete 0-1-0 transition across the
3 vectors. This lets the designer use the  clock as an input signal
in a logic equation in the PLD. Example:

    COMBINATORIAL_OUT = CLK_PIN*INP1 + ....;

If the JEDEC clock symbol C were used for this example, a message
will be generated warning the user of a 0-1-0 pulse being applied
to a product term.

- Waveform Display Format

A timing waveform can be generated by using the "-W" option. This
waveform output can be sent to printers that have the IBM-extended
ASCII character set. Regular ASCII characters can also be generated
by using the "-A" option.

- JEDEC-MAP to Logic Equation Format

Any JEDEC map for a supported device can be translated into logic
equations. The "-F" requires two files: a destination file, and a
pin-name file. The pin-name file contains a list of names that the
user wants to assign to the PLD pins.

The format of the pin-name file is:

       design_name
       device
       name0 1 @
       name1 2 @
       *
 
For example:

    A_22V10_design
    P22V10
    SYSCLK 1 @
    STROBE 2 @
    SYNC   23 @
    *

The equations will be written in terms of the names listed in this
pin name file. Pins that are not listed in a pin-name file are listed
in the equation file as "PXX_".

Use the "-N" option to force the simulator to skip simulation and
immediately translate the JEDEC map.
~
#r
Use this command to run operating system commands. The prompt
"System>" will be displayed. To return to PLPL, type '*'.
~
#h
- Installing PLPL

The recommended hardware configuration is an AT-class machine
with 512K to 640K of RAM; any monitor, and a hard disk.

Copy the following programs into a PLPL subdirectory:
   - PLPL     = menu/control program
   - PLC      = logic compiler
   - OPTIMIZE = equation minimizer
   - TESTV    = manual test vector generator
   - JM       = JEDEC Map generator
   - SIM      = functional simulator
   - BPLPL    = batch file
   - $PLPLHLP.TXT = Help text for control program
   - $PLPLOPT.TXT = Option List for each of the programs

Copy the database files (Pxxxx and Sxxxx), $___PLD.CDE, and
$_SEARCH.DBS into any other subdirectory.

When you first run the PLPL package, a program that needs to know
the  location  of  the  database  files will  prompt  you for the
subdirectory name. You only have  to  enter it  once, and then it
is stored in a configuration file  for future  reference by other
programs in PLPL.

Miscellaneous Notes:
(1) The Command Line: A character string called the command line
    is displayed when executing a program in PLPL.  This  string
    can be typed at  your operating  system  prompt  to directly
    execute the program.

(2) A batch  program can  be  made to  streamline  the  PLD file
    processing procedure.  Every  program  in  the PLPL  package
    (plc,optimize,jm,sim,testv) returns a value after executing.

    In DOS, a 0 is returned if the program ran without errors,
    otherwise a 1 is returned.  A  DOS  batch  program  can be
    written  using  the  "errorlevel"  test  to  conditionally
    control file processing.

    An example DOS batch program (BPLPL.BAT) is included with
    the master  diskette.  This file  will take a PLPL source
    file  (must  be  named [filename.PLD])  and  perform  the
    following operations:

   <1> - compile the source file
   <2> - optimize the compiled file
   <3> - make a JEDEC fuse map
            = send fuse map file to   [filename.JED]
            = make documentation file [filename.LST]
   <4> - look for a test vector/function table in
         the source file
            = if no table, then stop batch processing
            = else make JEDEC format vectors
   <5> - simulate the design by creating a model from
         the JEDEC fuse map and exercising this model
         with the vectors in the test vector file
            = send simulation results to [filename.SIM]
            = write waveform patterns to [filename.WAV]
   <6> - if simulation is successful, the append the test
         vectors to the JEDEC fuse map file

    The DOS batch program provides a summary of the files
    created. Run the BPLPL program by typing

         BPLPL filename (without the .PLD extension)

    All files with the same name and with the .WAV,.SIM,.JED
    .TST, and .LST extensions are deleted.

    For VAX/UNIX and VAX-VMS users, shell scripts and command
    files can  be  written  to make use of the program return
    values.

(3) Type the program name without any parameters to get a summary
    of the available options for each program.
~
#e
Exit : returns the user to the operating system.
~
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