BS   F1   F2
-------------------------------------------------------------------------------
000 0000 0000	BUS & R
000 0000 0001	BUS & R; BUS=0 ? NEXT|1
000 0000 0010	BUS & R; SH<0 ? NEXT|1
000 0000 0011	BUS & R; SH=0 ? NEXT|1
000 0000 0100	BUS & R; NEXT|BUS[6-15]
000 0000 0101	BUS & R; BUS|ALUC0
000 0000 0110	BUS & R; MD BUS
000 0000 0111	BUS & CONST

000 0001 0000	BUS & R				MAR ALU; 
000 0001 0001	BUS & R; BUS=0 ? NEXT|1		MAR ALU; 
000 0001 0010	BUS & R; SH<0 ? NEXT|1			MAR ALU; 
000 0001 0011	BUS & R; SH=0 ? NEXT|1			MAR ALU; 
000 0001 0100	BUS & R; NEXT|BUS[6-15]		MAR ALU; 
000 0001 0101	BUS & R; BUS|ALUC0			MAR ALU; 
000 0001 0110	BUS & R; MD BUS			MAR ALU; 
000 0001 0111	BUS & CONST				MAR ALU; 

000 0010 0000	BUS & R				TASK
000 0010 0001	BUS & R; BUS=0 ? NEXT|1		TASK
000 0010 0010	BUS & R; SH<0 ? NEXT|1			TASK
000 0010 0011	BUS & R; SH=0 ? NEXT|1			TASK
000 0010 0100	BUS & R; NEXT|BUS[6-15]		TASK
000 0010 0101	BUS & R; BUS|ALUC0			TASK
000 0010 0110	BUS & R; MD BUS			TASK
000 0010 0111	BUS & CONST				TASK

000 0011 0000	BUS & R				BLOCK
000 0011 0001	BUS & R; BUS=0 ? NEXT|1		BLOCK
000 0011 0010	BUS & R; SH<0 ? NEXT|1			BLOCK
000 0011 0011	BUS & R; SH=0 ? NEXT|1			BLOCK
000 0011 0100	BUS & R; NEXT|BUS[6-15]		BLOCK
000 0011 0101	BUS & R; BUS|ALUC0			BLOCK
000 0011 0110	BUS & R; MD BUS			BLOCK
000 0011 0111	BUS & CONST				BLOCK

000 0100 0000	BUS & R				L LSH 1
000 0100 0001	BUS & R; BUS=0 ? NEXT|1		L LSH 1
000 0100 0010	BUS & R; SH<0 ? NEXT|1			L LSH 1
000 0100 0011	BUS & R; SH=0 ? NEXT|1			L LSH 1
000 0100 0100	BUS & R; NEXT|BUS[6-15]		L LSH 1
000 0100 0101	BUS & R; BUS|ALUC0			L LSH 1
000 0100 0110	BUS & R; MD BUS			L LSH 1
000 0100 0111	BUS & CONST				L LSH 1

000 0101 0000	BUS & R				L RSH 1
000 0101 0001	BUS & R; BUS=0 ? NEXT|1		L RSH 1
000 0101 0010	BUS & R; SH<0 ? NEXT|1			L RSH 1
000 0101 0011	BUS & R; SH=0 ? NEXT|1			L RSH 1
000 0101 0100	BUS & R; NEXT|BUS[6-15]		L RSH 1
000 0101 0101	BUS & R; BUS|ALUC0			L RSH 1
000 0101 0110	BUS & R; MD BUS			L RSH 1
000 0101 0111	BUS & CONST				L RSH 1

000 0110 0000	BUS & R				L LCY 8
000 0110 0001	BUS & R; BUS=0 ? NEXT|1		L LCY 8
000 0110 0010	BUS & R; SH<0 ? NEXT|1			L LCY 8
000 0110 0011	BUS & R; SH=0 ? NEXT|1			L LCY 8
000 0110 0100	BUS & R; NEXT|BUS[6-15]		L LCY 8
000 0110 0101	BUS & R; BUS|ALUC0			L LCY 8
000 0110 0110	BUS & R; MD BUS			L LCY 8
000 0110 0111	BUS & CONST				L LCY 8

000 0111 0000	BUS & CONST;
000 0111 0001	BUS & CONST; BUS=0 ? NEXT|1
000 0111 0010	BUS & CONST; SH<0 ? NEXT|1
000 0111 0011	BUS & CONST; SH=0 ? NEXT|1
000 0111 0100	BUS & CONST; NEXT|BUS[6-15]
000 0111 0101	BUS & CONST; BUS|ALUC0
000 0111 0110	BUS & CONST; MD
000 0111 0111	BUS & CONST

001 0000 0000	BUS = 0
001 0000 0001	BUS = 0; BUS=0 ? NEXT|1
001 0000 0010	BUS = 0; SH<0 ? NEXT|1
001 0000 0011	BUS = 0; SH=0 ? NEXT|1
001 0000 0100	BUS = 0; NEXT|BUS[6-15]
001 0000 0101	BUS = 0; BUS|ALUC0
001 0000 0110	BUS = 0; MD BUS
001 0000 0111	BUS & ~CONST

001 0001 0000	BUS = 0					MAR ALU; 
001 0001 0001	BUS = 0; BUS=0 ? NEXT|1			MAR ALU; 
001 0001 0010	BUS = 0; SH<0 ? NEXT|1			MAR ALU; 
001 0001 0011	BUS = 0; SH=0 ? NEXT|1			MAR ALU; 
001 0001 0100	BUS = 0; NEXT|BUS[6-15]			MAR ALU; 
001 0001 0101	BUS = 0; BUS|ALUC0			MAR ALU; 
001 0001 0110	BUS = 0; MD BUS			MAR ALU; 
001 0001 0111	BUS & CONST				MAR ALU; 

001 0010 0000	BUS = 0					TASK
001 0010 0001	BUS = 0; BUS=0 ? NEXT|1			TASK
001 0010 0010	BUS = 0; SH<0 ? NEXT|1			TASK
001 0010 0011	BUS = 0; SH=0 ? NEXT|1			TASK
001 0010 0100	BUS = 0; NEXT|BUS[6-15]			TASK
001 0010 0101	BUS = 0; BUS|ALUC0			TASK
001 0010 0110	BUS = 0; MD BUS			TASK
001 0010 0111	BUS & CONST				TASK

001 0011 0000	BUS = 0					BLOCK
001 0011 0001	BUS = 0; BUS=0 ? NEXT|1			BLOCK
001 0011 0010	BUS = 0; SH<0 ? NEXT|1			BLOCK
001 0011 0011	BUS = 0; SH=0 ? NEXT|1			BLOCK
001 0011 0100	BUS = 0; NEXT|BUS[6-15]			BLOCK
001 0011 0101	BUS = 0; BUS|ALUC0			BLOCK
001 0011 0110	BUS = 0; MD BUS			BLOCK
001 0011 0111	BUS & CONST				BLOCK

001 0100 0000	BUS = 0					L LSH 1
001 0100 0001	BUS = 0; BUS=0 ? NEXT|1			L LSH 1
001 0100 0010	BUS = 0; SH<0 ? NEXT|1			L LSH 1
001 0100 0011	BUS = 0; SH=0 ? NEXT|1			L LSH 1
001 0100 0100	BUS = 0; NEXT|BUS[6-15]			L LSH 1
001 0100 0101	BUS = 0; BUS|ALUC0			L LSH 1
001 0100 0110	BUS = 0; MD BUS			L LSH 1
001 0100 0111	BUS & CONST				L LSH 1

001 0101 0000	BUS = 0					L RSH 1
001 0101 0001	BUS = 0; BUS=0 ? NEXT|1			L RSH 1
001 0101 0010	BUS = 0; SH<0 ? NEXT|1			L RSH 1
001 0101 0011	BUS = 0; SH=0 ? NEXT|1			L RSH 1
001 0101 0100	BUS = 0; NEXT|BUS[6-15]			L RSH 1
001 0101 0101	BUS = 0; BUS|ALUC0			L RSH 1
001 0101 0110	BUS = 0; MD BUS			L RSH 1
001 0101 0111	BUS & CONST				L RSH 1

001 0110 0000	BUS = 0					L LCY 8
001 0110 0001	BUS = 0; BUS=0 ? NEXT|1			L LCY 8
001 0110 0010	BUS = 0; SH<0 ? NEXT|1			L LCY 8
001 0110 0011	BUS = 0; SH=0 ? NEXT|1			L LCY 8
001 0110 0100	BUS = 0; NEXT|BUS[6-15]			L LCY 8
001 0110 0101	BUS = 0; BUS|ALUC0			L LCY 8
001 0110 0110	BUS = 0; MD BUS			L LCY 8
001 0110 0111	BUS & CONST				L LCY 8

001 0111 0000	BUS & CONST
001 0111 0001	BUS & CONST; BUS=0 ? NEXT|1
001 0111 0010	BUS & CONST; SH<0 ? NEXT|1
001 0111 0011	BUS & CONST; SH=0 ? NEXT|1
001 0111 0100	BUS & CONST; NEXT|BUS[6-15]
001 0111 0101	BUS & CONST; BUS|ALUC0
001 0111 0110	BUS & CONST; MD
001 0111 0111	BUS & CONST

010 0000 0000	
010 0000 0001	BUS=0 ? NEXT|1
010 0000 0010	SH<0 ? NEXT|1
010 0000 0011	SH=0 ? NEXT|1
010 0000 0100	NEXT|BUS[6-15]
010 0000 0101	BUS|ALUC0
010 0000 0110	MD BUS
010 0000 0111	BUS & CONST

010 0001 0000						MAR ALU; 
010 0001 0001	BUS=0 ? NEXT|1				MAR ALU; 
010 0001 0010	SH<0 ? NEXT|1				MAR ALU; 
010 0001 0011	SH=0 ? NEXT|1				MAR ALU; 
010 0001 0100	NEXT|BUS[6-15]				MAR ALU; 
010 0001 0101	BUS|ALUC0				MAR ALU; 
010 0001 0110	MD BUS					MAR ALU; 
010 0001 0111	BUS & CONST				MAR ALU; 

010 0010 0000						TASK
010 0010 0001	BUS=0 ? NEXT|1				TASK
010 0010 0010	SH<0 ? NEXT|1				TASK
010 0010 0011	SH=0 ? NEXT|1				TASK
010 0010 0100	NEXT|BUS[6-15]				TASK
010 0010 0101	BUS|ALUC0				TASK
010 0010 0110	MD BUS					TASK
010 0010 0111	BUS & CONST				TASK

010 0011 0000						BLOCK
010 0011 0001	BUS=0 ? NEXT|1				BLOCK
010 0011 0010	SH<0 ? NEXT|1				BLOCK
010 0011 0011	SH=0 ? NEXT|1				BLOCK
010 0011 0100	NEXT|BUS[6-15]				BLOCK
010 0011 0101	BUS|ALUC0				BLOCK
010 0011 0110	MD BUS					BLOCK
010 0011 0111	BUS & ~CONST				BLOCK

010 0100 0000						L LSH 1
010 0100 0001	BUS=0 ? NEXT|1				L LSH 1
010 0100 0010	SH<0 ? NEXT|1				L LSH 1
010 0100 0011	SH=0 ? NEXT|1				L LSH 1
010 0100 0100	NEXT|BUS[6-15]				L LSH 1
010 0100 0101	BUS|ALUC0				L LSH 1
010 0100 0110	MD BUS					L LSH 1
010 0100 0111	BUS & CONST				L LSH 1

010 0101 0000						L RSH 1
010 0101 0001	BUS=0 ? NEXT|1				L RSH 1
010 0101 0010	SH<0 ? NEXT|1				L RSH 1
010 0101 0011	SH=0 ? NEXT|1				L RSH 1
010 0101 0100	NEXT|BUS[6-15]				L RSH 1
010 0101 0101	BUS|ALUC0				L RSH 1
010 0101 0110	MD BUS					L RSH 1
010 0101 0111	BUS & CONST				L RSH 1

010 0110 0000						L LCY 8
010 0110 0001	BUS=0 ? NEXT|1				L LCY 8
010 0110 0010	SH<0 ? NEXT|1				L LCY 8
010 0110 0011	SH=0 ? NEXT|1				L LCY 8
010 0110 0100	NEXT|BUS[6-15]				L LCY 8
010 0110 0101	BUS|ALUC0				L LCY 8
010 0110 0110	MD BUS					L LCY 8
010 0110 0111	st[8*RSEL+BS]				L LCY 8

010 0111 0000	BUS & CONST;
010 0111 0001	BUS & CONST; BUS=0 ? NEXT|1
010 0111 0010	BUS & CONST; SH<0 ? NEXT|1
010 0111 0011	BUS & CONST; SH=0 ? NEXT|1
010 0111 0100	BUS & CONST; NEXT|BUS[6-15]
010 0111 0101	BUS & CONST; BUS|ALUC0
010 0111 0110	BUS & CONST; MD
010 0111 0111	BUS & CONST

011 0000 0000	BUS & S
011 0000 0001	BUS & S; BUS=0 ? NEXT|1
011 0000 0010	BUS & S; SH<0 ? NEXT|1
011 0000 0011	BUS & S; SH=0 ? NEXT|1
011 0000 0100	BUS & S; NEXT|BUS[6-15]
011 0000 0101	BUS & S; BUS|ALUC0
011 0000 0110	BUS & S; MD BUS
011 0000 0111	BUS & CONST

011 0001 0000	BUS & S				MAR ALU; 
011 0001 0001	BUS & S; BUS=0 ? NEXT|1		MAR ALU; 
011 0001 0010	BUS & S; SH<0 ? NEXT|1			MAR ALU; 
011 0001 0011	BUS & S; SH=0 ? NEXT|1			MAR ALU; 
011 0001 0100	BUS & S; NEXT|BUS[6-15]		MAR ALU; 
011 0001 0101	BUS & S; BUS|ALUC0			MAR ALU; 
011 0001 0110	BUS & S; MD BUS			MAR ALU; 
011 0001 0111	BUS & CONST				MAR ALU; 

011 0010 0000	BUS & S				TASK
011 0010 0001	BUS & S; BUS=0 ? NEXT|1		TASK
011 0010 0010	BUS & S; SH<0 ? NEXT|1			TASK
011 0010 0011	BUS & S; SH=0 ? NEXT|1			TASK
011 0010 0100	BUS & S; NEXT|BUS[6-15]		TASK
011 0010 0101	BUS & S; BUS|ALUC0			TASK
011 0010 0110	BUS & S; MD BUS			TASK
011 0010 0111	BUS & CONST				TASK

011 0011 0000	BUS & S				BLOCK
011 0011 0001	BUS & S; BUS=0 ? NEXT|1		BLOCK
011 0011 0010	BUS & S; SH<0 ? NEXT|1			BLOCK
011 0011 0011	BUS & S; SH=0 ? NEXT|1			BLOCK
011 0011 0100	BUS & S; NEXT|BUS[6-15]		BLOCK
011 0011 0101	BUS & S; BUS|ALUC0			BLOCK
011 0011 0110	BUS & S; MD BUS			BLOCK
011 0011 0111	BUS & CONST				BLOCK

011 0100 0000	BUS & S				L LSH 1
011 0100 0001	BUS & S; BUS=0 ? NEXT|1		L LSH 1
011 0100 0010	BUS & S; SH<0 ? NEXT|1			L LSH 1
011 0100 0011	BUS & S; SH=0 ? NEXT|1			L LSH 1
011 0100 0100	BUS & S; NEXT|BUS[6-15]		L LSH 1
011 0100 0101	BUS & S; BUS|ALUC0			L LSH 1
011 0100 0110	BUS & S; MD BUS			L LSH 1
011 0100 0111	BUS & CONST				L LSH 1

011 0101 0000	BUS & S				L RSH 1
011 0101 0001	BUS & S; BUS=0 ? NEXT|1		L RSH 1
011 0101 0010	BUS & S; SH<0 ? NEXT|1			L RSH 1
011 0101 0011	BUS & S; SH=0 ? NEXT|1			L RSH 1
011 0101 0100	BUS & S; NEXT|BUS[6-15]		L RSH 1
011 0101 0101	BUS & S; BUS|ALUC0			L RSH 1
011 0101 0110	BUS & S; MD BUS			L RSH 1
011 0101 0111	BUS & CONST				L RSH 1

011 0110 0000	BUS & S				L LCY 8
011 0110 0001	BUS & S; BUS=0 ? NEXT|1		L LCY 8
011 0110 0010	BUS & S; SH<0 ? NEXT|1			L LCY 8
011 0110 0011	BUS & S; SH=0 ? NEXT|1			L LCY 8
011 0110 0100	BUS & S; NEXT|BUS[6-15]		L LCY 8
011 0110 0101	BUS & S; BUS|ALUC0			L LCY 8
011 0110 0110	BUS & S; MD BUS			L LCY 8
011 0110 0111	BUS & CONST				L LCY 8

011 0111 0000	BUS & CONST;
011 0111 0001	BUS & CONST; BUS=0 ? NEXT|1
011 0111 0010	BUS & CONST; SH<0 ? NEXT|1
011 0111 0011	BUS & CONST; SH=0 ? NEXT|1
011 0111 0100	BUS & CONST; NEXT|BUS[6-15]
011 0111 0101	BUS & CONST; BUS|ALUC0
011 0111 0110	BUS & CONST; MD
011 0111 0111	BUS & CONST
