PDP-11 Devices
The PDP-11 bus, devices and their controls are described on a level
necessary to program them.

		            Although such old-fashioned devices are now quite
	                    obsolete, they still can teach important lessons.
								    Don Knuth

0 Bus and Interrupts

The bus connects CPU, memory and I/O devices by bidirectional lines.
These include 18 address lines, 16 data lines, and four interrupt
request lines.  CPU and devices initiate communication by requesting
bus mastership. If granted, the master activates the address lines in
order to read the addressed word, to write the addressed word or byte,
or to specify the interrupt vector.

Each device is wired to a request line which it activates to request an
interrupt. The lines are numbered from 0 to 3; the BR of a device is
defined as line number + 4. An interrupt is pending until the BR is
greater than the CPU's IPL. If so, the device is granted bus mastership
and uses it to address the interrupt vector. Then the request line is
deactivated, the CPU pushes PSW and PC, loads PC and PS from the
interrupt vector and switches to kernel mode--much like handling a trap
instruction. If the MMU is active, the address of the interrupt vector
is mapped to a bus address according to the data address space in
kernel mode. If more than one device activate an interrupt line at the
same time, the one wired to the higher numbered line is served first.
If they are wired to the same line, the one physically placed closer to
the bus link is selected. The CPU is interrupted only after it
completed the current instruction.

When a device requests the bus while transfering a block to/from memory,
the bus might be granted to late for the device. In that case the
"data late" error will be indicated by the device.

The eight general CPU registers are exceptional in that they are not
accessable through the bus but only via the panel, which is directly
connected to the CPU.

1 TM11/TU10 Magnetic Tape Sub System

The TM11 device controls up to eight TU10 magnetic tape drives.  The
1/2" reel-to-reel tape used to be the standard tape from their
introduction 1953 until around 1984, when it was replaced by cassette
tapes (1/4" or 1/8" wide).

Two reflecting markers on the tape indicate begin and end of tape
(BOT/EOT). The data is recorded in a sequence of one or more files.  A
file in turn is a sequence of blocks, which are separated by interblock
gaps (0.6 inch length). A block is a sequence of bytes. The size of a
block ranges from one to 2^16 bytes, typically from 500 to 2000 bytes.
The end of file is indicated by an EOF mark.

The interblock gaps are used by the drive to speed up the tape before
reading the next block and to slow down the tape afterwards. If
quiescent, the tape is positioned at a gap, never inside a block.

TU10 supports 9-track-tapes at the density of 800 bits per inch (BPI)
and 7 track tapes at 200 and 556 BPI. Because of the way the data is
encoded on the tape, "bits per inch" also means "bytes per inch".
9-track-tapes encode 8-bit bytes and 7-track-tapes encode 6-bit bytes.
A parity bit for each byte and a CRC bit pattern for each block secures
the data, thus enabling the system to correct one bit errors and to
detect two bit errors in a block. A tape is usually 2400' long.

The tape has to be mounted manually and is then loaded by the drive,
that is, the tape is positioned at the gap before the first block,
which is also known as the load point.

The I/O commands are (a and n are specified in device registers):

read:   Copy a block from tape to memory at [a, a+n). If the block is
	larger, copy the first n bytes and indicate an error. In any
	case, position the tape after the block. If a mark (EOF, EOT)
	is read instead of a block, copy nothing, position the tape
	after the mark, indicate the mark in the status register and
	indicate an error.

write:  Copy a block from memory at [a, a+n) to tape. Even if EOT is
	reached, try to write on the remaining space before physical
	end of tape.  The tape is positioned after the new block.

mark:   Write an EOF mark, even if EOT is reached there is always enough
	space to write an EOF mark.

The I/O control commands include:

rewind:	move the tape to the load point.

seek n: skip forward respective backward n blocks or until a mark is
	reached, whichever comes first (n is specified in a device
	register). If a mark is reached, indicate an error.
	The tape moves at a speed of 45" per seconds.

unload: unwind the tape from the drive's reel to the tape's reel.

1.0 TM11 Registers
1.0.0 Status Register		(MTS; at 0772520)
The MTS shows the state of the device and the current drive.  The
meanings of the bits are:

Bit	Meaning
15	The last command given is illegal because
	- the device is busy executing the previous command, or
	- tried to write onto a tape beeing write locked
	- The drive is not attached to the controller
14      at EOF
13      Cyclic Redundancy Check (CRC)
12      Parity check
11      Data Late
10      at EOT
9	block is larger than memory buffer
8	bad tape error
7	memory does not exist
6	drive is online
5	at BOT
4	this is a 7 track tape
3	settling down (in an interblock gap)
2	write locked, that is, the write enable ring is not applied to the
	reel
1	tape is rewinding
0	unit ready

1.0.1 Status and Control Register (MTCS; at 0772522)
The MTCS encodes and starts a command and shows the state of the command.
The meaning of the command (c) and status (s) bits are:
Bit	Meaning
15    s	Error occurred, see MTS for reason
14-13 c	set density, 1=200, 2=556, 3=800 BPS
12    c reset the device
11    c set parity
10-8  c drive number
7     s last command is done
6     c enable interrupts
5-4   c highest two bits of bus address
3-1   c	command, encoded as: 0=unload, 1=read, 2=write, 3=mark,
	4=seek forward, 5=seek backward, 6=write with extra gap,
	7=rewind
0     c execute the command as specified in MTCS, MTC and MTA.

1.0.2 Count Register		(MTC; at 0772524)
      Bus Address Register	(MTA; at 0772526)

During the execution of an I/O command, the MTC holds the complement of
the number of bytes to be transfered and the MTA holds the bus address
of the next byte to be transfered. Before an I/O command is issued,
both registers need to be written to by the CPU. They are then
incremented by the TM11 for each byte transfered.

During the execution of seek commands, the MTC holds the complement of
the number of blocks left to be skipped. As with I/O commands, it is
to be initialized by the CPU and will be incremented by TM11 for each
block skipped.

1.1 BR and interrupt vector.
If interrupts are enabled in the MTCS register, TM11 interrupts at
224 with BR=5 whenever a command is done.
2 RK11/RK05 Removable Disk Subsystem

The RK11 device controls up to eight RK05 disk drives. An RK05 disk has
two surfaces with 203 tracks each. A track holds twelve 512-byte
blocks.  The RK11 supports read/write commands one at a time, but seek
commands can be run concurrently on different drives. The data transfer
rate is about 400000 bytes/second and the average seek time 70 ms.

The data to be transferred with a single I/O command start at block
boundary and end at word boundary, possibly spanning more than one
consecutive blocks.

2.0 I/O Registers
2.0.0 Drive Status (RKDS; at 0777400)
The RKDS reports the status of the current drive. The readonly bits are
assigned as:

Bit	Meaning
15-13	drive number
12	drive power low,
11	always on, identifies the drive to be model RK05
10	drive unsafe
9	seek incomplete
8	block ok
7	drive ready
6	read/write/seek ready
5	write locked
4	positioned on block requested in RKDA
3-0	current block number

2.0.1 Error (RKER; at 0777402)
The RKER reports error conditions. The readonly bits are assigned as:

Bit	Meaning
15	drive error (see RKDS for further information)
14	overrun
13	write command but drive is write locked
12	seek error
11	illegal command, RKCS
10	memory does not exist
9	data late, i.e., bus was granted too late to the controller
8	timeing error
7	drive does not exist
6	track does not exist
5	sector does not exist
1	checksum error
0	write error

2.0.2 Control and Status (RKCS; at 0777404)
Bit	Meaning
15	error occurred
14	hard error
13	seek complete
11	inhibit increment (used for formatting)
10	format
8	stop on soft error
7	command is done
6	interrupt when done
5-4	high bits of bus address
3-1	command, encoded as: 0=reset controller,
	1=write, 2=read, 3=write and check,
	4=seek, 5=read and check, 6=reset drive, 7=set write lock
0	execute the command as specified in RKCS, RKWC, RKBA and RKDA.

2.0.3 Word count (RKWC at 0777406)
The complement of the number of words to be transferred.
RK11 increments the RKWC while transferring.

2.0.4 Bus Address (RKBA at 0777410)
The low 16 bit of the bus address which must be even.
RK11 increments the bus address while transfering.

2.0.5 Disk Address (RKDA at 0777412)
The disk address is encoded as:
Bit	Meaning	values
15-13	drive 	[0, 7)
12-5	track	[0, 203)
4	head	[0, 2)
3-0	block   [0, 12)

2.1 Bus request number and interrupt vector entry:
The BR of the RK device is 5, and its vector entry is at 0220.

3 The KL11 serial line controller.
The KL11 attaches to a teletype (TTY) via a 20mA current loop serial
line interface (110 baud, two stop bits, 7 bits per character). The TTY
is a keyboard and a printer connected to a serial line. The most common
model is the Automatic Send and Recieve 33 (ASR 33) with printing speed
at 10 characters per second and upper case only characters. Other
models connected to the KL11 support the complete ASCII character set.
The TTY serves as the PDP-11 console.

3.0 KL11 I/O registers
The KL11 provides two registers for input and two registers for
output.  The Kl11 places a character recieved from the keyboard into
the input buffer (IBUF at 0777562).  The CPU writes a character to be
printed into the output buffer (OBUF at 0777566).  The input command and
status register (ICSR at 0777560) and the output CSR (OCSR at 0777564)
both have a done bit (bit 7) and an interrupt enable bit (bit 6).
Whenever a character is recieved from the keyboard, KL11 places it into
the IBUF and sets the done bit in the ICSR.  The input done bit is
cleared when the CPU reads the input buffer.  When the CPU writes a
character to the output buffer, KL11 clears the output done bit, sends
the character to the printer and sets the done bit when the character
is transmitted.  After reset the input done bit is off and the output
done bit is on.  When the interrupt enable bit is set, the KL11 will
interrupt at 60 when a character is recieved respective at 64 when a
character is transmitted.  The BR is 4.

4 The KW11 line frequency clock.
The CSR at 0777546 has two bits implemented, bit 7, the done bit, and
bit 6, the interrupt enable bit. When bit 6 is set, the clock
interrupts at 0100 at every tick. The clock is synchronized by the
frequency of the power line, that is, it ticks 50 or 60 times a
second. The BR is six.
