
	           wau - UNIBUS / ATA (IDE) adapter

*******************************************************************************
* Copyright (c) 1999 by Dmitry Pryanishnikov, Dnipropetrovsk, Ukraine.        *
*                                                                             *
* Permission is granted to any individual or institution to use, copy,        *
* or redistribute this software so long as all of the original files          *
* are included, that it is not sold for profit, and that this copyright       *
* notice is retained.                                                         *
*                                                                             *
* This project has been provided 'as is'. Any expressed or implied warranties * 
* are disclaimed. In no event shall I be liable for any direct, indirect or   *
* other damages arising out of the use of this project, etc. However I am     *
* interested in feedback from the users of this technology, and any           *
* suggestions are welcome.                                                    *
*******************************************************************************

 This archive consists of the following files:
 
 wau1420.sch    - ATA <=> UNIBUS adapter schematic diagram (PCAD v4.5),
                  variant for Soviet PDP-11 clone SM1420
 wau1420.ps     - above diagram in Postscript format
 wau1700.sch    - ATA <=> UNIBUS adapter schematic diagram (PCAD v4.5),
                  variant for Soviet VAX-11/730 clone SM1700
 wau1700.ps     - above diagram in Postscript format
 wabrom.mac     - primary bootstrap from ATA HDD for PDP-11 source text
 wabrom.lst     - assembly listing of above bootstrap

  This device is an adapter (not a controller) which provides 4 completely
independent ATA (IDE) channels for a UNIBUS machine. We have tested it with
Soviet PDP-11 clone SM1420 and Soviet VAX-11/730 clone SM1700.
  Channels are wired using common data and address buses and separate
device select wires. Logical limit for the number of devices is 8 (4 pairs
of master/slave for each channel), but it would be very difficult to place 8
connectors on 18-inch cable. I recommend to AVOID use of slave units if
possible (therefore, it is better to wire 2 connectors for masters on
separate channels then wire them in parallel and use master/slave pair).
Use of master/slave pair prevents simultaneous work of drives and may
cause incompatibility between drives of different manufacturers.
Adapter provides generic ATA interface, and therefore it should be
possible to connect any ATA device to it (for example, CD-ROM),
but appropriate software not yet written by me.
   I/O page address space for adapter has size of 400 (octal) bytes and
can be assigned by jumpers starting at any 400 (octal) boundary. Adapter
does not distinguish byte vs. word references to it's addresses and always
reads/writes full 16-bit word. Bits 8-15 of data are ignored during writes
to 8-bit ATA registers and unpredictable (contain a junk) during reads.
First 200 (octal) bytes of address space mapped to UV EPROM contents
(DD27 contains a low-order byte for each word, DD28 contain high-order
one). So we have 64 words which can be used for primary bootstrap from
ATA HDD on PDP-11. For VAX-11 variant of adapter those ICs could be omitted.
Rest 200 (octal) bytes of address space are logically broken to 4 zones
40 (octal) bytes each (zone per ATA channel). Each zone has the following
layout:

Offset
from the start
of zone (octal)

      high-order byte |  low-order byte

      +----------------------------------------+
+0    | Reserved      |   Adapter CSR          |
      |----------------------------------------|
+2    | Reserved for DMA co-adapter CSR        |
      |----------------------------------------|
+4    | Reserved for DMA address register      |
      |----------------------------------------|
+6    | Reserved for DMA word count            |
      |----------------------------------------|
+10   |          Reserved                      |
      |----------------------------------------|
+12   |          Reserved                      |
      |----------------------------------------|
+14   | Reserved      | Alternate status (r/o) |
      | Reserved      | Device control (w/o)   |
      |----------------------------------------|
+16   |          Reserved                      |
      |----------------------------------------|
+20   |           Data (r/w)                   |
      |----------------------------------------|
+22   | Reserved      | Error (r/o)            |
      | Reserved      | Features (w/o)         |
      |----------------------------------------|
+24   | Reserved      | Sector Count (r/w)     |
      |----------------------------------------|
+26   | Reserved      | Sector Number (r/w)    |
      |----------------------------------------|
+30   | Reserved      | Cylinder Low (r/w)     |
      |----------------------------------------|
+32   | Reserved      | Cylinder High (r/w)    |
      |----------------------------------------|
+34   | Reserved      | Device/Head (r/w)      |
      |----------------------------------------|
+36   | Reserved      | Status (r/o)           |
      | Reserved      | Command (w/o)          |
      +----------------------------------------+

     Adapter CSR layout:

        +-----------------------------------------------+
        | INT | IE  | DTM | NDM |  0  |  0  |  0  | MD1 |
        +-----------------------------------------------+

INT (r/o) - state of IRQ line on appropriate channel; if both this and
            also bit 6 (IE) of this register are set, then adapter asserts
            interrupt (interrupts aren't triggered any way, so ISR must
            clear IE or INT (reading Status Register per ATA std.) to
            prevent multiple interrupts).
IE  (r/w) - interrupt enable bit, cleared by BUS INIT L
DTM (r/o) - "dead time" indication, see below
NDM (r/o) - "DMA coadapter not installed". Always set to 1 by this
            version of adapter
    MD1   - reserved for faster PIO modes (PIO mode >0).
	    Cleared by BUS INIT L.

     Rest of registers are just mapped to correspondent ATA registers,
see ATA standards for description.
     First ATA channel occupies address zone at (base+200) (octal), and
vector (base+0), second - address (base+240) and vector (base+4), third -
address (base+300) and vector (base+10) and fourth - address (base+340)
and vector (base+14). We are using mainly 171000 (octal) as adapter's
base address and 120 (octal) as a base vector. Use jumpers A12-A8 to set
base address (connecting together upper on diagram pin pair will set
address bit to "1") and V8-V4 to set base vector (same about "0"/"1").

 Integrated Circuits:

DD1...DD7       Soviet 559IP3
                (four bus transmitters/receivers per package, not sure
                about DEC equivalent - check 8641)
DD8,DD9         SN7432
DD10...DD13     Soviet 559IP2
                (four bus receivers per package, not sure about DEC
		equivalent - check 8881)
DD14...DD18     i8282
DD19,DD20       SN7404
DD21,DD22       SN74123
DD23...DD25     SN74LS74
DD26            SN7430
DD27,DD28       i2716
DD29,DD30       SN74153
DD31...DD33     SN7408
DD34            SN74LS259
DD35...DD38     SN7400
DD39            SN7420
DD40            SN74LS138
DD41            SN74LS148
DD42            i8224
DD43            SN74LS245
DD44            SN74LS164
DD45            SN7402
DD46            SN7477
DD47            SN74153
DD48            SN74LS259
DD49,DD50       SN74LS373

     Quartz oscillator frequency is 16 MHz.

     The part of adapter which includes DD21,DD22,C1...C4,R1,R7,R8,R11,R12
is useful in rare cases of use some 'design-broken' HDDs which may
require some minimum delay between the commands. We have found only one
such HDD, namely, IBM WDA-L42 (40Mb). We looked at Linux IDE HDD driver
and found that problem is known to Linux people also (from ide.c):
+++++
#if (DISK_RECOVERY_TIME > 0) 
/*
 * For really screwy hardware (hey, at least it *can* be used with Linux)
 * we can enforce a minimum delay time between successive operations.
 */
-----
One could test his drive for this defect by reading, e.g., HDD block 0
in tight loop (it was possible to detect it even on PC/AT 486 reading
disk via int 13). So I have decided to use combined hardware/software
workaround for such drives. Every time program writes/reads one of command
block registers (asserting appropriate CS1FX signal) it starts appropriate
monovibrator, and software waits for deassertion of DTM bit in adapter CSR
before issuing the next command. During experiments with WDA-L42 it was
determined that safe delay between the commands (recovery time) for this
drive should be approximately 100us, so one should connect R=10kOhm,
C=68nF to IC for channel which is to be used with WDA-L42. For the most
cases capacitors can be omitted (resistors can be R=10kOhm), or even all
above details may be removed (in this case, DD30/(3-6) should be connected
to GND).

   ICs DD22,DD23 may be omitted in case primary bootstrap on adapter
(or should I say Boot ROM?) not required.

   All ICs series SN74LS can (and even recommended to) be replaced with
appropriate SN74ALS, SN74 - by SN74LS/ALS (except DD21,DD22 where RC
should be different for that series). Registers i8282 were used only
due to pretty pinout and can be replaced with SN74LS374 (requires pinout
change).


Appendix. Adapter <-> ATA HDD cable wiring example for the case of 2
"master" drives on channels #0 and #1 (those connectors are standard ATA
40-pin "female" sockets).

Adapter's             Signal           Connector for   Connector for
connector             name             channel #0      channel #1
(X3 for wau1420
or X5 for wau1700)

A1                      RESET-              1               1
B1                      Ground              2               2
A2                      DD7                 3               3
B2                      DD8                 4               4
A3                      DD6                 5               5
B3                      DD9                 6               6
A4                      DD5                 7               7
B4                      DD10                8               8
A5                      DD4                 9               9
B5                      DD11               10              10
A6                      DD3                11              11
B6                      DD12               12              12
A7                      DD2                13              13
B7                      DD13               14              14
A8                      DD1                15              15
B8                      DD14               16              16
A9                      DD0                17              17
B9                      DD15               18              18
A10                     Ground             19              19
B10                     DMARQ #0           21
A11                     Ground             22              22
B11                     DIOW-              23              23
A12                     Ground             24              24
B12                     DIOR-              25              25
A13                     Ground             26              26
B13                     IORDY              27              27
A14                     DMACK- #0          29
B14                     Ground             30              30
A15                     INTRQ #0           31
B15                     IOCS16-            32              32
A16                     DA1                33              33
B16                     DA0                35              35
A17                     DA2                36              36
B17                     CS1FX- #0          37
A18                     CS3FX- #0          38
B18                     Ground             40              40
A19                     DMACK- #1                          29
B19                     DMARQ- #1                          21
A20                     INTRQ #1                           31
B20                     CS1FX- #1                          37
A21                     CS3FX- #1                          38
B21                     Ground             40              40

   Wiring for channels #2 and #3 should be evident from schematic diagram.
To wire master/slave pair one should connect pins with the same numbers of
2 connectors; don't connect signals not listed in table to adapter - they
can be used for inter-drive communication within master/slave pair.

dmitry@digital.dp.ua
