BMUX Burroughs Polling Protocol MULTIPLEXOR SAGE division of GENERAL SCIENTIFIC CORPORATION 966 Hungerford Dr. Rockville, Md. 20850 301-340-2773 TECHNICAL MANUAL TABLE OF CONTENTS BMUX USAGE INFORMATION Startup 1-1 Console Commands 1-1 Initialization of Operations 1-2 Status Information 1-2 Suspension of Operations 1-2 Exit Procedure 1-2 Configuration of Multiplexor 1-2 Console messages to a defined port 1-4 Software Problems 1-4 BMUX CONSOLE COMMAND SUMMARY PROCede 2-1 HALT 2-1 MESSage## 2-1 STATistics 2-1 EXIT 2-2 SOFTWARE PERFORMANCE REPORT SPR 3-1 HARDWARE Processor option straping 4-1 Ports 0 to 3 option strapping 4-3 Ports 4 to 7 option strapping 4-5 Ports 8 to 11 option strapping 4-6 Ports 12 to 15 option strapping 4-7 Ports 16 to 19 option strapping 4-8 Ports 20 to 23 option strapping 4-9 Disk Controller 4-10 Disk Drive 4-11 Cable Wiring 4-12 BMUX MAINLINE LOGIC DOCUMENTATION Mainline Logic 5-1 Interrupt Service Logic 5-2 Configuration Logic 5-2 SYSTEM SOFTWARE EQUATES SF1 (Source File 1) 6-1 SUPPORT SUBROUTINE DOCUMENTATION BTIME 7-1 GBUFC 7-1 SAVE 7-1 STOR 7-2 READ 7-2 TABLE OF CONTENTS WRITE 7-2 FORCE 7-2 FNDCOM 7-2 JORSTA 7-3 REBUF 7-3 GPCBDA 7-4 CONWRI 7-4 PCBSET 7-4 BOMB 7-4 CONFDP 7-4 CONCMD 7-4 HLTPRO 7-5 START 7-5 STDISP 7-5 MSG 7-5 PROXIT 7-5 DISTAT 7-6 CONCPY 7-6 Canned Messages 7-6 SF20 Module 8-1 SF30 Module 8-1 SF40 Module 8-2 SF50 Module 8-3 SF60 Module 9-1 BMUX DATA STRUCTURE DOCUMENTATION CR1-CR5 10-1 CR6 10-1 CRTAB 10-1 TRKSRP 10-1 CONFLG 10-1 TRAPA 10-1 TRDQ2 10-1 TSP-TEP 10-1 PSP-PEP 10-2 SPTR-PEN 10-2 PRPTR-TWPTR 10-2 HALTFL 10-2 INIFLG 10-2 STDFLG 10-2 SPFUN 10-2 CCMD 10-2 ISRTAB 10-2 DA1-DA8 10-2 TABLE OF CONTENTS ISRSAV 10-2 CONSAV 10-3 RCSRA-XBUFA 10-3 RCSRI-XBUFI 10-3 WAIT1-NEWSEC 10-3 PAT 10-3 CUMTAB 10-3 PCB 10-3 POLTAB 10-3 TTYPE 10-4 BRTAB 10-4 PCBDAT 10-4 TWBPCB 10-4 RVITAB-JORST 10-4 BMUX USAGE INFORMATION General Scientific Corporation Rockville, Md. 1. STARTUP The BMUX software is normally booted automatically when the system is started by either a power-up sequence or the depression and lifting of the "RUN" switch on the LSI-11. If, for some reason, the console terminal shows a period (.) on the current line, it is probably awaiting user response to the RT-11 console prompt. in this case, enter: RUN BMUX and depress the RETURN key. This will start the BMUX software. When the start sequence has run, regardless of the cause of its initiation, the BMUX software will announce its readiness by displaying the message: **** BMUX INITIALIZED TO HALT MODE **** indicating that the console is functional and the software is ready for operation. 2. CONSOLE COMMANDS The console terminal (Port 2) can asynchronously access both the Burroughs and the multiplexor's control interface. If a console command entry is desired, the user of the console terminal must start the current line with two Control-V's, created by simultaneously depressing the control and "V" keys. The command must immediately follow the second control-V and be one of the following: A. PROC Initiates multiplexor operations B. STAT Generates a status display for the defined trunk(s) and ports C. MESS ## Sends the remainder of the line to Port ##, if defined D. HALT Temporarily suspends multiplexor operations by preventing input by the ports E. EXIT (must be preceeded by the HALT command) causes the multiplexor software to release control to RT-11 (generally used to run the configuration program) Invalid console command entry will be denoted by the appearence of either "!!!!" (invalid command) or "MESS ??" (invalid port number). in the case where the "EXIT" command is entered but not preceeded by the "HALT" command, it will be ignored. 3. INITIALIZATION OF OPERATIONS Enter the "PROC" console command to begin communications operations between the port terminals and the Burroughs mainframe. 4. STATUS INFORMATION To examine the status of various ports and the trunk(s), use the "STAT" console command. Remember that the display values for traffic (TFC) and errors (ERR) are "wrap-around" counts. This means that an accurate traffic and error count over any timeframe is the absolute difference between the last set of values and the current ones. This also applies to the values displayed on the "LINK:" line at the end of the display. refer to the BMUX console command summary for display element descriptions. 5. SUSPENSION OF OPERATIONS If it is desired to temporarily block all terminal access to the Burroughs cpu, the "HALT" console command will return the software to a pseudo-halt-mode state similar to that immediately after startup. In this state, the read buffers are still active, but port inputs (except for the console) are blocked. If a port terminal user attempts data entry, the terminal will sound a bell or similar audible alarm. 6. EXIT PROCEDURE If it is desired that the software be completely initialized to the startup state, use the "HALT" and "EXIT" console commands, in that order. the software will then exit to RT-11 control. Refer to the startup procedures for restarting the BMUX software. 7. CONFIGURATION OF MULTIPLEXOR To change the configuration of the multiplexor, use the EXIT sequence detailed above. when under RT-11 control, enter: RUN BCONF and depress the RETURN key. The configuration program will now run. The use of this portion of the software will result in the destruction of the prior configuration. All ports must be defined, including the trunk(s). The procedure of multiplexor configuration will require verification that the prior configuration is to be destroyed. The user responds yes (Y) or no (N) to the destruction message. A response of no (N) will cause an exit without distrubing the prior configuration. If a yes (Y) response is entered, the program will commence prompting for the trunk and port parameters. At least one trunk must be defined, or the software will reject definition of any ports. Port 2, the console, must be defined; or the BMUX software cannot be started and operations cannot commence. A trunk definition requires definition of the following: A. Two-character poll address B. 6-character owner name C. 5-character site name D. 3-digit decimal line buffer size (1-160. characters) A port definition requires definition of the following: A. Two-character poll address B. 6-character owner name C. 5-character site name D. 3-digit decimal line buffer size (1-160. characters) E. 2-digit decimal carriage return delay (00-20 null characters) F. 2-digit decimal form feed delay (00-20 null characters) G. A yes (Y) or no (N) response to cause input characters to be echoed by the multiplexor There are two special input conditions that can be entered for the poll address prompt: A. Two control-V characters (created by simultaneously depressing the control and V keys) cause the current port/trunk to be "skipped", with definition proceeding to the next port/trunk (if any). B. A control-V and an "E" character terminates the configuration process by setting the remaining ports to an undefined state. After the configuration has been prepared, re-enter the BMUX software as shown in the startup information. This process may be done as often as desired, but it disables the operational capability of the multiplexor during the configuration procedure. 8. CONSOLE MESSAGES TO A DEFINED PORT If the user of the console terminal wishes to send a message to the user of a defined port, the "MESS" command can be utilized (as opposed to using the Burroughs message capability) by entering the message line in the following format: (control-V)(control-V)MESS ## (message as desired) Where the ## is the port number assigned to the port as shown in the "STAT" display. this capability is convenient in that it removes the processing of the message from the Burroughs mainframe. It is usable only within the set of ports defined by the "STAT" display. 9. SOFTWARE PROBLEMS If a software problem should occur, the logic in the multiplexor should indicate the situation by displaying a "**** BMUX ABORT ****" message upon the console terminal. If this happens, certain information should be acquired from the system and the BMUX system problem report (SPR) should be prepared as completely as possible. When this type of situation occurs, the console terminal will then be under DEC "ODT" control. In this state, the registers ($0, $1, $2, $3, $4, $5, and $6) can be examined by entering the register name followed by a "/" character (ex: $0/ ). When the value has been copied, depress the return key and go on to the next register. When all the registers have been examined and their values entered on the spr form, enter the $6 value, followed by a "/" character. This will be some number between 0 and 1000 under normal abort conditions. when the value displayed by the initial "/" character has been copied onto the SPR form, depress the line-feed (LF) key to get the next value (displayed in the form: address/value). repeat this process until the address value is 1000. Refer the form to the appropriate point of contact for resolution of the cause of the abort condition. BMUX CONSOLE COMMANDS SUMMARY ============================= Console commands for the BMUX software can be requested at the console port (PORT NUMBER 02) only!! The format of all console commands is as follows: (control-V) (control-V)command(RETURN) where: (Control-V) is the simultaneous depression of the control and V keys (RETURN) is the depression of the return (or carriage return) key COMMAND is a four-character BMUX command from the following table: PROC The processing of I/O will now begin or resume HALT All inputs (except console commands) will suspend MESS ## (msg) The message (msg) (whatever was typed) will be sent to port ## STAT A table of information regarding all ports and trunks defined will be displayed on the console. The format of the individual table line is as follows: ## PP TT OWNER LOC TFC ERR STS RWQ where: ## is the BMUX port number PP is the port's two-character ASCII poll address TT is the trunk BMUX port number to which the port's input and output will 'flow' to and from the host OWNER is the six-character owner or user name LOC is the five-character location for the port TFC is the count of lines sent/received on the port ERR is the count of input errors for the port or any errors in trunk I/O or protocol handling STS is the port's status indication with bit values: 1 Input complete 2 Output complete 4 Need an input buffer 8 Statistics count ready 16 Console command input R Appears if an input buffer is active for the port W Appears if an output buffer is active for the port Q Appears if there is port input queued for the host The last line of the display contains information specific to the trunk line(s). This line is labeled: LINK: The values contained in the line are: PRO ERR Count of protocol errors detected POL ADR Count of invalid poll addresses received CONTENTION 1 Trunk 1 (port #0) is in contention 2 Trunk 2 (port #2) is in contention EXIT If preceeded by a 'HALT' command, causes the BMUX program to exit to RT-11 control. NOTE If entered inadvertantly, type: RUN BMUX(return) to re-enter the BMUX program. Please report any difficulties with this software via the BMUX System Problem Report (SPR) form. GENERAL SCIENTIFIC CORPORATION BMUX PROBLEM REPORT ODT ADDRESS:___________________ RELEASE:______ DATE:______ REPORTING: PERSON:_____________________ COMPANY:__________________ =================================================================== PROBLEM SYMPTOMS:__________________________________________________ ___________________________________________________________________ ___________________________________________________________________ ___________________________________________________________________ ___________________________________________________________________ ___________________________________________________________________ =================================================================== REGISTERS: STACK: R0_____________________ >>>>>>________________________ ^ R1_____________________ ^ ________________________ ^ R2_____________________ ^ ________________________ ^ R3_____________________ ^ ________________________ ^ R4_____________________ ^ ________________________ ^ R5_____________________ ^ ________________________ ^ R6_________________STACK>>> ^ ________________________ ________________________ ________________________ ________________________ ________________________ ________________________ ________________________ HARDWARE CONFIGURATION OF BMUX The BMUX Multiplexor is designed about the LSI-11 processor, manufactured by Digital Equipment Corporation. The BMUX components are arranged in a 4 x 8 backplane arrangement as follows: PROCESSOR LSI-11 ------------------------- ------------------------- PORTS 0,1,2,3 DLV11J DISK CONTROLLER ------------------------- ------------------------- PORTS 4,5,6,7 DLV11J PORTS 8,9,10,11 ------------------------- ------------------------- PORTS 16,17,18,19 PORTS 12,13,14,15 ------------------------- ------------------------- PORTS 20,21,22,23 MEMORY ------------------------- ------------------------- SPARE SPARE ------------------------- ------------------------- SPARE SPARE ------------------------- ------------------------- SPARE SPARE ------------------------- ------------------------- The placement of the component boards is critical and should not be arbitrarily relocated. The jumpers on the processor board should be configured as follows: PROCESSOR OPTION JUMPERS JUMPER STATUS FUNCTION ______ ______ ________________________________________________ W1 R Resident memory bank 1 not selected W2 R Resident memory bank 2 not selected W3 R Event line (LTC) interrupt enabled W4 I Processor controlled memory refresh disabled W5 R Power up mode 0 selected W6 R W7 - Factory configured bias voltage (do not change) W8 - Factory configured bias voltage (do not change) W9 I Disable reply from resident memory W10 R Disable reply from resident memory during refres W11 R Disable on board memory select SERIAL LINE INTERFACE JUMPER OPTIONS Lines 0 to 3 Label Jumper Function Implemented _____ ___________ ________________________________________ A12 X to 1 This arrangement of jumpers A5-A12 A11 X to 1 implements the octal base device ad- A10 X to 1 dress 17650X, which is the assigned A9 X to 1 address for channel 0 RCSR. The least A8 X to 0 significant digit is decoded on the mod- A7 R ule during operation to address one of A6 I four SLU device registers as follows A5 X to 0 X=0,RCSR X=2,RBUF X=4,XCSR X=6,XBUF C1 X to 1 These jumpers are used to enable C2 X to 1 channel 3 for console operation. Base address must be 176500 (factory con- figured), 176540, or 177500 for the console. BREAK No Jumper No response to break V7 I This arrangement of jumpers V5-V7 V6 I implements the octal "base" vector of V5 X to 0 300 with channel 3 at 60 and 64 CHANNEL 0 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 0 Parity generation and detection CHANNEL 1 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 0 Parity generation and detection CHANNEL 2 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 3 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection N0-3 X to 3 EIA RS-423 AND RS-232C M0-3 X to 3 EIA RS-423 AND RS-232C R10 22 kohm Channels 0 and 1, slew rate of 2usec R23 22 kohm Channels 2 and 3, slew rate of 2usec BAUD RATE Port Jump Description 0 to N Trunk 0 set to 9600 bps 1 to N Trunk 1 set to 9600 bps 2 selected remotely 3 selected remotely SERIAL LINE INTERFACE JUMPER OPTIONS Lines 4 to 7 Label Jumper Function Implemented _____ ___________ ________________________________________ A12 X to 1 This arrangement of jumpers A5-A12 A11 X to 1 implements the octal base device ad- A10 X to 0 dress 17564X, which is the assigned A9 X to 1 address for channel 0 RCSR. The least A8 X to 1 significant digit is decoded on the mod- A7 I ule during operation to address one of A6 R four SLU device registers as follows A5 X to 1 X=0,RCSR X=2,RBUF X=4,XCSR X=6,XBUF C1 X to 0 These jumpers are used to disable C2 X to 0 channel 3 for console operation. BREAK No Jumper No response to break V7 I This arrangement of jumpers V5-V7 V6 I implements the octal "base" vector of V5 X to 1 340 CHANNEL 0 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 1 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 2 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 3 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection N0-3 X to 3 EIA RS-423 AND RS-232C M0-3 X to 3 EIA RS-423 AND RS-232C R10 22 kohm Channels 0 and 1, slew rate of 2usec R23 22 kohm Channels 2 and 3, slew rate of 2usec SERIAL LINE INTERFACE JUMPER OPTIONS Lines 8 to 11 Label Jumper Function Implemented _____ ___________ ________________________________________ A12 X to 1 This arrangement of jumpers A5-A12 A11 X to 1 implements the octal base device ad- A10 X to 0 dress 17570X, which is the assigned A9 X to 1 address for channel 0 RCSR. The least A8 X to 1 significant digit is decoded on the mod- A7 I ule durRng operation to address one of A6 I four SLU device registers as follows A5 X to 0 X=0,RCSR X=2,RBUF X=4,XCSR X=6,XBUF C1 X to 0 These jumpers are used to disable C2 X to 0 channel 3 for console operation. BREAK No Jumper No response to break V7 I This arrangement of jumpers V5-V7 V6 I implements the octal "base" vector of V5 X to 1 340 CHANNEL 0 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 1 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 2 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 3 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection N0-3 X to 3 EIA RS-423 AND RS-232C M0-3 X to 3 EIA RS-423 AND RS-232C R10 22 kohm Channels 0 and 1, slew rate of 2usec R23 22 kohm Channels 2 and 3, slew rate of 2usec SERIAL LINE INTERFACE JUMPER OPTIONS Lines 12 to 15 Label Jumper Function Implemented _____ ___________ ________________________________________ A12 X to 1 This arrangement of jumpers A5-A12 A11 X to 1 implements the octal base device ad- A10 X to 0 dress 17574X, which is the assigned A9 X to 1 address for channel 0 RCSR. The least A8 X to 1 significant digit is decoded on the mod- A7 I ule during operation to address one of A6 I four SLU device registers as follows A5 X to 1 X=0,RCSR X=2,RBUF X=4,XCSR X=6,XBUF C1 X to 0 These jumpers are used to disable C2 X to 0 channel 3 for console operation. BREAK No Jumper No response to break V7 I This arrangement of jumpers V5-V7 V6 I implements the octal "base" vector of V5 X to 1 340 CHANNEL 0 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 1 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 2 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 3 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection N0-3 X to 3 EIA RS-423 AND RS-232C M0-3 X to 3 EIA RS-423 AND RS-232C R10 22 kohm Channels 0 and 1, slew rate of 2usec R23 22 kohm Channels 2 and 3, slew rate of 2usec SERIAL LINE INTERFACE JUMPER OPTIONS Lines 16 to 19 Label Jumper Function Implemented _____ ___________ ________________________________________ A12 X to 1 This arrangement of jumpers A5-A12 A11 X to 1 implements the octal base device ad- A10 X to 1 dress 17600X, which is the assigned A9 X to 0 address for channel 0 RCSR. The least A8 X to 0 significant digit is decoded on the mod- A7 R ule during operation to address one of A6 R four SLU device registers as follows A5 X to 0 X=0,RCSR X=2,RBUF X=4,XCSR X=6,XBUF C1 X to 0 These jumpers are used to enable C2 X to 0 channel 3 for console operation. BREAK No Jumper No response to break V7 I This arrangement of jumpers V5-V7 V6 I implements the octal "base" vector of V5 X to 1 340 CHANNEL 0 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 1 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 2 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 3 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection N0-3 X to 3 EIA RS-423 AND RS-232C M0-3 X to 3 EIA RS-423 AND RS-232C R10 22 kohm Channels 0 and 1, slew rate of 2usec R23 22 kohm Channels 2 and 3, slew rate of 2usec SERIAL LINE INTERFACE JUMPER OPTIONS Lines 20 to 23 Label Jumper Function Implemented _____ ___________ ________________________________________ A12 X to 1 This arrangement of jumpers A5-A12 A11 X to 1 implements the octal base device ad- A10 X to 1 dress 17604X, which is the assigned A9 X to 0 address for channel 0 RCSR. The least A8 X to 0 significant digit is decoded on the mod- A7 R ule during operation to address one of A6 R four SLU device registers as follows A5 X to 1 X=0,RCSR X=2,RBUF X=4,XCSR X=6,XBUF C1 X to 0 These jumpers are used to disable C2 X to 0 channel 3 for console operation. BREAK No Jumper No response to break V7 I This arrangement of jumpers V5-V7 V6 I implements the octal "base" vector of V5 X to 1 340 CHANNEL 0 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 1 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 2 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection CHANNEL 3 E X to 1 Even parity D X to 1 8 data bits S X to 0 1 stop bit P X to 1 No Parity generation and detection N0-3 X to 3 EIA RS-423 AND RS-232C M0-3 X to 3 EIA RS-423 AND RS-232C R10 22 kohm Channels 0 and 1, slew rate of 2usec R23 22 kohm Channels 2 and 3, slew rate of 2usec DISK CONTROLLER The MDC11 Disk Controller is a peripheral controller intended for use in LSI-11 based computer systems. The option straps are set as follows: Label Jumper Function Implemented ----- ------ --------------------------------------- R0 I Positioning step time period R1 I set at 40 milliseconds Mx None 1.6 second time out delay RD I Refresh Disable R13 I Address 13 173 I Enable address 173000 A15 R Prom address bit 15 A14 R Prom address bit 14 A13 I Prom address bit 13 PD I Prom Disable ER0 I Enable Prom block 0 ER1 I Enable Prom block 1 ER2 I Enable Prom block 2 ER3 I Enable prom block 3 A-B I A-B C-D I C-D E R E 12M I 12 Volt supply A11 R Address 11 latched 5M I -5 Volt supply to ROMS R-Q R R-Q B12 R Base address of minidisk B11 R controller located at 177200. B10 R Register B9 R Command-Status (CSR) 177200 B8 I Track (TR) 177202 B7 R Sector 177204 B6 I Data 177206 B5 I B4 I B3 I M1 R Time out delay M2 R set at M4 R 1.6 seconds after no user access MD R Motor disable DISK DRIVE The disk utilized is the MPI 51/52 or the Shugart SA400. They are physically and electrically interchangeable. The option straps are as follows: Label Jumper Function Implemented ----- ------ --------------------------------------- T1 I Head solinoid with select T2 I Drive select 1 selected T3 R Drive select 2 not selected T4 R Drive select 3 not selected T5 I Drive always selected T6 R Drive 4 not selected T7 I Head solinoid with motor on BMUX MAINLINE LOGIC DOCUMENTATION The software is divided into three major portions: A. Mainline Logic B. Interrupt Service Logic C. Configuration Logic. The mainline logic is divided into two portions: Initialization and Controller Logic. The initialization logic presets the operational conditions for the proper functioning of the controller portion. The controller handles all garbage collection, I/O start/stop and control interface functions. The initialization section does the following: A. Saves the current contents and presets the interrupt vector address contents for the proper interrupt service routine entry, B. Reads the configuration information from disk to preset the port- dependent operations of the controller and interrupt service portions of the software, C. Prints an initialization message on the console and initiates the input process for the console, and D. Presets flags to show that the logic has been initialized. The controller section does the following: A. Starts all read/write I/O sequences for the trunk(s) and ports, B. Processes all read/write I/O completions for the trunk(s) and ports, C. De-queues all traffic and messages for the trunk(s) and ports, D. Acquires and releases all buffers from/to the trunk and port pools, E. Processes all console control interface commands, F. Maintains (when possible) a double-read condition for the trunk(s), G. Journals traffic and error statistics (by trunk/port) to a cumulative table, and H. Handles the timer expiration situation for the trunk(s), and the interrupt service logic resides with the mainline logic and asychronously services the transmission/receipt of characters by the trunk(s) and ports. the trunk read ISR (interrupt service routine) works hand-in-hand with the controller section and trunk write ISR to provide response to the Burroughs protocol. The port read/write ISR's process buffers to/from the trunk(s) and ports. Messages from the console port to the other ports is picked up by the command processor segment of the controller section and is massaged to look like a trunk read completion. The buffers pools are separate and homogeneous in size and structure. Hence the same acquisition/release routines can be used for both. The trunk read pool is used to supply read buffers for the trunk read ISR, which become port write buffers when the burroughs has sent a buffer to a port in a 'select' protocol sequence. The port read pool is used to supply read buffers for the port read ISR, which become trunk-bound write buffers. Console messages reside in the port read buffer, but are massaged to look like a trunk read destined for the specified port. These are dequeued by a special segment of the mainline's traffic-routing routines. A third segment of the software is the configuration logic, which shares and sets up defined port values in the data structure segment (SF2) to enable the controller and interrupt service logic to function as the user desires. The in-core structure of the multiplexor and configuration portions of the software (low-to-high memory adressing) is as follows: program stack program stack | | data structure (SF2) data structure (SF2) | | buffer pools (SF98, SF99) configuration logic (SF60) | initialization and controller (SF10) | command processing routines (SF12) | trunk read ISR (SF20) | port write ISR (SF30) | trunk read ISR (SF40) | trunk write ISR (SF50) | canned messages (SF90) These two software entities cannot co-exist in memory at the same time. Buffer request and release are controlled by two common routines having separate entry points for Trunk and Port buffer processing. These routines maintain pointers for each buffer pool which denote the start and end of the group of buffers currently active for that pool. Traffic scans will begin at the start pointer value and stop when the end pointer value is reached. When a buffer is requested from the buffer pool, the search is first made from the buffer immediately following the end pointer until the start pointer value is reached. If none exist, a search is made from the start pointer to the end pointer looking for "embedded" buffers that are available for use. When a buffer is released to either buffer pool, the start and/or end pointers are updated IF the buffer was being pointed to by either pointer. A buffer is active if its Read Queue (RQ) byte is NOT a -1 value. If the Write Queue (WQ) byte is NOT a -1 value, the buffer is queued for transfer to a Trunk or Port. Refer to the following diagram for a sample condition of the two buffer pools, Trunk and Port. In the example, Trunk buffers 4 and 5 are active for Trunk Read purposes. Due to the positional order of the two, buffer 4 is probably active and buffer 5 is waiting for use (refer to references to the "double-queued" buffers for Trunk reads). The other Trunk buffers have completed the Trunk Read process and are awaiting (or in the process of) transmission to the specified PCB terminals: buffer 1 is queued for PCB 2, followed by buffer 3, and buffer 2 is queued for PCB 3. In the Port buffer pool, buffers are actively being used for Port Reads: buffer 6 is active for PCB 5, buffer 11 for PCB 3, and buffer 12 for PCB 4. Buffers 7-10 have completed the Port Read process and are awaiting transmission to the Trunk. Note that PCB 2 has NO buffer queued in the Port Read buffer pool. It has probably JUST completed a Read process and the mainline has NOT YET requested a new buffer for the Read process for PCB 2. In the general flow of buffers, Port Read buffers "feed" the Trunk Write process, just as Trunk Read buffers "feed" the Port Write process. The "Traffic Queues" for each Write process are loosely held between the start and end pointers of the two buffer pools. Traffic dequeuing occurs when a Trunk or Port has completed its last Write process and is ready to commence another. The Trunk Write dequeuing is controlled by the Burroughs requests, however. It is probably obvious that the Trunk buffer pool stands the best chance of becoming "staurated" due to large "bursts" of output from the Burroughs processor. This is purely dependent upon the ability of the defined Port PCB's to output the buffers received from the Trunk fast enough to keep ahead of the Burroughs transmissions. The software DOES prohibit further buffer transmittal from the Burroughs when the Trunk buffer pool becomes saturated by "throttling" the transmission until at least one Trunk buffer is available for the Read process. .TITLE BMUX -GENERAL SCIENTIFIC CORP. .IDENT /000001/ ; GAITHERSBURG, MARYLAND ; ; COPYRIGHT (C) 1979 ; ; THIS SOFTWARE IS FURNISHED UNDER A LICENSE FOR USE ONLY ON A SINGLE ; COMPUTER SYSTEM AND MAY BE COPIED ONLY WITH THE INCLUSION OF THE ABOVE ; COPYRIGHT NOTICE AND THE EXPRESSED, WRITTEN PERMISSION OF GENERAL ; SCIENTIFIC CORPORATION. TITLE TO AND OWNERSHIP OF THIS SOFTWARE SHALL ; REMAIN WITH GENERAL SCIENTIFIC CORPORATION. COPIES OF THIS SOFTWARE ; MAY NOT BE PROVIDED TO OR OTHERWISE MADE AVAILABLE TO ANY OTHER PERSON ; EXCEPT FOR USE ON A GENERAL SCIENTIFIC CORPORATION SUPPLIED SYSTEM. ; ; THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE AND ; SHOULD NOT BE CONSTRUED AS A COMMITMENT BY GENERAL SCIENTIFIC CORPORATION. ; .LIST ; ; ; .PAGE .SBTTL NOTES ; ; THE FOLLOWING SET OF EQUATES EXPRESSES THE DESIGN PARAMETERS ; FOR THE BMUX SOFTWARE. NOT ALL OF THE EQUATES ARE USED IN THE ; INITIAL VERSION OF THE SYSTEM. SOME LOCAL EQUATES OCCUR IN SOME ; OF THE MODULES. AT A LATER TIME, THESE WILL BE MOVED TO THIS ; SOURCE FILE. ; ; ***** IMPORTANT NOTE: ***** ; ; THIS SOURCE FILE ** MUST ** BE ASSEMBLED WITH EVERY OTHER SOURCE ; FILE, SF2-SF99. ; ; .PAGE .SBTTL MACRO CALLS AND DEF'S ; .MCALL .SPND,.TWAIT,.REGDEF,..V2.. ; ..V2.. ; VERSION 2 MACRO CALLS .REGDEF ;MAKE LIFE EASIER ; .PAGE .SBTTL DLV11-J EQUATES ; THIS SECTION DEFINES THE DLV-11J DEVICE BIT SETTINGS AND REGI ; DEVICE HARDWARE REGISTER OFFSETS RELATIVE TO THE GIVEN ; DEVICE'S RCSR ADDRESS. REFER TO THE DEC LSI-11 PERIPHERALS ; MANUAL FOR INFORMATION REGARDING THE OPERATIONS OF THE DLV-11J ; VIA ITS HARDWARE REGISTERS. ; ; ; RCSR: READ CHANNEL CONTROL & STATUS REGISTER ; RCSR=0 ;DEVICE ADR REG OFFSET R.DONE=200 ;RCVR DONE BIT R.IE=100 ;INTERRUPT ENABLE BIT R.RE=1 ;RCVR ENABLE (CLEARS R.DONE) R.KILL=101 ;RCVR STOP BITS ; ; RBUF: READ CHANNEL BUFFER REGISTER ; RBUF=2 ;DEV ADR OFFSET ; ; STATUS BIT VALUES FOR RBUF ; R.ER=100000 ;ERROR BIT R.OV=40000 ;OVER-RUN ERROR R.FR=20000 ;FRAMING ERROR R.PA=10000 ;PARITY ERROR ; ; XCSR: TRANSMIT CHANNEL CONTROL & STATUS REGISTER ; XCSR=4 ;DEV ADR OFFSET X.RDY=200 ;XMTR READY BIT X.IE=100 ;INTERRUPT ENABLE BIT X.BR=1 ;XMTR BREAK (SET TO BREAK XMIT) ; ; XBUF: TRANSMIT CHANNEL BUFFER REGISTER ; XBUF=6 ;DEV ADR OFFSET ; DATA IS TRANSMITTED BY MOVING A CHARACTER INTO THE LOWER BYTE ; .PAGE .SBTTL SYSTEM EQUATES ; ; THE FOLLOWING VALUES SET THE LIMITS OF THE MULTIPLEXOR'S ; DESIGN AND DEFINE CERTAIN CRITICAL VALUES, SUCH AS THE PORT ; CONTROL BLOCK (PCB) NUMBER FOR THE CONSOLE. ; ; MAXPRT=24. ;MAX # OF PORTS DEF'D CONSOL=2 ;PORT # OF CONSOLE DEVICE CONVEC=60 ;CONSOLE VECTOR TRKA=0 ;PCB FOR TRUNK A TRKB=1 ;PCB FOR TRUNK B STA=MAXPRT ;STATUS POLL FOR TRUNK A STB=MAXPRT+1 ; SAME FOR B STALL=MAXPRT+2 ;BOX STATISTICS POLL PCB # TRAVEC=300 ;TRUNK A VECTOR TRBVEC=310 ;TRUNK B VECTOR CMDL=4 ;LEN OF ASCII CMD IN BYTES NCMD=6 ;NUMBER OF CONSOLE COMMANDS CTABL=6 ; LEN OF CMD TABLE ENTRY TIMOUT=100. ;10. SECOND MAX TIME-OUT NUMBUF=54. ;# BUFFERS IN EACH (OF TWO) POOLS BUFSIZ=170. ;SIZE OF DATA PORTION OF BUFFER BUFLEN=BUFSIZ+6 ;LEN OF EACH BUFFER .PAGE .SBTTL CHAR RECOGNITION EQUATES ; ; THE FOLLOWING EQUATES DEFINE ASCII CHARACTER VALUES OF IMPORTANCE ; ; TO THE PROCESSING OF THE TERMINAL PORTS, SUCH AS THE RETURN KEY. ; ; TERMINAL ASCII: ; ESC=33 ;ESCAPE CR=15 ;CARRIAGE RETURN LF=12 ;LINE-FEED FF=14 ;FORM-FEED NULL=0 ;NULL BS=10 ;BACK-SPACE DEL=177 ;LINE DELETE SYNC=26 ;SYNC (CMD FLAG CHAR) ; ; ; THE FOLLOWING VALUES ARE OF SPECIAL IMPORTANCE TO THE PROCESSING ; ; OF THE BURROUGHS PROTOCOL BY THE MAINLINE AND TRUNK ISR'S, SUCH ; ; AS THE POL OR SEL CHARACTERS (WHICH INDICATE 'POLL' AND 'SELECT' ; ; REQUESTS ISSUED BY THE BURROUGHS' LINE CONTROL PROGRAM). ; ; BURROUGHS ASCII: ; ENQ=5 ;ENQUIRE POL=160 ;PORT-TO-B SELECT SEL=161 ;B-TO-PORT SELECT CON=7 ;CONTENTION MODE (BELL) BELL=7 EOT=4 ;END-OF-XMIT ETX=3 ;END-OF-TEXT ACK=6 ;ACKNOWLEDGE NAK=25 ;NEGATIVE ACKNOWLEDGE SOH=1 ;START OF HEADER STX=2 ;START OF TEXT ; RVI=40 ;REVERSE INTERRUPT USED TO STOP OUTPUT FROM HOST (NOT USED) ; ; .PAGE .SBTTL PCB DEFINITION ; ; THE FOLLOWING EQUATES DEFINE THE STRUCTURE AND SOME OF THE DATA ; CONTENTS OF THE PORT CONTROL BLOCK (PCB). CURRENTLY, THE P.BAUD ; AND P.TYPE BYTES ARE NOT USED; DUE TO THE IMPLEMENTATION OF THE ; DLV-11J DEVICES. ; ; P.SOU=0 ;PCB INDEX TO POLTAB FOR THIS PORT (-1 IF NOT DEF'D) P.DST=1 ;PCB INDEX TO POLTAB FOR DESTINATION FROM HERE (OR -1) P.PST=2 ;PORT STATUS BYTE ; ; P.PST BIT MEANINGS: ; PS.RF=1 ;READ FINISHED BIT PS.WF=2 ;WRITE FINISHED BIT PS.RB=4 ;READ BUFFER NEEDED BIT PS.JS=10 ;JOURNAL STATS HOLD WD TO BUFFER BIT PS.CMD=20 ;PROCESS COMMAND FROM CONSOLE BIT PS.TQ=40 ;TRAFFIC QUEUED FOR TRUNK BIT ; P.DELF=3 ;DELAY FLAG (0=>INACTIVE) ; ; P.DELF BIT MEANINGS: ; PD.CR=1 ;CR DELAY FLAG PD.FF=2 ;FF DELAY FLAG ; P.BAUD=4 ;PORT BAUD RATE (INFO ONLY) P.TYPE=5 ;PORT TERM TYPE (INFO ONLY) P.LSIZ=6 ;LINE LENGTH (BYTES) P.ECHO=7 ;ECHO FLAG (0=>NO) P.CRD=10 ;CR DELAY VALUE (0=NONE) P.FFD=11 ;FF DELAY VALUE (0=NONE) P.STAT=12 ;STATS FLAG (0=NONE) ; ; P.STAT BIT MEANINGS: ; PST.E=1 ;ERROR STATISTICS COLLECTION BIT PST.T=2 ;TRAFFIC STATISTICS COLLECTION BIT ; ; P.WIND=13 ;STATS WINDOW (.1 SEC 'TICKS') P.ERR=14 ;ERROR STATS COUNTER P.TFC=15 ;TFC STATS COUNTER P.RST=16 ;READ STATUS BYTE P.WST=17 ;WRITE STATUS BYTE ; ; READ/WRITE STATUS BIT SETTINGS ; PS.DOR=300 ;RD: DATA OVER-RUN ERROR PS.FRA=240 ;RD: FRAMING ERROR PS.PAR=220 ;RD: PARITY ERROR PS.TMO=210 ;WR: TIME-OUT ERROR PS.OK=1 ;R/W: SUCCESSFUL COMPLETION ; ; P.RC=20 ;READ CHAR CNT P.WC=21 ;WRITE CHAR CNT P.RBFA=22 ;READ BUFFER ADR P.RBP=24 ;READ BUFFER PTR (CURRENT) P.WBFA=26 ;WRITE BUFFER ADR P.WBP=30 ;WRITE BUFFER PTR (CURRENT) P.SHLD=32 ;STATS HOLD WD (FOR JOURNALING TO CUMULATIVE TABLE) P.STIM=34 ;STATS WINDOW TIMER P.WTIM=35 ;WRITE I/O TIMER P.DC=36 ;DELAY CNTR (0= NO DELAY, ELSE # OF NULL'S) P.ECH=37 ;ECHO CHAR AWAITING OUTPUT ; PCBLEN=40 ;LEN OF PCB IN BYTES ; .PAGE .SBTTL BUFFER DEF'S ; ; THE BUFFERS OF BOTH POOLS ARE HOMOGENEOUS IN SIZE AND FLAGS USAGE ; IN THE F(IN THE FIRST 3 WDS OF EACH BUFFER). THE FIRST BYTE IS A -1 IF IT ; IS NOT QUEUED FOR USE AS A READ BUFFER. THE SECOND BYTE IS A -1 IF ; IT IS NOT QUEUED TO BE WRITTEN TO A SPECIFIED PORT (PCB NUMBER). ; THE THIRD BYTE CONTAINS THE READ/WRITE CHARACTER SIZE (MAX 255.). ; THE FOURTH BYTE CONTAINS A ZERO IF THE BUFFER IS NOT ACTIVELY BEING ; USED, ELSE IT CONTAINS A 1. THE FIFTH AND SIXTH BYTES ARE USED TO ; COMPUTE THE BCC CHARACTER VALUE FOR BUFFERS DESTINED FOR TRANSMISSION ; TO THE BURROUGHS VIA EITHER TRUNK. ; ; PORT AND TRUNK READS BEGIN AT THE APPROPRIATE POINTS WITHIN THE BUFFER, ; SINCE THE BURROUGHS HEADER VALUES ARE PLACED AT THE BEGINNING OF THE ; PORT READ BUFFER PRIOR TO ITS TRANSMISSION. BOTH THE ETX AND BCC ; (COMPUTED) CHARACTERS ARE AFFIXED TO THE END OF THE PORT READ BUFFERS. ; ; THE BUFFERS ARE MANAGED BY THE DATA LISTHEAD PTRS: ; ; PST: START OF PORT ACTIVE BUFFERS ; PEP: END OF PORT ACTIVE BUFFERS ; TSP: START OF TRUNK ACTIVE BUFFERS ; TEP: END OF TRUNK ACTIVE BUFFERS ; ; THE BUFFER POOL(S) ARE COMPLETELY USED WHEN THE START PTR ; VALUE IS THE SAME AS THE END PTR. ; ; ; RQ=0 ;READ Q BYTE: -1=AVAIL,ELSE PORT # WQ=1 ;WRITE Q BYTE: SAME AS RQ SZ=2 ;R/W CHAR SIZE (MAX 146.) AFL=3 ;ACTIVE FLAG (0=INACT, 1=ACT) TDATA=6 ;START OF TRUNK READ PDATA=10. ;START OF PORT READ DATA ; IF XM# USED, PDATA SHOULD BE 11. BCC=4 ;BCC COMPUTATION WD BAD0=7 ;START OF TWO-BYTE POLL ADR IN HEADER ; NOTE: AREA FROM TDATA TO PDATA CONTAINS BURROUGHS HDR ; ; .LIST BMUX Support Subroutine Documentation 1. BTIME: Trunk Timeout Handler This subroutine verifys that the Trunk timeout message byte is not as yet set. If so, the message byte is set to trigger the Console message indicating that this Trunk is not responding to communication attempts. 2. GBUFC: Buffer Request Handler This subroutine has two entry points: GTBUF: To request a Trunk read buffer, and GPBUF: To request a Port read buffer. The common routine processes the buffer pool pointers as set by the entry point logic to locate and allocate a buffer for the Trunk/Port which has requested the action. If a buffer is located, its address is placed on the top of the stack upon return from the subroutine. If no available buffers were found, a zero will be returned. This routine processes the pool starting at the first buffer after the current end pointer. If needed, the "search" pointer is reset to the top of the buffer pool being examined (this is the "wrap-around" case). If scanning from the end pointer to the start pointer fails to provide an available buffer, the scan will then switch to the "embedded" case and search from the start pointer to the end pointer. Once the entire buffer pool is checked, a zero is returned to the calling routine to indicate the pool is completely used. If a buffer islocated, the end pointer is the set to the buffer's address, unless this was the "embedded case", to set the limits for the mainline's traffic scan. This is an important point, since the start and end pointers are the limits for the mainline's dequeuing of traffic for the Trunk and Port write processes. 3. SAVE: Register Save Routine When the routine to be executed will destroy register contents that are needed after the routines execution, this routine is called to save the contents of the registers, R0 through R5, on the stack (SP). The RSTOR subroutine must be called at the logical point to restore the registers to their saved values just prior to exit from the calling routine. 4. STOR: Register Restoration Routine This routine restores the registers, R0 through R5, to the values saved on the stack (SP) by the SAVE routine. See usage note for the SAVE routine for more information regarding the application of this pair of subroutines. 5. READ: Trunk/Port Read Process Initiation Routine When the mainline processing requires the initiation of a new read condition for a Trunk or Port, this routine is called to preset the appropriate pointers and counters so the read interrupt service routines can process the characters received and place them in the Trunk/Port's read buffer. Just prior to exit from this routine, the Interrupt Enable bit for the Trunk/Port is set in the appropriate Read Command/Status Register (RCSR) to enable interrupt processing. 6. WRITE: Trunk/Port Write Process Initiation Routine This routine has a special entry point, FORCE, used to transmit the Trunk's Contention Break message (in accordance with the Burroughs protocol). The entire routine functions similarly to the READ routine in that it sets up the appropriate pointers to support output character interrupt processing by the Trunk/Port interrupt service routines. In addition to setting the Interrupt Enable bit in the Trunk/Port's Transmit Command/Status Register (XCSR), the FIRST character to be transmitted MUST be loaded into the Transmit Buffer Register (XBUF) to initiate the transmission process to accomplish the Write function. 7. FORCE: Burroughs Protocol Contention Break to Trunk Routine Refer to the WRITE routine for processing information. This routine is entered after the Contention Break message has been set up to initiate communications on the Trunk line NOW, rather than waiting for the next cyclic polling process to be initiated by the Burroughs end of the link. For more information on the conditions for initiation, refer to the FNDCOM routine description. 8. FNDCOM: Traffic Dequeuing (Trunk/Port) Routine This routine has two entry points: FNDMSG: Sets up Trunk Write traffic scans, and FNDPWB: Sets up Port Write traffic scans. The common logic scans the buffer pool specified by the entry point, looking for buffers in the pool whose Write Queue (WQ) byte contains the Trunk/Port's Port Control Block (PCB) number as found in the PCB's Source (P.SOU) byte. If a match occurs, the buffer address will be loaded into the Port's Write Buffer address word in the PCB so the Write process can be initiated. The Trunk is processed slightly differently. In order for the buffer to be dequeued, the Read Queue (RQ) byte in the buffer MUST match the Dequeue byte (TRKRSP) for this Trunk. Otherwise, scanning continues. If a Port buffer is dequeued for the Trunk, it is placed into a holding array (TWBPCB) ordered in PCB sequence. The logic then determines if a Break Contention is needed for this the Trunk line to transmit the buffer to the Burroughs processor. If not, control returns to the calling routine, and the buffer will be transmitted in its proper sequence. If a Contention Break is needed, the source PCB number from the buffer will be encoded in ASCII and placed in the Contention Break buffer and control given to the FORCE routine to "wake up" the Burroughs. 9. JORSTA: Statistics Journaling Routine This routine transfers the traffic (P.TFC) and error (P.ERR) byte values from the holding word (P.SHLD) in the PCB into the "wrap-around" word accumulators in the Statistics Cumulative array (CUMTAB), ordered in PCB sequence. This array can be displayed using the 'STAT' Console command. 10. REBUF: Buffer Release Routine This routine returns buffers to either pool upon completion of the Trunk/Port Write process. After return, it frees enables the dequeuing of traffic for the Trunk or Port by clearing the Write Buffer Address (P.WBFA) word, which allows the traffic dequeuing to resume. The header words of the buffer are reset and the the buffer pool pointers (start/end) are appropriately updated. 11. GPCBDA: Device Address Pointers Preset Routine When the mainline logic requires that the Read and Transmit Device Address Registers be accessed, this routine will preset the pointer words according to the PCB number contained in the PCB's source byte (P.SOU). 12. CONWRI: Console Message Output Routine This routine copies a "canned" message into a Trunk read buffer and queues it for the Console port's write process. If the Trunk read buffer pool is full, the C-bit will be set upon return, indicating that the routine failed to complete the requested action. 13. PCBSET: Configuration Preset Routine During initialization of the multiplexor, this routine is called to find and copy the Configuration-dependent data structure from floppy disk to core. It uses standard RT-11 directives (.LOOKUP, .READW and .CLOSE) to perform this action. The Configuration-dependent area consists of 543. words beginning at label "PCB" in the data structure. 14. BOMB: Multiplexor Abort Exit Point If software conditions develop which the multiplexor cannot handle, this routine is entered to indicate that the condition has occurred and to provide an opportunity to examine the software for information about the condition. This routine "undo's" the initialization process, prints the abort message to the Console, and enters DEC's standard SOFTWARE "ODT" module to provide the user and maintenance personel with software tools to aid the examination. 15. CONFDP: Special Message Dispatcher This routine processes special message conditions such as Trunk timeout for both possible Trunks. The Trunk timeout flag byte is examined to see if a message is needed. Else, the routine exits. If a message is needed, the routine copies the appropriate Trunk's message into the LAST defined buffer in the Port buffer pool. The timeout flag byte is then incremented until it reaches a timed limit and is reset. The message copied is queued for the Console to indicate that the named Trunk line is not supporting communications. At some later point, other special messages could be added here. 16. CONCMD: Console Command Decoding Routine When a Console command is detected by the Port read ISR, the mainline will route it to this routine for decoding and dispatch. The input buffer is checked against the existing command dispatch table (CCMD) and the appropriate command processing routine is called. If the command is invalid, the buffer will be echoed to the console with the console command in error replaced with an error indicator "!!!!" in place of the command. Once the processing call has completed, the buffer will either be released or reused. 17. HLTPRO: HALT Command Processing Routine This command is called by the CONCMD routine when a 'HALT' command is detected. It sets the HALT condition flag, HALTFL, which disables input from the Trunk and Ports terminals (except for the Console). 18. START: PROC Command Processing Routine This routine is called by the CONCMD routine when a 'PROC' command is detected. It clears the HALT mode flag (HALTFL), re-initializes the Read process for all Trunks and Ports defined, clears the Trunk traffic-queued table (TWBPCB), and arbitrarily sets the Trunk Contention mode flag(s) to indicate a Contention condition. 19. STDISP: STAT Command Display Header Routine When the CONCMD routine detects a 'STAT' command, this routine is called. It copies the display header into a Port read buffer and queues it for the Console. To preset the remainder of the status display, a flag is set (STDFLG) and the PCB counter for the display line processor (DISTAT) is set for PCB 0 (the lowest-numbered PCB in the system). Control is then returned to CONCMD. 20. MSG: Console Message Dispatcher When the CONCMD routine detects a 'MESS' command, this routine is called. The PCB number (02-23) is validated and the buffer is queued for that Port. If the PCB number is invalid, it is replaced in the buffer by the ASCII constant '??' to signal an error. In this case, the buffer will begin with 'MESS ??' and be echoed upon the Console. 21. PROXIT: EXIT Command Processing Routine Detection of an 'EXIT' command by the CONCMD routine causes this routine to be called. If HALT mode is in effect (HALTFL set), the routine will "un-do" the initialization process, print an EXIT message upon the console, and return Console and program control to RT-11. If the EXIT command is entered and the HALT mode flag is not set, it wil be IGNORED. 22. DISTAT: STAT Display Line Processing Routine When a 'STAT' command has been requested by the Console, this routine is entered once for every COMPLETE scan of ALL PCB's by the mainline logic. If the display flag is set (STDFLG), the 'buffer-ready' flag (STRDY) is checked. If set, the logic is awaiting an available Port read buffer. If the flag is not set, the NEXT PCB to be displayed is processed into an intermediate buffer according to the format defined by the header line and the buffer-ready flag is set. The CONCPY routine is then called to copy the staging buffer (CM16) into a Port read buffer. This process continues until ALL PCB's have been represented in a line of the status display. Once this point has been reached, the Link line (representing both possible Trunks) is formatted to show protocol errors and conditions. The process is terminated after this line is queued for the Console by resetting the display flag, STDFLG. 23. CONCPY: Console Status Display Buffer Copy Routine When a line of status display has been prepared by the DISTAT routine, this routine is called to acquire a Port read buffer, copy the formatted line into it from the staging area (CM16), and queue it for output upon the Console terminal. 24. Canned Messages: The system uses various "canned" messages, literal ASCII strings used for display purposes, etc. The strings are contained in the SF90 and SF12 source modules. BMUX Port Interrupt Service Routines Documentation 25. SF20 Module - Port Read Interrupt Service Processing Routine This routine has six entry points: PR0: entry point for the Console; PR1: entry point for PCB 3; PR2: entry point for PCB's 5, 9, 13, 17 and 21; PR3: entry point for PCB's 6, 10, 14, 18 and 22; PR4: entry point for PCB's 7, 11, 15, 19 and 23; and PR5: entry point for PCB's 4, 8, 12, 16 and 20. The multiple entry points each establish a pointer to variable-length table containing a LIST of pointers to the various Ports' PCB and Device Address entries. Upon entry, the ISR will scan ALL Ports defined in the list to see WHICH Port caused the Interrupt to occur. This structured technique permits the ISR to be data-driven and the actual logic exists only ONCE but processes ALL Read Interrupts for ANY Port. The Read ISR routine processes input character interrupts from the terminal Ports, 2 through 23. It handles the following: 1. Console command recognition for the Console, 2. Blocks input from ALL terminals EXCEPT the Console during HALT mode, 3. Backspace and line-deletion conditions, 4. Blocks terminal input and sends a BELL character if the terminal's Trunk line is in a timeout condition, 5. Auto-echo (if defined) of a terminal's input characters, 6. End-of-line conditions by formatting the appropriate header information in the buffer for transmission of the buffer to the Burroughs processor, and 7. Detects over-sized line situations. This routine computes a BCC value, the XOR-ed sum of ALL input characters that were input for transmission to the Burroughs processor. When the full buffer is ready for transmission to the Trunk line, a completion status will be set into the Read Status byte (P.RST) and a Read Completion flag (PS.RF) set in the Port Status byte (P.PST) of the PCB to trigger mainline completion handling. 26. SF30 Module - Port Write Interrupt Service Processing Routine This routine has six entry points: PW0: entry point for the Console; PW1: entry point for PCB 3; PW2: entry point for PCB's 5, 9, 13, 17 and 21; PW3: entry point for PCB's 6, 10, 14, 18 and 22; PW4: entry point for PCB's 7, 11, 15, 19 and 23; and PW5: entry point for PCB's 4, 8, 12, 16 and 20. This multiple-entry ISR routine processes the identification of the Port which caused the Interrupt Entry in the same manner as the SF20 Port Read ISR logic. Refer to the description in that module's discussion for more details. The ISR handles the Write buffer character processing to complete the Write function for terminal Ports 2 through 23. The following conditions are handled by this routine: 1. Output character buffer processing; 2. Carriage return (CR) and form feed (FF) delays (if defined) by sending the specified number of ASCII NULL characters after the transmission of a CR or FF; and 3. Write completion handling. When the output sequence is complete, a completion status is placed in the Write Status byte (P.WST) and the Write Completion flag is set in the Port Status byte (P.PST) of the PCB. 27. SF40 Module - Trunk Read Interrupt Service Processing Routine This routine has two entry points: TR0: entry point for Trunk 0, and TR1: entry point for Trunk 1. The ISR entry points for this routine specify the table address for the appropriate Trunk PCB and Device Address entries. In this manner, the logic appears only ONCE but will process Read Interrupts for either of the two Trunk lines (if both are defined). It is responsible for the following actions: 1. Protocol interpretation and response for the Trunk lines, 2. Traffic receipt from the Burroughs destined for the Ports, 3. Protocol verification, 4. Poll address verification, 5. Oversized line detection, and 6. Burroughs-bound traffic control by coordination with the Trunk Write ISR and the mainline logic. This routine is the sole validator of the protocol messages from the Burroughs. Invalid lengths, bad poll addresses, etc will result in error conditions being noted by this routine. If traffic is sent from or requested by the Burroughs processor, this routine verifies the poll address and request by the processor and attempts to fill the same. Refer to information on the protocol for the Burroughs link for specific details. The Burroughs protocol buffers accepted by this routine are: 1. Message buffers, 2. POL requests for Burroughs-bound traffic, 3. SEL requests for permission to send a buffer to a terminal, and 4. CON buffers indicating the Burroughs is declaring the line to be in Contention mode (that is, "wake me up if you have any traffic"). This routine also handles completion of Trunk Writes, since the buffers sent to the Byrroughs MUST be acknowledged by the processor before a Trunk Write action can be considered completed. Read Completions for the Trunk(s) occur only after a buffer has been received for one of the defined terminal Ports. ALL reads on the Trunk(s) are "double-queued", i.e. a second buffer MUST be waiting before the receipt of a buffer destined for a Port is acknowledged by the multiplexor. If the multiplexor is in HALT mode or a second read buffer does NOT exist (due to Trunk read buffer pool usage), SELect requests will NOT be acknowledged. As part of the Trunk timeout processing, the receipt of a POL or SEL request causes the Contention Break timer condition to be canceled. 28. SF50 Module - Trunk Write Interrupt Service Processing Routine This routine has two entry points: TW0: entry point for Trunk 0, and TW1: entry point for Trunk 1. The ISR entry points specify the appropriate PCB and Device Address entries for the Trunk to be processed. In this fashion, the logic to process either Trunk line's Write Interrupts occurs only ONCE. This routine merely outputs ALL characters in the Trunk write buffer and turns off the Interrupt Enable bit when the last character has been transmitted to the Burroughs processor. It also clears the Trunk Write Buffer Address word (P.WBFA) in the PCB to allow further Trunk traffic processing. BMUX Configuration Module Documentation 29. SF60 Module - Configuration Generator This routine uses standard RT-11 directives for terminal and disk I/O to prompt the user for a definition of the Trunk(s) and Port(s) he wishes to use. After the definition has been completed, it is stored on a mini-floppy disk for subsequent retrieval by the multiplexor PCBSET routine. The minimum configuration consists of a Trunk (PCB's 0 or 1) and the Console Port (PCB 2). ALL others are optional. The data structure module, SF2, is commonly used by both the Configuration Generator and the Multiplexor. The user is prompted, starting at PCB 0 and proceeding to PCB 23, for the needed information. Refer to the user documentation for order and limits upon the various prompts by the Configuration Generator. If a port is NOT defined, its Source (P.SOU) and Destination (P.DST) bytes contain a -1 value. The Statistics are preset for each Trunk or Port defined to collect BOTH Error and Traffic counts. All numeric inputs are assumed to be DECIMAL values. All inputs are validated for size, but the SITE and OWNER fields are validated for length ONLY, and stored AS ENTERED. Entry of two Control-V's causes the PCB to be skipped UNLESS it is PCB 2. If a Trunk is NOT defined, the Generator will exit after the definition of the first Port PCB. A Control-V and an ASCII 'E' causes the remaining PCB's to be skipped and not defined. BMUX Data Structure Documentation 30. SF2 Module - Data Structure The following data elements comprise the functional control set for both the Configuration Genertator and the Multiplexor. The following table provides the item-specific information: Label: Description: CR1-CR5 These are canned responses used to handle the Burroughs protocol CR6 This buffer is sent to the appropriate Trunk to break the Contention condition on that Trunk. The proper POLL ADDRESS is first inserted after the EOT character. CRTAB This is a table of the canned response addresses. TRKSRP Each byte (0/1) is used by the mainline to scan for traffic to be placed in the Burroughs-bound table for the PCB number held in that Trunk's TRKRSP byte. This is used only by the mainline. CONFLG Non-zero values in the respective bytes (0/1) indicate that the corresponding Trunk line is in Contention mode. This acts as a communications mechanism to relay the receipt of a Contention message by the Trunk Read ISR to the mainline. TRAPA The Trunk Read ISR uses the respective bytes (0/1) to signal to the mainline the PCB from which it wants traffic sent to the Burroughs via the Trunk Write process (in response to a POLL). TRDQ2 The mainline stores the address of the second buffer of the "double-queued" buffer pair in the respective words (0/1) for each Trunk to signal the Trunk Read ISR that it can accept buffers from the Burroughs. This "double-queued" buffer process prevents "windows" in the monitoring of the Trunk communications from the Burroughs processor. TSP-TEP These two pointers hold the starting and ending addresses for the active Trunk buffer pool buffers. The buffer request and release routines maintain the values of the pointers. PSP-PEP Used as TSP and TEP, but for the Port buffer pool. SPTR-PEN These scratch areas are used by the buffer request and release routines to examine the buffer pools. PRPTR-TWPTR These pointers are used to hold the entry point table addresses for the Trunk and Port Read/Write ISR's. HALTFL This byte, if non-zero, indicates that HALT mode is in effect. INIFLG This byte, if non-zero, indicates the multiplexor is NOT yet initialized. STDFLG If this byte is non-zero, the STAT command is processing lines of display information. SPFUN This table is used to define the list of special subroutines the mainline must process between each complete scan of ALL the defined PCB entries. CCMD The Console command decoder uses this table to identify a valid Console command and execute the proper routine for that command. ISRTAB This table is used during Initialization to establish the Interrupt Vector entry addresses for Interrupt processing. The Vector address, Read ISR address and Write ISR address comprise a unit entry in this table. DA1-DA8 These variable-length tables consist of PCB number/Device Read CSR address pairs for the Trunks/Ports utilizing the specified Interrupt Vector as entry to the Read or Write ISR's. Refer to the ISR module documentation for further information. ISRSAV This area is used by the Initialization process to save both the prior Interrupt Vector contents and the prior Device Address contents before the multiplexor "takes over" for its operations. In ABORT or EXIT conditions, this table is used to reset the Interrupt Vectors and Device Address Registers before giving control back to RT-11. CONSAV The Console Device Address Register contents are also saved in this area for abort reset. RCSRA-XBUFA This set of Device Address Register pointers is used SOLELY by the mainline to access a given device for Read/Write initiation. RCSRI-XBUFI This set of Device Address Register pointers are used soley by the currently active ISR routine to process the interrupt. WAIT1-NEWSEC RT-11 directive scratch areas. PAT Software maintenance scratch area for absolute patches. CUMTAB Statistics cumulative accumulator table (2 words/PCB). PCB Port Control Block table. This table defines the active PCB's that the multiplexor must process. Being the Master control structure for the multiplexor's operation, it is much too difficult to describe ALL of the interactions in this segment of the documentation to any detail. In general, it controls traffic flow, buffer flow, ISR processing, traffic/error statistics collection, Trunk timeout detection, and status coordination between the ISR's and the mainline. Please refer to the System Equates documentation for PCB definitions. POLTAB This table contains the user-defined POLL ADDRESS for each defined PCB, 2 ASCII bytes in PCB order. Unused areas will contain a -1 value, and ASCII control characters are not permitted by the Configuration generator. This table is used by the Trunk Read ISR to validate a POLL ADDRESS received in a POL or SEL buffer from the Burroughs processor. The Port Read ISR uses this table to define the POLL ADDRESS value in the header segment of the buffer to be sent to the Burroughs CPU. TTYPE This table contains the 6-byte OWNER value entered by the user via the Configuration Generator. Undefined values will contain a "******" value. BRTAB The SITE values entered by the user via the Configuration Generator are stored here, 5 bytes per PCB in PCB order. If a PCB is not defined, a "*****" value will appear. PCBDAT This table provides a cross-reference of PCB numbers and their corresponding Device Address Register addreses. TWBPCB This table holds buffer addresses, in PCB order, which are to be transmitted to the Burroughs for processing. If no buffer is queued from any given PCB, the corresponding word will be a zero value. RVITAB-JORST Scratch areas for future expansion.