/******************** MODULE INFO  ****************************/
/*
*  File name   :  top.sfl
*
*  AUTHOR      :  Yoshihiro Iida (3aepm001@keyaki.cc.u-tokai.ac.jp)
*  VERSION     :  1.0
*  DATE        :  Oct 16, 2003
*
*   Compiler    :  sfl2vl
*   Project     :  POP-11: PDP-11 compatible On Programmable chip
*   Functions   :  Top layer of POP-11 for UNIX simulation
*
*
Copyright (c) Yoshihiro Iida, Tokai University, Shimizu Lab., Japan.
(http://shimizu-lab.dt.u-tokai.ac.jp)
This software is the property of Tokai University, Shimizu Lab., Japan.

The POP-11 is free set of files; you can use it, redistribute it
and/or modify it under the following terms:

1. You are not allowed to remove or modify this copyright notice
   and License paragraphs, even if parts of the software is used.
2. The improvements and/or extentions you make SHALL be available
   for the community under THIS license, source code included.
   Improvements or extentions, including adaptions to new architectures/languages,
   SHALL be reported and transmitted to Tokai University, Shimizu Lab., Japan.
3. You must cause the modified files to carry prominent notices stating
   that you changed the files, what you did and the date of changes.
4. You may NOT distribute this set of files under another license without
   explisit permission from Tokai University, Shimizu Lab., Japan.
5. This set of files is free, and distributed in the hope that it will be
   useful, but WITHOUT ANY WARRANTY; without even the implied warranty
   of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
   You SHALL NOT use this software unless you accept to carry all
   risk and cost of defects or limitations.

*
*    ------------  CHANGE RECORD  ----------------
*    Yoshihiro Iida (3aepm001@keyaki.cc.u-tokai.ac.jp) Sep 21, 2004:
*        First free version of this software published.
*
*/

%i "core.sfl"
%i "../div4.sfl"

declare top_module {
  input     D0in<16>;
  input     D1in<16>;
  output    D0out<16>;
  output    D1out<16>;
  output    adr<16>;
  instrout  rd;
  instrout  wt;
  instrout  cs0, cs1;
  instrout  ble0, bhe0;
  instrout  ble1, bhe1;
  input     in<16>;
  output    out<16>;
  instrout  rd_hi, rd_lo;
  instrout  wt_hi, wt_lo;
  input     rts,txd;
  output    cts,rxd;
  instrout  dsk_rd, dsk_wt;
  input     dsk_in<16>;
  output    dsk_out<16>;
  output    dsk_adr<21>;
}

module top_module {
  input     D0in<16>;
  input     D1in<16>;
  output    D0out<16>;
  output    D1out<16>;
  output    adr<16>;
  instrout  rd;
  instrout  wt;
  instrout  cs0, cs1;
  instrout  ble0, bhe0;
  instrout  ble1, bhe1;
  input     in<16>;
  output    out<16>;
  instrout  rd_hi, rd_lo;
  instrout  wt_hi, wt_lo;
  input     rts,txd;
  output    cts,rxd;
  instrout  dsk_rd, dsk_wt;
  input     dsk_in<16>;
  output    dsk_out<16>;
  output    dsk_adr<21>;

  core      cpu;

  instr_arg rd(adr);
  instr_arg wt(adr);
  instr_arg rd_lo(adr);
  instr_arg rd_hi(adr);
  instr_arg wt_lo(adr,out);
  instr_arg wt_hi(adr,out);
  instr_arg dsk_rd(dsk_adr);
  instr_arg dsk_wt(dsk_adr, dsk_out);

  par {
    cpu.rts = rts;
    cpu.txd = txd;
    cts = cpu.cts;
    rxd = cpu.rxd;
  }

  instruct cpu.dsk_wt par { dsk_wt(cpu.dsk_adr, cpu.dsk_out); }
  instruct cpu.dsk_rd par { cpu.dsk_in = dsk_rd(cpu.dsk_adr).dsk_in; }

  instruct cpu.rd par {
    rd(cpu.adr<16:1>);
    if(^cpu.adr<17>) cs0();
    if( cpu.adr<17>) cs1();
    if(cpu.byte) par {
      if(^cpu.adr<0> &^cpu.adr<17>) par { ble0(); cpu.in = 0x00||D0in<07:00>; }
      if(^cpu.adr<0> & cpu.adr<17>) par { ble1(); cpu.in = 0x00||D1in<07:00>; }
      if( cpu.adr<0> &^cpu.adr<17>) par { bhe0(); cpu.in = 0x00||D0in<15:08>; }
      if( cpu.adr<0> & cpu.adr<17>) par { bhe1(); cpu.in = 0x00||D1in<15:08>; }
    }
    if(^cpu.byte) par {
      if(^cpu.adr<17>) par { cpu.in = D0in; ble0(); bhe0(); }
      if( cpu.adr<17>) par { cpu.in = D1in; ble1(); bhe1(); }
    }
  }

  instruct cpu.wt par {
    wt(cpu.adr<16:01>);
    if(^cpu.adr<17>) cs0();
    if( cpu.adr<17>) cs1();
    if(cpu.byte) par {
      if(^cpu.adr<0> &^cpu.adr<17>) par { ble0(); D0out = cpu.out; }
      if(^cpu.adr<0> & cpu.adr<17>) par { ble1(); D1out = cpu.out; }
      if( cpu.adr<0> &^cpu.adr<17>) par { bhe0(); D0out = cpu.out<7:0>||0x00; }
      if( cpu.adr<0> & cpu.adr<17>) par { bhe1(); D1out = cpu.out<7:0>||0x00; }
    }
    if(^cpu.byte) par {
      if(^cpu.adr<17>) par { D0out = cpu.out; ble0(); bhe0(); }
      if( cpu.adr<17>) par { D1out = cpu.out; ble1(); bhe1(); }
    }
  }

  instruct cpu.erd any {
    cpu.byte: any {
      ^cpu.adr<0>: cpu.in = rd_lo(cpu.adr<16:01>).in;
       cpu.adr<0>: cpu.in = 0x00 || rd_lo(cpu.adr<16:01>).in<15:08>;
    }
    ^cpu.byte: cpu.in = rd_lo(cpu.adr<16:01>).in;
  }

  instruct cpu.ewt any {
    cpu.byte: any {
      ^cpu.adr<0>: wt_lo(cpu.adr<16:01>,cpu.out);
       cpu.adr<0>: wt_hi(cpu.adr<16:01>,cpu.out<7:0>||0x00);
    }
    ^cpu.byte: par {
      wt_lo(cpu.adr<16:01>,cpu.out);
      wt_hi(cpu.adr<16:01>,cpu.out);
    }
  }

}/* end of top */

module top {
  bidirect  D0<16>;
  bidirect  D1<16>;
  output    A<16>;
  output    OE, WE;
  output    CS0, CS1;
  output    BE0, BE1, BE2, BE3;

  input     IN<16>;
  output    OUT<16>;
  output    WEL, WEH;

  input     rts,txd;
  output    cts,rxd;

  input     we_enable;

  instrout  dsk_rd, dsk_wt;
  input     dsk_in<16>;
  output    dsk_out<16>;
  output    dsk_adr<21>;

  top_module cpu;

  instr_arg dsk_rd(dsk_adr);
  instr_arg dsk_wt(dsk_adr, dsk_out);

  par {

    cts = cpu.cts;
    rxd = cpu.rxd;
    cpu.rts = rts;
    cpu.txd = txd;

    cpu.in = IN;
    OUT = cpu.out;
    WEL = cpu.wt_lo;
    WEH = cpu.wt_hi;

    OE = ^cpu.rd;
    WE = ^(cpu.wt & we_enable);
    CS0 = ^cpu.cs0;
    CS1 = ^cpu.cs1;
    BE0 = ^cpu.ble0;
    BE1 = ^cpu.bhe0;
    BE2 = ^cpu.ble1;
    BE3 = ^cpu.bhe1;
    A = cpu.adr;

    cpu.D0in = D0;
    cpu.D1in = D1;

    any {
      cpu.wt & cpu.cs0: D0 = cpu.D0out;
      cpu.wt & cpu.cs1: D1 = cpu.D1out;
    }

  }

  instruct cpu.dsk_wt par { dsk_wt(cpu.dsk_adr, cpu.dsk_out); }
  instruct cpu.dsk_rd par { cpu.dsk_in = dsk_rd(cpu.dsk_adr).dsk_in; }

}/* top */