/*
Copyright (c) Yoshihiro Iida, Tokai University, Shimizu Lab., Japan.
(http://shimizu-lab.dt.u-tokai.ac.jp)
This software is the property of Tokai University, Shimizu Lab., Japan.

The POP-11 is free set of files; you can use it, redistribute it
and/or modify it under the following terms:

1. You are not allowed to remove or modify this copyright notice
   and License paragraphs, even if parts of the software is used.
2. The improvements and/or extentions you make SHALL be available
   for the community under THIS license, source code included.
   Improvements or extentions, including adaptions to new architectures/languages,
   SHALL be reported and transmitted to Tokai University, Shimizu Lab., Japan.
3. You must cause the modified files to carry prominent notices stating
   that you changed the files, what you did and the date of changes.
4. You may NOT distribute this set of files under another license without
   explisit permission from Tokai University, Shimizu Lab., Japan.
5. This set of files is free, and distributed in the hope that it will be
   useful, but WITHOUT ANY WARRANTY; without even the implied warranty
   of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
   You SHALL NOT use this software unless you accept to carry all
   risk and cost of defects or limitations.

*/

%i "dec6.sfl"
%i "dec4.sfl"
%i "inc3.sfl"
%i "RS232C_R1.1.sfl"
%i "RS232C_S1.2.sfl"
%d COUNT 0b111111

declare RS232C_IF{
	input		txd;
	input		rts;
	input		in<8>;
	output		cts;
	output		rxd;
	output		out<8>;
	output		sv;
	output		rv;
	instrin		do;
	instrin		get;
	instrin		put;
	instrin		chmod1;

	instr_arg put(in);
	instr_arg chmod1(in);
}	
	
module RS232C_IF{
	input		txd;
	input		rts;
	input		in<8>;
	output		cts;
	output		rxd;
	output		out<8>;
	output		sv;
	output		rv;
	instrin		do;
	instrin		get;
	instrin		chmod1;
	instrin		put;

	reg		clk<6>;

	dec6		count;
	RS232C_R	reciever;
	RS232C_S	sender;
	
	stage_name cycle{ task run();}

	par{
		rv = reciever.stat;
		sv = sender.stat;
		cts = reciever.cts;
		rxd = sender.rxd;
		reciever.txd = txd;
		sender.rts = rts;
	}	

	instruct get out = reciever.get().data;

	instruct put sender.put(in);
	instruct chmod1 sender.chmod1(in);

	instruct do par{
		generate cycle.run();
	}	

	stage cycle{
		state_name	idle, divide;
		first_state	divide;
		state divide par{
			reciever.do();
			sender.do();

      clk := COUNT;
			goto idle;
		}

		state idle any{
			/|clk:clk := count.do(clk).out;
			^(/|clk):goto divide;
		}
	}
}