/******************** MODULE INFO  ****************************/
/*
*  File name   :  arbiter.sfl
*
*  AUTHOR      :  Yoshihiro Iida (3aepm001@keyaki.cc.u-tokai.ac.jp)
*  VERSION     :  1.0
*  DATE        :  Oct 16, 2003
*
*   Compiler    :  sfl2vl
*   Project     :  POP-11: PDP-11 compatible On Programmable chip
*   Functions   :  Interrupt arbiter of POP-11
*
*
Copyright (c) Yoshihiro Iida, Tokai University, Shimizu Lab., Japan.
(http://shimizu-lab.dt.u-tokai.ac.jp)
This software is the property of Tokai University, Shimizu Lab., Japan.

The POP-11 is free set of files; you can use it, redistribute it
and/or modify it under the following terms:

1. You are not allowed to remove or modify this copyright notice
   and License paragraphs, even if parts of the software is used.
2. The improvements and/or extentions you make SHALL be available
   for the community under THIS license, source code included.
   Improvements or extentions, including adaptions to new architectures/languages,
   SHALL be reported and transmitted to Tokai University, Shimizu Lab., Japan.
3. You must cause the modified files to carry prominent notices stating
   that you changed the files, what you did and the date of changes.
4. You may NOT distribute this set of files under another license without
   explisit permission from Tokai University, Shimizu Lab., Japan.
5. This set of files is free, and distributed in the hope that it will be
   useful, but WITHOUT ANY WARRANTY; without even the implied warranty
   of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
   You SHALL NOT use this software unless you accept to carry all
   risk and cost of defects or limitations.

*
*    ------------  CHANGE RECORD  ----------------
*    Yoshihiro Iida (3aepm001@keyaki.cc.u-tokai.ac.jp) Sep 21, 2004:
*        First free version of this software published.
*
*/

/* Timer */
%d DEV0_PRI 0o6
%d DEV0_VEC 0x40
/* RK Disk Controller */
%d DEV1_PRI 0o5
%d DEV1_VEC 0x90
/* Serial Receiver */
%d DEV2_PRI 0o4
%d DEV2_VEC 0x30
/* Serial Sender */
%d DEV3_PRI 0o4
%d DEV3_VEC 0x34

declare arbit_add {
  instrin   do;
  input     a<4>,b<4>;
  output    out;
  instr_arg do(a,b);
}

module arbit_add {
  instrin   do;
  input     a<4>,b<4>;
  output    out;
  sel       c0,c1,c2,c3;
  sel       g0,g1,g2,g3;
  sel       p0,p1,p2,p3;

  instruct do par{
    g0 = a<0>&b<0>;
    g1 = a<1>&b<1>;
    g2 = a<2>&b<2>;
    g3 = a<3>&b<3>;
    p0 = a<0>@b<0>;
    p1 = a<1>@b<1>;
    p2 = a<2>@b<2>;
    p3 = a<3>@b<3>;
    c0 = g0;
    c1 = g1|(p1&g0);
    c2 = g2|(p2&g1)|(p2&p1&g0);
    c3 = g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0);
    out = (p3@c2);
  }
}

declare arbiter {
  instrin   irq0;
  instrin   irq1;
  instrin   irq2;
  instrin   irq3;
  instrin   ack;
  instrout  int;
  input     cpu_pri<3>;
  output    vector<8>;
}

module arbiter {
  instrin   irq0;
  instrin   irq1;
  instrin   irq2;
  instrin   irq3;
  instrin   ack;
  instrout  int;
  input     cpu_pri<3>;
  output    vector<8>;

  arbit_add compare;
  reg_wr    int_req, int_sel<2>;
  reg_wr    int_req0;
  reg_wr    int_req1;
  reg_wr    int_req2;
  reg_wr    int_req3;

  par {
    any {
      irq0: int_req0 := 0b1;
      irq1: int_req1 := 0b1;
      irq2: int_req2 := 0b1;
      irq3: int_req3 := 0b1;
    }
    alt {
      ack: int_req := 0b0;
      int_req0: par { if(compare.do(0b1||^DEV0_PRI,0b0||cpu_pri).out) int_req := 0b1; int_sel := 0b00; }
      int_req1: par { if(compare.do(0b1||^DEV1_PRI,0b0||cpu_pri).out) int_req := 0b1; int_sel := 0b01; }
      int_req2: par { if(compare.do(0b1||^DEV2_PRI,0b0||cpu_pri).out) int_req := 0b1; int_sel := 0b10; }
      int_req3: par { if(compare.do(0b1||^DEV3_PRI,0b0||cpu_pri).out) int_req := 0b1; int_sel := 0b11; }
    }
    if(int_req) int();
    if(ack) any {
      int_sel==0b00: par { vector = DEV0_VEC; int_req0 := 0b0; }
      int_sel==0b01: par { vector = DEV1_VEC; int_req1 := 0b0; }
      int_sel==0b10: par { vector = DEV2_VEC; int_req2 := 0b0; }
      int_sel==0b11: par { vector = DEV3_VEC; int_req3 := 0b0; }
    }
  }

}/* end of arbiter */