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Note 24.0                 MicroVAX instr set difference               No replies
FURILO::JACKSON                                     578 lines  19-AUG-1985 11:32
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      +---------------+                                    +-----------------+
      | d i g i t a l |                                    |  uNOTE # 024    |
      +---------------+                                    +-----------------+

                                                                         
      +----------------------------------------------------+-----------------+
      | Title: MicroVAX Instruction Set Differences        | Date: 28-APR-85 |
      +----------------------------------------------------+-----------------+
      | Originator: Mike Collins                           | Page 1 of 10    |
      +----------------------------------------------------+-----------------+


      The MicroVAX architecture specifies that the full  VAX  instruction  set
      need  not  be  implemented in the hardware of a MicroVAX processor.  For
      those processors that fall into  this  category,  there  is  a  software
      emulator which guarantees that the instructions are still executable.

      This MicroNote lists all of the instructions of the VAX architecture and
      for each MicroVAX processor indicates which instructions are implemented
      in hardware/microcode, those  that  are  emulated  and  those  that  are
      present in a floating point unit.

      The  instructions  are  listed  in  alphabetical  order  by  instruction
      mnemonic.   The  following  designations  are  used to indicate where an
      instruction will be executed.

      CPU   - Instructions marked with 'CPU' are implemented in the hardware of
              the particular MicroVAX processor.

      EMA   - Instructions marked with 'EMA' are emulated with microcode assist.

      E     - Instructions marked with an 'E' are emulated entirely in software.

      Processor specific designations:
      MicroVAX II
      FPU   - Instructions marked with 'FPU' are implemented in the hardware 
              only if an external floating point unit is present, otherwise they
              are emulated.

      MicroVAX I
      Hx    - Instructions marked with 'H', 'HF', 'HD' or 'HG' are implemented 
              in hardware even though the MicroVAX architecture specifies that 
              these instructions are emulated.

              There are two versions of  the  MicroVAX  I,  one  with  F_  and
              D_floating  and the other with F_ and G_floating instructions in
              microcode.  There are no MicroVAX I processors  with  all  3  of
              these  floating  point  instruction  types in the hardware.  The
              F_floating instructions are identified by 'HF',  the  D_floating
              by 'HD' and the G_floating by 'HG'.

                                                                Page 2


              Reference  MicroNote  #21,  'Floating  Point  Considerations  on
              MicroVAX I'.

      The  following  table  lists  statistics  about  the   distribution   of
      instructions   based   on  where  they  are  executed.   There  are  304
      instructions in the VAX instruction set.

      Table 1 - MicroVAX Instruction Distribution

      +-------------------------+--------------+------------+-------------+
      |       Description       |   MicroVAX   | MicroVAX I | MicroVAX II |
      |                         | Architecture |            |             |
      +-------------------------+--------------+------------+-------------+
      |   Percentage executed   |     57.6     |    74.3    |    57.6     |
      |         in CPU          |              |            |             |
      +-------------------------+--------------+------------+-------------+
      |   Percentage executed   |      N/A     |     N/A    |    23.0     |
      |         in FPU          |              |            |             |
      +-------------------------+--------------+------------+-------------+
      |   Percentage emulated   |      8.9     |     7.3    |     8.9     |
      |  with microcode assist  |              |            |             |
      +-------------------------+--------------+------------+-------------+
      |   Percentage emulated   |     33.5     |    18.4    |    10.5     |
      |   entirely in software  |              |            |             |
      +-------------------------+--------------+------------+-------------+


      Table 2 - Instruction Set Differences

      Mnemonic         Description              MicroVAX    MicroVAXI MicroVAXII
                                              Architecture

      ACBB      Add compare and branch byte       CPU          CPU       CPU
      ACBD      Add compare and branch             E            HD       FPU
                D_floating
      ACBF      Add compare and branch             E            HF       FPU
                F_floating
      ACBG      Add compare and branch             E            HG       FPU
                G_floating
      ACBH      Add compare and branch             E            E         E
                H_floating

      ACBL      Add compare and branch            CPU          CPU       CPU
                longword
      ACBW      Add compare and branch word       CPU          CPU       CPU
      ADAWI     Add aligned word interlocked      CPU          CPU       CPU
      ADDB2     Add byte 2-operand                CPU          CPU       CPU
      ADDB3     Add byte 3-operand                CPU          CPU       CPU

      ADDD2     Add D_floating 2-operand           E            HD       FPU
      ADDD3     Add D_floating 3_operand           E            HD       FPU
      ADDF2     Add F_floating 2_operand           E            HF       FPU
      ADDF3     Add F_floating 3_operand           E            HF       FPU
      ADDG2     Add G_floating 2_operand           E            HG       FPU

                                                                Page 3


      Mnemonic         Description              MicroVAX    MicroVAXI MicroVAXII
                                              Architecture

      ADDG3     Add G_floating 3_operand           E            HG       FPU
      ADDH2     Add H_floating 2_operand           E            E         E
      ADDH3     Add H_floating 3-operand           E            E         E
      ADDL2     Add longword 2-operand            CPU          CPU       CPU
      ADDL3     Add longword 3-operand            CPU          CPU       CPU

      ADDP4     Add packed 4-operand               E           EMA       EMA
      ADDP6     Add packed 6-operand               E           EMA       EMA
      ADDW2     Add word 2-operand                CPU          CPU       CPU
      ADDW3     Add word 3-operand                CPU          CPU       CPU
      ADWC      Add with carry                    CPU          CPU       CPU

      AOBLEQ    Add one and branch on             CPU          CPU       CPU
                less or equal
      AOBLSS    Add one and branch on less        CPU          CPU       CPU
      ASHL      Arithmetic shift longword         CPU          CPU       CPU
      ASHP      Arithmetic shift and               E           EMA       EMA
                round packed
      ASHQ      Arithmetic shift quad             CPU          CPU       CPU

      BBC       Branch on bit clear               CPU          CPU       CPU
      BBCC      Branch on bit clear and clear     CPU          CPU       CPU
      BBCCI     Branch on bit clear and clear     CPU          CPU       CPU
                interlocked
      BBCS      Branch on bit clear and set       CPU          CPU       CPU
      BBS       Branch on bit set                 CPU          CPU       CPU

      BBSC      Branch on bit set and clear       CPU          CPU       CPU
      BBSS      Branch on bit set and set         CPU          CPU       CPU
      BBSSI     Branch on bit set and set         CPU          CPU       CPU
                interlocked
      BCC       Branch on carry clear             CPU          CPU       CPU
      BCS       Branch on carry set               CPU          CPU       CPU

      BEQL      Branch on equal                   CPU          CPU       CPU
      BEQLU (=BEQL) Branch on equal unsigned      CPU          CPU       CPU
      BGEQ      Branch on greater or equal        CPU          CPU       CPU
      BGEQU (=BCC)  Branch on greater or equal    CPU          CPU       CPU
                unsigned
      BGTR      Branch on greater                 CPU          CPU       CPU

      BGTRU     Branch on greater unsigned        CPU          CPU       CPU
      BICB2     Bit clear byte 2-operand          CPU          CPU       CPU
      BICB3     Bit clear byte 3-operand          CPU          CPU       CPU
      BICL2     Bit clear longword 2-operand      CPU          CPU       CPU
      BICL3     Bit clear longword 3-operand      CPU          CPU       CPU

      BICPSW    Bit clear processor status        CPU          CPU       CPU
                word
      BICW2     Bit clear word 2-operand          CPU          CPU       CPU
      BICW3     Bit clear word 3-operand          CPU          CPU       CPU
      BISB2     Bit set byte 2-operand            CPU          CPU       CPU
      BISB3     Bit set byte 3-operand            CPU          CPU       CPU

                                                                Page 4


      Mnemonic         Description              MicroVAX    MicroVAXI MicroVAXII
                                              Architecture

      BISL2     Bit set longword 2-operand        CPU          CPU       CPU
      BISL3     Bit set longword 3-operand        CPU          CPU       CPU
      BISPSW    Bit set processor status          CPU          CPU       CPU
                word
      BISW2     Bit set word 2-operand            CPU          CPU       CPU
      BISW3     Bit set word 3-operand            CPU          CPU       CPU

      BITB      Bit test byte                     CPU          CPU       CPU
      BITL      Bit test longword                 CPU          CPU       CPU
      BITW      Bit test word                     CPU          CPU       CPU
      BLBC      Branch on low bit clear           CPU          CPU       CPU
      BLBS      Branch on low bit set             CPU          CPU       CPU

      BLEQ      Branch on less or equal           CPU          CPU       CPU
      BLEQU     Branch on less or equal           CPU          CPU       CPU
                unsigned
      BLSS      Branch on less                    CPU          CPU       CPU
      BLSSU (=BCS) Branch on less unsigned        CPU          CPU       CPU
      BNEQ      Branch on not equal               CPU          CPU       CPU

      BNEQU (=BNEQ) Branch on not equal unsigned  CPU          CPU       CPU
      BPT       Break point fault                 CPU          CPU       CPU
      BRB       Branch with byte displacement     CPU          CPU       CPU
      BRW       Branch with word displacement     CPU          CPU       CPU
      BSBB      Branch to subroutine with         CPU          CPU       CPU
                byte displacement

      BSBW      Branch to subroutine with         CPU          CPU       CPU
                word displacement
      BVC       Branch on overflow clear          CPU          CPU       CPU
      BVS       Branch on overflow set            CPU          CPU       CPU
      CALLG     Call with general argument        CPU          CPU       CPU
                list
      CALLS     Call with argument list on        CPU          CPU       CPU
                stack

      CASEB     Case byte                         CPU          CPU       CPU
      CASEL     Case longword                     CPU          CPU       CPU
      CASEW     Case word                         CPU          CPU       CPU
      CHME      Change mode to executive          CPU          CPU       CPU
      CHMK      Change mode to kernel             CPU          CPU       CPU

      CHMS      Change mode to supervisor         CPU          CPU       CPU
      CHMU      Change mode to user               CPU          CPU       CPU
      CLRB      Clear byte                        CPU          CPU       CPU
      CLRD (=CLRQ) Clear D_floating               CPU          CPU       CPU
      CLRF (=CLRL) Clear F_floating               CPU          CPU       CPU

      CLRG (=CLRQ) Clear G_floating               CPU          CPU       CPU
      CLRH (=CLRO) Clear H_floating               CPU          CPU       CPU
      CLRL      Clear longword                    CPU          CPU       CPU
      CLRO      Clear ocatword                     E            E         E
      CLRQ      Clear quadword                    CPU          CPU       CPU

                                                                Page 5


      Mnemonic         Description              MicroVAX    MicroVAXI MicroVAXII
                                              Architecture

      CLRW      Clear word                        CPU          CPU       CPU
      CMPB      Compare byte                      CPU          CPU       CPU
      CMPC3     Compare character 3-operand        E            H        EMA
      CMPC5     Compare character 5-operand        E           EMA       EMA
      CMPD      Compare D_floating                 E            HD       FPU

      CMPF      Compare F_floating                 E            HF       FPU
      CMPG      Compare G_floating                 E            HG       FPU
      CMPH      Compare H_floating                 E            E         E
      CMPL      Compare longword                  CPU          CPU       CPU
      CMPP3     Compare packed 3-operand           E           EMA       EMA

      CMPP4     Compare packed 4-operand           E           EMA       EMA
      CMPV      Compare field                     CPU          CPU       CPU
      CMPW      Compare word                      CPU          CPU       CPU
      CMPZV     Compare zero-extended field       CPU          CPU       CPU
      CRC       Calculate cyclic redundancy        E           EMA       EMA
                check

      CVTBD     Convert byte to D_floating         E            HD       FPU
      CVTBF     Convert byte to F_floating         E            HF       FPU
      CVTBG     Convert byte to G_floating         E            HG       FPU
      CVTBH     Convert byte to H_floating         E            E         E
      CVTBL     Convert byte to longword          CPU          CPU       CPU

      CVTBW     Convert byte to word              CPU          CPU       CPU
      CVTDB     Convert D_floating to byte         E            HD       FPU
      CVTDF     Convert D_floating to              E            HD       FPU
                F_floating         
      CVTDH     Convert D_floating to              E            E         E
                H_floating
      CVTDL     Convert D_floating to              E            HD       FPU
                longword

      CVTDW     Convert D_floating to word         E            HD       FPU
      CVTFB     Convert F_floating to byte         E            HF       FPU
      CVTFD     Convert F_floating to              E            HF       FPU
                D_floating
      CVTFG     Convert F_floating to              E            HG       FPU
                G_floating
      CVTFH     Convert F_floating to              E            E         E
                H_floating

      CVTFL     Convert F_floating to              E            HF       FPU
                longword
      CVTFW     Convert F_floating to word         E            HF       FPU
      CVTGB     Convert G_floating to byte         E            HG       FPU
      CVTGF     Convert G_floating to              E            HG       FPU
                F_floating 
      CVTGH     Convert G_floating to              E            E         E
                H_floating

                                                                Page 6


      Mnemonic         Description              MicroVAX    MicroVAXI MicroVAXII
                                              Architecture

      CVTGL     Convert G_floating to              E            HG       FPU
                longword
      CVTGW     Convert G_floating to word         E            HG       FPU
      CVTHB     Convert H_floating to byte         E            E         E
      CVTHD     Convert H_floating to              E            E         E
                D_floating
      CVTHF     Convert H_floating to              E            E         E
                F_floating

      CVTHG     Convert H_floating to              E            E         E
                G_floating
      CVTHL     Convert H_floating to              E            E         E
                longword
      CVTHW     Convert H_floating to word         E            E         E
      CVTLB     Convert longword to byte          CPU          CPU       CPU
      CVTLD     Convert longword to D_floating     E            HD       FPU

      CVTLF     Convert longword to F_floating     E            HF       FPU
      CVTLG     Convert longword to G_floating     E            HG       FPU
      CVTLH     Convert longword to H_floating     E            E         E
      CVTLP     Convert longword to packed         E           EMA       EMA
      CVTLW     Convert longword to word          CPU          CPU       CPU

      CVTPL     Convert packed to longword         E           EMA       EMA
      CVTPS     Convert packed to leading          E           EMA       EMA
                separate
      CVTPT     Convert packed to trailing         E           EMA       EMA
      CVTRDL    Convert rounded D_floating         E            HD       FPU
                to longword
      CVTRFL    Convert rounded F_floating         E            HF       FPU
                to longword

      CVTRGL    Convert rounded G_floating         E            HG       FPU
                to longword
      CVTRHL    Convert rounded H_floating         E            E         E
                to longword
      CVTSP     Convert leading separate           E           EMA       EMA
                to packed
      CVTTP     Convert trailing to packed         E           EMA       EMA
      CVTWB     Convert word to byte              CPU          CPU       CPU

      CVTWD     Convert word to D_floating         E            HD       FPU
      CVTWF     Convert word to F_floating         E            HF       FPU
      CVTWG     Convert word to G_floating         E            HG       FPU
      CVTWH     Convert word to H_floating         E            E         E
      CVTWL     Convert word to longword          CPU          CPU       CPU

      DECB      Decrement byte                    CPU          CPU       CPU
      DECL      Decrement longword                CPU          CPU       CPU
      DECW      Decrement word                    CPU          CPU       CPU
      DIVB2     Divide byte 2-operand             CPU          CPU       CPU
      DIVB3     Divide byte 3-operand             CPU          CPU       CPU

                                                                Page 7


      Mnemonic         Description              MicroVAX    MicroVAXI MicroVAXII
                                              Architecture

      DIVD2     Divide D_floating 2-operand        E            HD       FPU
      DIVD3     Divide D_floating 3-operand        E            HD       FPU
      DIVF2     Divide F_floating 2-operand        E            HF       FPU
      DIVF3     Divide F_floating 3-operand        E            HF       FPU
      DIVG2     Divide G_floating 2-operand        E            HG       FPU

      DIVG3     Divide G_floating 3-operand        E            HG       FPU
      DIVH2     Divide H-floating 2-operand        E            E         E
      DIVH3     Divide H-floating 3-operand        E            E         E
      DIVL2     Divide longword 2-operand         CPU          CPU       CPU
      DIVL3     Divide longword 3-operand         CPU          CPU       CPU

      DIVP      Divide packed                      E           EMA       EMA
      DIVW2     Divide word 2-operand             CPU          CPU       CPU
      DIVW3     Divide word 3-operand             CPU          CPU       CPU
      EDITPC    Edit packed to character           E           EMA       EMA
                string
      EDIV      Extended divide                   CPU          CPU       CPU

      EMODD     Extended modulus D_floating        E            HD       FPU
      EMODF     Extended modulus F_floating        E            HF       FPU
      EMODG     Extended modulus G_floating        E            HG       FPU
      EMODH     Extended modulus H_floating        E            E         E
      EMUL      Extended multiply                 CPU          CPU       CPU

      EXTV      Extract field                     CPU          CPU       CPU
      EXTZV     Extract zero_extended field       CPU          CPU       CPU
      FFC       Find first clear bit              CPU          CPU       CPU
      FFS       Find first set bit                CPU          CPU       CPU
      HALT      Halt (kernel mode only)           CPU          CPU       CPU

      INCB      Increment byte                    CPU          CPU       CPU
      INCL      Increment longword                CPU          CPU       CPU
      INCW      Increment word                    CPU          CPU       CPU
      INDEX     Index calculation                 CPU          CPU       CPU
      INSQHI    Insert at head of queue,          CPU          CPU       CPU
                interlocked

      INSQTI    Insert at tail of queue,          CPU          CPU       CPU
                interlocked 
      INSQUE    Insert into queue                 CPU          CPU       CPU
      INSV      Insert field                      CPU          CPU       CPU
      JMP       Jump                              CPU          CPU       CPU
      JSB       Jump to subroutine                CPU          CPU       CPU

      LDPCTX    Load process context (only        CPU          CPU       CPU
                legal on interrupt stack) 
      LOCC      Locate character                   E            H        EMA
      MATCHC    Match characters                   E           EMA       EMA
      MCOMB     Move complemented byte            CPU          CPU       CPU
      MCOML     Move complemented longword        CPU          CPU       CPU

                                                                Page 8


      Mnemonic         Description              MicroVAX    MicroVAXI MicroVAXII
                                              Architecture

      MCOMW     Move complemented word            CPU          CPU       CPU
      MFPR      Move from processor register      CPU          CPU       CPU
                (kernel mode only)
      MNEGB     Move negated byte                 CPU          CPU       CPU
      MNEGD     Move negated D_floating            E            HD       FPU
      MNEGF     Move negated F_floating            E            HF       FPU

      MNEGG     Move negated G_floating            E            HG       FPU
      MNEGH     Move negated H_floating            E            E         E
      MNEGL     Move negated longword             CPU          CPU       CPU
      MNEGW     Move negated word                 CPU          CPU       CPU
      MOVAB     Move address of byte              CPU          CPU       CPU

      MOVAD (=MOVAQ) Move address of D_floating   CPU          CPU       CPU
      MOVAF (=MOVAL) Move address of F_floating   CPU          CPU       CPU
      MOVAG (=MOVAQ) Move address of G_floating   CPU          CPU       CPU
      MOVAH (=MOVAO) Move address of H_floating   CPU          CPU       CPU
      MOVAL     Move address of longword          CPU          CPU       CPU

      MOVAO     Move address of ocatword           E            E         E
      MOVAQ     Move address of quadword          CPU          CPU       CPU
      MOVAW     Move address of word              CPU          CPU       CPU
      MOVB      Move byte                         CPU          CPU       CPU
      MOVC3     Move character 3-operand          CPU          CPU       CPU

      MOVC5     Move character 5-operand          CPU          CPU       CPU
      MOVD      Move D_floating                    E            HD       FPU
      MOVF      Move F_floating                    E            HF       FPU
      MOVG      Move G_floating                    E            HG       FPU
      MOVH      Move H_floating                    E            E         E

      MOVL      Move longword                     CPU          CPU       CPU
      MOVO      Move octaword                      E            E         E
      MOVP      Move packed                        E           EMA       EMA
      MOVPSL    Move processor status             CPU          CPU       CPU
                longword
      MOVQ      Move quadword                     CPU          CPU       CPU

      MOVTC     Move translated characters         E           EMA       EMA
      MOVTUC    Move translated until              E           EMA       EMA
                character
      MOVW      Move word                         CPU          CPU       CPU
      MOVZBL    Move zero-extended byte to        CPU          CPU       CPU
                longword
      MOVZBW    Move zero-extended byte to        CPU          CPU       CPU
                word

                                                                Page 9


      Mnemonic         Description              MicroVAX    MicroVAXI MicroVAXII
                                              Architecture

      MOVZWL    Move zero-extended word to        CPU          CPU       CPU
                longword
      MTPR      Move to processor register        CPU          CPU       CPU
                (kernel mode only)
      MULB2     Multiply byte 2-operand           CPU          CPU       CPU
      MULB3     Multiply byte 3-operand           CPU          CPU       CPU
      MULD2     Multiply D_floating 2-operand      E            HD       FPU

      MULD3     Multiply D_floating 3-operand      E            HD       FPU
      MULF2     Multiply F_floating 2-operand      E            HF       FPU
      MULF3     Multiply F_floating 3-operand      E            HF       FPU
      MULG2     Multiply G_floating 2-operand      E            HG       FPU
      MULG3     Multiply G_floating 3-operand      E            HG       FPU

      MULH2     Multiply H_floating 2-operand      E            E         E
      MULH3     Multiply H_floating 3-operand      E            E         E
      MULL2     Multiply longword 2-operand       CPU          CPU       CPU
      MULL3     Multiply longword 3-operand       CPU          CPU       CPU
      MULP      Multiply packed                    E           EMA       EMA

      MULW2     Multiply word 2-operand           CPU          CPU       CPU
      MULW3     Multiply word 3-operand           CPU          CPU       CPU
      NOP       No operation                      CPU          CPU       CPU
      POLYD     Evaluate polynomial D_floating     E            HD       FPU
      POLYF     Evaluate polynomial F_floating     E            HF       FPU

      POLYG     Evaluate polynomial G_floating     E            HG       FPU
      POLYH     Evaluate polynomial H_floating     E            E         E
      POPR      Pop registers                     CPU          CPU       CPU
      PROBER    Probe read access                 CPU          CPU       CPU
      PROBEW    Probe write access                CPU          CPU       CPU

      PUSHAB    Push address of byte              CPU          CPU       CPU
      PUSHAD (=PUSHAQ) Push address of D_floating CPU          CPU       CPU
      PUSHAF (=PUSHAL) Push address of F_floating CPU          CPU       CPU
      PUSHAG (=PUSHAQ) Push address of G_floating CPU          CPU       CPU
      PUSHAH (=PUSHAO) Push address of H_floating CPU          CPU       CPU

      PUSHAL    Push address of longword          CPU          CPU       CPU
      PUSHAO    Push address of ocatword           E            E         E
      PUSHAQ    Push address of quadword          CPU          CPU       CPU
      PUSHAW    Push address of word              CPU          CPU       CPU
      PUSHL     Push longword                     CPU          CPU       CPU

      PUSHR     Push registers                    CPU          CPU       CPU
      REI       Return from exception or          CPU          CPU       CPU
                interrupt
      REMQHI    Remove from head of queue,        CPU          CPU       CPU
                interlocked
      REMQTI    Remove from tail of queue,        CPU          CPU       CPU
                interlocked
      REMQUE    Remove from queue                 CPU          CPU       CPU

                                                               Page 10


      Mnemonic         Description              MicroVAX    MicroVAXI MicroVAXII
                                              Architecture

      RET       Return from procedure             CPU          CPU       CPU
      ROTL      Rotate longword                   CPU          CPU       CPU
      RSB       Return from subroutine            CPU          CPU       CPU
      SBWC      Subtract with carry               CPU          CPU       CPU
      SCANC     Scan for character                 E            H        EMA

      SKPC      Skip character                     E            H        EMA
      SOBGEQ    Subtract one and branch           CPU          CPU       CPU
                on greater or equal  
      SOBGTR    Subtract one and branch           CPU          CPU       CPU
                on greater
      SPANC     Span characters                    E            H        EMA
      SUBB2     Subtract byte 2-operand           CPU          CPU       CPU

      SUBB3     Subtract byte 3-operand           CPU          CPU       CPU
      SUBD2     Subtract D_floating 2-operand      E            HD       FPU
      SUBD3     Subtract D_floating 3-operand      E            HD       FPU
      SUBF2     Subtract F_floating 2-operand      E            HF       FPU
      SUBF3     Subtract F_floating 3-operand      E            HF       FPU

      SUBG2     Subtract G_floating 2-operand      E            HG       FPU
      SUBG3     Subtract G_floating 3-operand      E            HG       FPU
      SUBH2     Subtract H_floating 2-operand      E            E         E
      SUBH3     Subtract H_floating 3-operand      E            E         E
      SUBL2     Subtract longword 2-operand       CPU          CPU       CPU

      SUBL3     Subtract longword 3-operand       CPU          CPU       CPU
      SUBP4     Subtract packed 4-operand          E           EMA       EMA
      SUBP6     Subtract packed 6-operand          E           EMA       EMA
      SUBW2     Subtract word 2-operand           CPU          CPU       CPU
      SUBW3     Subtract word 3-operand           CPU          CPU       CPU

      SVPCTX    Save process context (kernel      CPU          CPU       CPU
                mode only)
      TSTB      Test byte                         CPU          CPU       CPU
      TSTD      Test D_floating                    E            HD       FPU
      TSTF      Test F_floating                    E            HF       FPU
      TSTG      Test G_floating                    E            HG       FPU

      TSTH      Test H_floating                    E            E         E
      TSTL      Test longword                     CPU          CPU       CPU
      TSTW      Test word                         CPU          CPU       CPU
      XFC       Extended function call            CPU          CPU       CPU
      XORB2     Exclusive OR byte 2-operand       CPU          CPU       CPU

      XORB3     Exclusive OR byte 3-operand       CPU          CPU       CPU
      XORL2     Exclusive OR longword 2-operand   CPU          CPU       CPU
      XORL3     Exclusive OR longword 3-operand   CPU          CPU       CPU
      XORW2     Exclusive OR word 2-operand       CPU          CPU       CPU
      XORW3     Exclusive OR word 3-operand       CPU          CPU       CPU

