RTL Logic

[Scott Stevens]

On Fri, 7 Jan 2005 12:59:57 -0800 (PST)
Tom Jennings <tomj at wps.com> wrote:

> On Fri, 7 Jan 2005, Steve Thatcher wrote:
> 
> > dirt has been known to be found in most places in the world...
> >
> > doing a wired-or and wired-and depends on reading IC specifications
> > for specific chips. It is what design engineers do...
> 
> Sorry for being so obtuse! Phrase meant: "wire OR/etc was very
> common in RTL".
> 
> I tried wired-OR once in TTL, didn't like the results :-)
> 

Wired-OR will work fine for open-collector output TTL.  It will fail
miserably with totem-pole output parts.  A 'battle of the transistors'
will ensue and one output or another will win.