================================================================================
Note 6.0                  LSI-11/23 & 11/73 Differences               No replies
JAWS::KAISER                                        413 lines  25-MAR-1985 09:15
--------------------------------------------------------------------------------
      +---------------+					   +-----------------+
      | d i g i t a l |					   |  uNOTE # 006    |
      +---------------+					   +-----------------+


      +----------------------------------------------------+-----------------+
      | Title:		  Differences Between		   | Date: 23-APR-84 |
      |		      the LSI-11/73 and LSI-11/23	   |		     |
      +----------------------------------------------------+-----------------+
      | Originator: Mike Collins			   | Page 1 of 8     |
      +----------------------------------------------------+-----------------+



      This MicroNote identifies and discusses  the  differences	 between   the
      LSI-11/23	 (KDF11-AA) and the LSI-11/73 (KDJ11-AA).  The following table
      lists these differences.	Following the table are individual discussions
      on these differences.

      Some of these differences are discussed from the point  of  view	of  an
      11/23 to 11/73 upgrade.

      Table 1 LSI-11/73 versus LSI-11/23

      +--------------------------+-----------------------+---------------------+
      |	       FEATURE		 |	   11/73	 |	 11/23	       |
      +==========================+=======================+=====================+
      | Odd Address Traps	 |	    Yes		 |	   No	       |
      +--------------------------+-----------------------+---------------------+
      | Micro ODT		 |	   22 Bit	 |	  18 Bit       |
      +--------------------------+-----------------------+---------------------+
      | Illegal Halt		 |	  Traps to 4	 |     Traps to 10     |
      +--------------------------+-----------------------+---------------------+
      | Processor Modes		 |	      3		 |	    2	       |
      +--------------------------+-----------------------+---------------------+
      | I & D Space		 |	     Yes	 |	   No	       |
      +--------------------------+-----------------------+---------------------+
      | General Purpose Reg Sets |	      2		 |	    1	       |
      +--------------------------+-----------------------+---------------------+
      | Floating Point Inst. Set |	   Standard	 |	  Option       |
      +--------------------------+-----------------------+---------------------+
      | Line Time Clock Reg.	 |	     Yes	 |	    No	       |
      +--------------------------+-----------------------+---------------------+
      | On-board Cache Memory	 |	     Yes	 |	    No	       |
      +--------------------------+-----------------------+---------------------+
      | Pipelined Processing	 |	     Yes	 |	    No	       |
      +--------------------------+-----------------------+---------------------+
      | UBMap Signal on the Q-bus|	Not Available	 |	 Available     |
      +--------------------------+-----------------------+---------------------+
      | Additional Instructions	 |	CSM, TSTSET,	 |	    Not	       |
      |	       Available	 |	   WRTLCK	 |	 Available     |
      +--------------------------+-----------------------+---------------------+
								   cont'd

									Page 2


      Table 1 cont'd LSI-11/73 versus LSI-11/23

      +--------------------------+-----------------------+---------------------+
      |	       FEATURE		 |	   11/73	 |	 11/23	       |
      +==========================+=======================+=====================+
      |				 |			 |		       |
      |				 |  CPU Error Register	 +----+		       |
      |				 |  Memory System Error Reg   |		       |
      | Additional CPU Registers |  Cache Control Reg	      |	     Not       |
      |				 |  Hit/Miss Reg	      |	  Available    |
      |				 |  Program Interrupt Req Reg |		       |
      |				 |  Line Time Clock Reg	      |		       |
      |				 |  Maintenance Reg	 +----+		       |
      |				 |			 |		       |
      +--------------------------+-----------------------+---------------------+
      |				 |     A discussion of processor speed can     |
      |	   Processor Speed	 |   be found in the respective user guides    |
      |				 |			 |		       |
      |				 |    User Guide Part #	 |  User Guide Part #  |
      |				 |	 EK-KDJ1A-UG	 |     EK-KDF11-UG     |
      |				 |			 |		       |
      +--------------------------+-----------------------+---------------------+


			      ODD ADDRESS TRAPS

      The 11/73 processor will trap to 4 when it  encounters  an  odd  address
      reference.   i.e.	  whenever  an	address begins on an odd byte boundary
      (least significant bit = 1).  The 11/23 ignores odd  address  references
      and simply treats the LSB as a zero, effectively 'forcing' all addresses
      to begin on even byte  boundaries.   Odd	address	 traps	do  not	 occur
      frequently,  however  it is possible for code to run on an 11/23 and NOT
      run  on  an  11/73  because  of  them.   Fixes  for  these  errors   are
      straightforward.

		    MICRO ODT (Octal Debugging Technique)

      Both the 11/23 and the 11/73 implement  ODT  in  their  microcode.   The
      11/23 can use ODT to examine main memory locations from 0 to 256 Kbytes,
      but no further.  On the other hand, the 11/73 ODT can examine the full 4
      Mbyte  range  of	main memory.  When accessing addresses in the I/O page
      with an 11/73, a full 22 bit address must be specified.

	   Example: To look at the first instruction of the bootstrap code with
		    an 11/73 it is necessary to type:

		       @17773000/
		       or  @7777777777773000/

		       NOT @773000/	This is NOT enough because only
					18 bits have been specified.

									Page 3


				 ILLEGAL HALT

      The 11/23 and the	 11/73	respond	 differently  when  detecting  a  halt
      instruction  in  user or supervisor mode.	 The 11/23 traps to address 10
      whereas the 11/73 traps to address 4.  The 11/73 also sets  the  Illegal
      Halt Bit in the CPU ERROR Register to indicate an Illegal Halt occurred.

			       PROCESSOR MODES

      The 11/23 has two processor modes, KERNEL and USER.  The 11/73 has three
      KERNEL, SUPERVISOR and USER.

				I and D SPACE

      The concept of I and  D  space  is  used	in  mapping  information  into
      separate	physical memory segments, depending on whether the information
      is considered instructions (I) or data (D).  The use of I	 and  D	 space
      allows programs to exist in two virtual segments and effectively doubles
      the address available to the user from 64 Kbytes to 128 Kbytes.

      The 11/73 has the capability for I and D space whereas  the  11/23  does
      not.   To implement this feature, many more PAR/PDR pairs are necessary.
      The 11/73 has 48 PAR/PDR pairs, the 11/23 has only 16 PAR/PDR pairs.

			GENERAL PURPOSE REGISTER SETS

      The 11/23 and all previous LSI-11	 processors  have  1  set  of  general
      purpose  registers,  R0  thru  R7.   Some	 of these are used for special
      purposes.	 R7 is used as the program counter and R6 is used as the stack
      pointer.	Internal to the 11/23 are 2 registers used for stack pointers,
      one for each processor mode).  There are 5 additional registers R0  thru
      R5.

      The 11/73 has two sets of general purpose registers, listed in the table
      below.  Only eight are visible to the user at any given time.  There are
      two groups of six registers (R0 thru R5 and R0' thru  R5').   The	 group
      currently	 being used is selected by bit 11 in the Processor Status Word
      (PSW).  Only one stack pointer is visible to the user at	any  one  time
      and is determined by bits 14 and 15 in the PSW.

	 Register Number	      Designation
	      0			      R0      R0'
	      1			      R1      R1'
	      2			      R2      R2'
	      3			      R3      R3'
	      4			      R4      R4'
	      5			      R5      R5'
	     *6			      KSP     SSP    USP
	      7			      PC

		* KSP = Kernel Stack Pointer
		  SSP = Supervisor Stack Pointer
		  USP = User Stack Pointer

									Page 4


			FLOATING POINT INSTRUCTION SET

      Both the 11/23 and the 11/73 use the  FP11  Floating  Point  Instruction
      Set.   The  FP11	Instruction  Set is an option for the 11/23 (choice of
      either the KEF11 chip or the FPF11  floating  point  accelerator).   The
      FP11  instruction set is part of the J11 microprocessor microcode and is
      therefore a standard feature of the 11/73.

			   LINE TIME CLOCK REGISTER

      The original dual height 11/23 CPU does  not  have  an  LTC  (Line  Time
      Clock)  register	on  the	 board.	 In 11/23 based systems the BDV11 boot
      module contains the  LTC	reg.   In  order  to  enable  or  disable  LTC
      interrupts under software control, the 11/23 must write to this register
      over the Q-bus.


	      +---------+				   +---------+
	      |		|				   |	     |
	      |	 11/23	|				   |   LTC   |
	      |		|				   |   REG   |
	      |		|				   |	     |
	      |	   1	|				   |	     |
	      +--+   +--+				   +--+	  +--+
		 | 7 |					      |	  |
		 |   +----------------------------------------+	  +-------------
		 | 7 5 4 6		       Q-bus
		 +--------------------------------------------------------------

      The 11/73 has an LTC  register  on  the  CPU  board.   This  means  that
      whenever	the  11/73  wants  to  enable  or disable LTC interrupts under
      software control it writes to this on-board register.   The  address  of
      the  LTC	register (location 177546) is 'trapped' on the board and NEVER
      goes out onto the Q-bus.	When the 11/73 is used	in  a  system  with  a
      BDV11,  it  is recommended that software control over the LTC interrupts
      be disabled on the BDV11 (see uNOTE  114).

	      +---------+
	      |		|
	      |	 11/73	|
	      |		|
	      |		|
	      | 177546	|
	      +---------+
		 |   |
		 |   +----------------------------------------------------------
		 |			   Q-bus
		 +--------------------------------------------------------------

			    ON-BOARD CACHE MEMORY

      Cache memory systems are designed	 to  increase  CPU  performance.   The
      cache maintains copies of portions of main memory in very high-speed RAM
      and thus reduces access times significantly.

									Page 5


      The 11/73 is the first Q-bus  processor  to  implement  a	 cache	memory
      system.	The  cache  is	automatically  enabled	on  power-up  and  its
      operation is transparent to software.  However software  can  enable  or
      disable the cache by writing to the Cache Control Register (CCR).

      When the cache is enabled, any information fetched from main memory will
      be  'cached'  i.e.   placed  in the high-speed RAM.  Information fetched
      from an I/O device will NOT be 'cached' (i.e.  information fetched  from
      an address in the I/O page).


      CAUTION :	 Digital Equipment Corporation does not support a system which
      uses  shared  or	dual-ported  memory  on	 the Q-bus.  However there are
      applications  and	 non-DEC  add-on  hardware  which  do	support	  such
      configurations.  Consider the following:

      The system below uses an 11/73, has a certain amount of main  memory  as
      well  as	dual-ported  memory.   The  cache is enabled and the following
      sequence of events occur:

	  1.  The 11/73 reads a	 word  from  the  dual-ported  RAM  at
	  address  A  which  contains  the  value  X.	The  value  is
	  'cached'.
		  +---------+		  +---------+		  +---------+
		  |	    |		  |	    |		  |	    |
		  |  11/73  |		  |_________|		  | EXTERNAL|
		  |	    |	    +-----| A: X    | <-+	  | DEVICE  |
		  |	    |	    |	  |---------|	|	  |	    |
		  | A: X    |<------+	  |	    |	|	  |	    |
		  +---------+		  |	    |	|	  +---------+
					  |   RAM   |	|
					  |	    |	 Dual-Ported RAM
					  |	    |
					  +---------+

	  2. The external device writes a new value, Y, into location A.

		  +---------+		  +---------+		  +---------+
		  |	    |		  |	    |		  |	    |
		  |  11/73  |		  |_________|		  | EXTERNAL|
		  |	    |		  | A: Y    | <---------- | DEVICE  |
		  |	    |		  |---------|		  |	    |
		  | A: X    |		  |	    |		  |	    |
		  +---------+		  |	    |		  +---------+
					  |   RAM   |
					  |	    |
					  |	    |
					  +---------+
	  3.  The 11/73 references location A again, but finds that it
	  is  in  the  cache  and therefore uses the 'old' value of X.
	  But this is incorrect	 since	the  external  device  updated
	  location A with the new value Y.

      This anomaly can be corrected in a number of ways.

									Page 6


      A.  Put the dual ported RAM somewhere in the I/O page since any I/O page
      reference	 always	 bypasses  cache.  If the amount of dual-ported RAM is
      large this may not be practical.

      B.   The	memory	management  unit  contains  several  Page   Descriptor
      Registers	 (PDRs).   The	PDRs  contain  information  relative  to  page
      expansion, page length and access control.  Bit 15 of each  PDR  is  the
      Bypass Cache bit.	 If the PDR accessed during a relocation operation has
      this bit set the reference will go directly to  main  memory.   Hits  on
      reads  or	 writes	 will  result  in  invalidation	 of the accessed cache
      location.

      Enabling this bit in each PDR associated	with  the  dual-ported	memory
      will force these references to bypass cache.

      C.  Whenever the processor reads from the	 dual-ported  RAM,  add	 extra
      code which will simply turn off the cache prior to the read and turn the
      cache back on after the read is complete.	 Turning the cache on and  off
      can  be  done  by	 setting  the  appropriate  bits  in the Cache Control
      Register.

			     PIPELINED PROCESSING

      The 11/73 gets much of its performance by implementing  a	 prefetch  and
      predecode	  mechanism.   The  major  benefit  of	this  is  that	memory
      references are overlapped with  internal	operations  which  results  in
      faster   program	execution.   The  11/23	 does  not  implement  such  a
      mechanism.


      CAUTION  :   This	 implementation	 is  completely	 compatible  with  DEC
      hardware	and  software.	 However  there	 are  applications and non-DEC
      add-on hardware which may	 be  confused.	 Such  situations  are	easily
      corrected.


      The prefetch mechanism assumes sequential program flow;  one instruction
      immediately  follows  the	 next.	 Whenever  the	program	 flow  is  not
      sequential (i.e.	the PSW, CCR, PC or any memory management register  is
      written)	the  pipeline  is 'flushed'.  If a non-DEC device does its own
      'macro' memory management, the instruction flow may be confused.

      For example :

      A non-DEC device utilizes 2 ROM sets for boot code.  Both ROM  sets  map
      over  the	 same  addresses  but  only 1 set is enabled at any instant in
      time.  This is done via a ROM set enable CSR.  Assume the boot  code  in
      ROM  set	X is executing.	 Instruction X + 1 is a MOV instruction to the
      ROM enable CSR to transfer program control to ROM set Y.	The intent  of
      the  ROM	code  is for statement Y + 2 in ROM set 2 to be executed next.
      This will work OK with  an  11/23.   However  because  of	 the  prefetch
      mechanism	 of the 11/73, the 11/73 will execute instruction X + 2 of ROM
      set 1, NOT ROM set 2.

      This particular boot method effectively does its own memory mapping  and

									Page 7


      since  it	 is done at the 'macro' level and external to the J11 cpu, the
      pipeline is not 'flushed'.  A  simple  solution  is  to  include	a  NOP
      instruction  after  the instruction which updates the ROM enable CSR, or
      to use a branch instruction which effectively changes the PC and	causes
      the pipeline to be 'flushed'.


					      User Boot Device
	      +---------+	   +------------------------------------------+
	      |		|	   |	       ROM X		  ROM Y	      |
	      |	 11/73	|	   |	      +-------+		+-------+     |
	      |		|	   |  X	      |	      |	  Y	|	|     |
	      |		|	   |  X + 1   |	      |	  Y + 1 |	|     |
	      |		|	   |  X + 2   |	      |	  Y + 2 |	|     |
	      +---------+	   |  .	      |	      |	  .	|	|     |
				   |  .	      |	      |	  .	|	|     |
      Sequence of events :	   |  .	      |	      |	  .	|	|     |
      1. ROM X is enabled.	   |  X + n   |	      |	  Y + n |	|     |
				   |	      |	      |		|	|     |
      2. Instruction X + 1 enables |	      +-------+		+-------+     |
	 ROM Y.			   |  +----------------+		      |
				   |  | ROM Enable CSR |		      |
      3. Next instruction to be	   |  +----------------+		      |
	 executed is Y + 2.	   +------------------------------------------+

		      MAP SIGNAL ON THE Q-BUS (UBMAP L)

      The 11/23 outputs the signal UBMAP onto the Q-bus.  Some non-DEC	add-on
      equipment	 may use this signal for special purposes.  This signal is not
      defined by the Q-bus  specification  and	for  design  reasons  was  not
      included	on  the 11/73.	Therefore, the 11/73 may not work with non-DEC
      devices which expect to see this signal.

		      ADDITIONAL INSTRUCTIONS AVAILABLE

      These 3 instructions are part of the 11/73 instruction set but  are  NOT
      found in the 11/23:

		      CSM     Call to Supervisor Mode
		      TSTSET  Test Destination and Set Low Bit
		      WRTLCK  Read/Lock Destination Write/Unlock R0 into
			      Destination

									Page 8


		      ADDITIONAL CPU REGISTERS AVAILABLE

      The following CPU registers are part of the DCJ11 chip or implemented on
      the 11/73 module and are not found on the 11/23.

		      CPU Error Register
		      Memory System Error Register
		      Cache Control Register
		      Hit/Miss Register
		      Additional PAR/PDR's necessary to implement I & D Space
		      Program Interrupt Request Register
		      Line Time Clock Register (previously discussed)
		      Maintenance Register

			       PROCESSOR SPEED

      The 11/73 executes instructions significantly  faster  than  the	11/23.
      Software	which  bases  delays  on instruction loops may not work on the
      11/73 because the	 instructions,	and  therefore	the  delay  loop,  are
      completed	 much  faster  than  they  were	 when  executed	 on the 11/23.
      Software which uses this method of  implementing	delays	produces  code
      which  is	 not processor independent.  However instances do appear every
      so often and it is important to be aware of this possibility.

