================================================================================
Note 11.0                LSI-11/73 Advanced Memory Mgmt               No replies
JAWS::KAISER                                        557 lines  25-MAR-1985 09:19
--------------------------------------------------------------------------------
     +---------------+					  +-----------------+
     | d i g i t a l |					  |  uNOTE # 011    |
     +---------------+					  +-----------------+


     +----------------------------------------------------+-----------------+
     | Title: LSI-11/73 ADVANCED MEMORY MANAGEMENT	  | Date: 04-Sep-84 |
     +----------------------------------------------------+-----------------+
     | Originator: Art Bigler				  | Page 1 of 11    |
     +----------------------------------------------------+-----------------+



     This  micronote  examines	the  advanced  memory	management   features
     available	on  the	 DCJ11	based  LSI-11/73  series processors (KDJ11-A,
     KDJ11-B).	 These	features  include  the	 standard   virtual   address
     relocation	 within	 the  physical	address space and the kernel and user
     execution modes, all of which are currently available as options on  the
     mid-range LSI-11/23 (KDF11-A, KDF11-B) processors.	 In addition to these
     features, the DCJ11 based processors also provide instruction  and	 data
     space  (I/D  space) memory management and the supervisor execution mode.
     The following discussion is intended to further clarify these  features.
     For  information pertaining to address relocation the reader is referred
     to micronote 008, MEMORY MANAGEMENT AND THE LSI-11/73.


     1.0	INSTRUCTION/DATA SPACE MEMORY MANAGEMENT

     I/D space memory management is utilized in the DCJ11 based processors IN
     ADDITION  TO  the	relocation  of	virtual addresses within the physical
     address space.  This provides the	ability	 to  place  multiple  program
     images  in physical memory while at the same time providing an increased
     virtual address space of 128 kb or 64 kw  by  mapping  instructions  and
     data to separate areas of physical memory.	 The means by which I/D space
     memory management is attained involves both  hardware  and	 software  as
     described in the following paragraphs.


     1.1	I/D SPACE HARDWARE

     The hardware required to implement I/D space  addressing  is  integrated
     into  the	memory	management  unit  and  is standard on all DCJ11 based
     processors.  This includes the following:

	   1.	Eight  (8)  additional	active	page  registers	 (APR's)  per
	       execution  mode	(more  about  execution	 modes later).	These
	       APR's are used to map to the data space when I/D space  memory
	       management is enabled.

	   1.  Additional  control  and	 status	 bits  in  memory  management
	       registers  0  and 3 (MMR0, MMR3) which are used to control the
	       enabling and disabling of data space addressing.	  INSTRUCTION
	       SPACE ADDRESSING IS ALWAYS ENABLED.

     1.1.1	ACTIVE PAGE REGISTERS

									  Page 2


     The hardware provides a total of sixteen (16) APR's per execution	mode,
     eight   (8)  instruction  space  registers	 and  eight  (8)  data	space
     registers.	 THE APR's are further divided into page descriptor registers
     (PDR's)  and  page	 address  registers (PAR's) as described in micronote
     008.  The physical addresses for these registers are  contained  in  the
     I/O page and are as follows:



		+-------+---------------+---------------+-------+
		|  MODE |     PAR's	|     PDR's	|  PAGE |
		+-------+---------------+---------------+-------+
		|	|    17772340	|    17772300	|   0	|
		+	+---------------+---------------+-------+
		|	|    17772342	|    17772302	|   1	|
		+	+---------------+---------------+-------+
		|	|    17772344	|    17772304	|   2	|
		+	+---------------+---------------+-------+
		| KERNEL|    17772346	|    17772306	|   3	|
		+   I	+---------------+---------------+-------+
		| SPACE |    17772350	|    17772310	|   4	|
		+	+---------------+---------------+-------+
		|	|    17772352	|    17772312	|   5	|
		+	+---------------+---------------+-------+
		|	|    17772354	|    17772314	|   6	|
		+	+---------------+---------------+-------+
		|	|    17772356	|    17772316	|   7	|
		+-------+---------------+---------------+-------+
		|	|    17772360	|    17772320	|   0	|
		+	+---------------+---------------+-------+
		|	|    17772362	|    17772322	|   1	|
		+	+---------------+---------------+-------+
		|	|    17772364	|    17772324	|   2	|
		+	+---------------+---------------+-------+
		| KERNEL|    17772366	|    17772326	|   3	|
		+   D	+---------------+---------------+-------+
		| SPACE |    17772370	|    17772330	|   4	|
		+	+---------------+---------------+-------+
		|	|    17772372	|    17772332	|   5	|
		+	+---------------+---------------+-------+
		|	|    17772374	|    17772334	|   6	|
		+	+---------------+---------------+-------+
		|	|    17772376	|    17772336	|   7	|
		+-------+---------------+---------------+-------+


				     TABLE 1a
				KERNEL MODE APR'S

									  Page 3


		+-------+---------------+---------------+-------+
		|  MODE |     PAR's	|     PDR's	|  PAGE |
		+-------+---------------+---------------+-------+
		|	|    17772240	|    17772200	|   0	|
		+	+---------------+---------------+-------+
		|	|    17772242	|    17772202	|   1	|
		+	+---------------+---------------+-------+
		|	|    17772244	|    17772204	|   2	|
		+	+---------------+---------------+-------+
		| SPVSR |    17772246	|    17772206	|   3	|
		+   I	+---------------+---------------+-------+
		| SPACE |    17772250	|    17772210	|   4	|
		+	+---------------+---------------+-------+
		|	|    17772252	|    17772212	|   5	|
		+	+---------------+---------------+-------+
		|	|    17772254	|    17772214	|   6	|
		+	+---------------+---------------+-------+
		|	|    17772256	|    17772216	|   7	|
		+-------+---------------+---------------+-------+
		|	|    17772260	|    17772220	|   0	|
		+	+---------------+---------------+-------+
		|	|    17772262	|    17772222	|   1	|
		+	+---------------+---------------+-------+
		|	|    17772264	|    17772224	|   2	|
		+	+---------------+---------------+-------+
		| SPVSR |    17772266	|    17772226	|   3	|
		+   D	+---------------+---------------+-------+
		| SPACE |    17772270	|    17772230	|   4	|
		+	+---------------+---------------+-------+
		|	|    17772272	|    17772232	|   5	|
		+	+---------------+---------------+-------+
		|	|    17772274	|    17772234	|   6	|
		+	+---------------+---------------+-------+
		|	|    17772276	|    17772236	|   7	|
		+-------+---------------+---------------+-------+


				     TABLE 1b
			      SUPERVISOR MODE APR'S

									  Page 4


		+-------+---------------+---------------+-------+
		|  MODE |     PAR's	|     PDR's	|  PAGE |
		+-------+---------------+---------------+-------+
		|	|    17777640	|    17777600	|   0	|
		+	+---------------+---------------+-------+
		|	|    17777642	|    17777602	|   1	|
		+	+---------------+---------------+-------+
		|	|    17777644	|    17777604	|   2	|
		+	+---------------+---------------+-------+
		|  USER |    17777646	|    17777606	|   3	|
		+   I	+---------------+---------------+-------+
		| SPACE |    17777650	|    17777610	|   4	|
		+	+---------------+---------------+-------+
		|	|    17777652	|    17777612	|   5	|
		+	+---------------+---------------+-------+
		|	|    17777654	|    17777614	|   6	|
		+	+---------------+---------------+-------+
		|	|    17777656	|    17777616	|   7	|
		+-------+---------------+---------------+-------+
		|	|    17777660	|    17777620	|   0	|
		+	+---------------+---------------+-------+
		|	|    17777662	|    17777622	|   1	|
		+	+---------------+---------------+-------+
		|	|    17777664	|    17777624	|   2	|
		+	+---------------+---------------+-------+
		|  USER |    17777666	|    17777626	|   3	|
		+   D	+---------------+---------------+-------+
		| SPACE |    17777670	|    17777630	|   4	|
		+	+---------------+---------------+-------+
		|	|    17777672	|    17777632	|   5	|
		+	+---------------+---------------+-------+
		|	|    17777674	|    17777634	|   6	|
		+	+---------------+---------------+-------+
		|	|    17777676	|    17777636	|   7	|
		+-------+---------------+---------------+-------+


				     TABLE 1c
				 USER MODE APR'S


     1.1.2	MEMORY MANAGEMENT REGISTER 0

     Memory  management	 register  0  (MMR0)  contains	control	 and   status
     information  for  the  memory  management	unit (MMU).  This register is
     discussed completely in micronote 008, to	which  the  reader  is	again
     refferred	for  information  on  those  functions which are not directly
     applicable to I/D space and supervisor mode.

     MMR0 contains three (3) status bits which are used in the implementation
     of	 I/D  space  memory addressing.	 These bits, 04 through 06, yield MMU
     status  information  whenever  a  MMU  abort  occurs  and	are  used  in
     conjunction  with	MMR0  bits 01 through 03 and 13 through 15 to provide
     complete execution mode and I/D space status for the  page	 causing  the
     abort.  See figure 1.

									  Page 5


     Bit 04, the page address space status bit, indicates the  address	space
     associated	 with  the  aborted  page  and	is equal to a zero (0) for an
     instruction space page and a one (1) for a data space page whenever  I/D
     space  addressing	is  enabled.   If I/D space addressing is not enabled
     this bit always reflects a zero (0).

     Bits 05 and 06, the processor mode status bits, indicate  the  processor
     execution	mode  associated with the page causing the abort.  These bits
     are coded as follows:

		 BIT
		06 05		EXECUTION MODE
		-----		--------------

		 0  0		KERNEL

		 0  1		SUPERVISOR

		 1  0		ILLEGAL (causes an abort with bit 15 set)

		 1  1		USER

     For more information on MMU aborts see micronote 008.

									  Page 6


			    MMR0    ADDRESS: 17777572

	  1   1	  1   1	  1   1	  0   0	  0   0	  0   0	  0   0	  0   0
	  5   4	  3   2	  1   0	  9   8	  7   6	  5   4	  3   2	  1   0
	+===+---+---+---+===+===+===+---+---+---+===+===+===+---+---+---+
	|   |	|   | 0 | 0 | 0 | 0 | 0 | 0 |	    |	|	    |	|
	+===+---+---+---+===+===+===+---+---+---+===+===+===+---+---+---+
	 |_| |_| |_|			     |_____| |_| |_________| |_|
	  |   |	  |				|     |	      |	      |
	  |   |	  |____ABORT READ-ONLY	      PAGE    |	    PAGE      |
	  |   |		ACCESS VIOLATION      MODE    |	    NUMBER    |
	  |   |					      |		      |
	  |   |________ABORT PAGE LENGTH ERROR	    PAGE	  ENABLE
	  |					   ADDRESS    RELOCATION
	  |____________ABORT NON-RESIDENT	   SPACE (I/D)



	BIT #		DESCRIPTION
	-----		-----------

	<15>	-	ABORT READ-ONLY ACCESS VIOLATION (R ONLY)
	<14>	-	ABORT PAGE LENGTH ERROR (R ONLY)
	<13>	-	ABORT NON-RESIDENT (R ONLY)
	<12:07> -	NOT USED (R ONLY)
	<06:05> -	PAGE MODE (R ONLY)
	<04>	-	PAGE ADDRESS SPACE (I/D) (R ONLY)
	<03:01> -	PAGE NUMBER (R ONLY)
	<00>	-	ENABLE RELOCATION (R/W)


				     FIGURE 1
		       MEMORY MANAGEMENT REGISTER 0 (MMR0)


     1.1.3	MEMORY MANAGEMENT REGISTER 3

     Memory  management	 register  3  (MMR3)  contains	control	 and   status
     information  for  data space addressing, 22 bit mapping, and the call to
     supervisor mode  (CSM)  instruction.   This  register,  once  again,  is
     discussed in detail in micronote 008.

     MMR3  contains  three  (3)	 control  bits	which	are   used   in	  the
     implementation  of	 I/D  space  addressing.   These bits, 00 through 02,
     individually enable data space addressing	for  each  of  the  execution
     modes.   Bit  00 enables data space addressing for the USER mode, bit 01
     enables it for SUPERVISOR mode, and bit 02 enables it for	KERNEL	mode.
     The  desired bits are set to a one (1) whenever data space addressing is
     desired.  MMR3 is cleared during  power-up,  console  restart,  and  the
     execution of the RESET instruction.  See figure 2.

									  Page 7


			MMR3 REGISTER	 ADDRESS: 17772516

	  1   1	  1   1	  1   1	  0   0	  0   0	  0   0	  0   0	  0   0
	  5   4	  3   2	  1   0	  9   8	  7   6	  5   4	  3   2	  1   0
	+===+---+---+---+===+===+===+---+---+---+===+===+===+---+---+---+
	| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |   |	|   |	MODE	|
	+===+---+---+---+===+===+===+---+---+---+===+===+===+---+---+---+
						 |_| |_| |_| |_| |_| |_|
						  |   |	  |   |	  |   |
			UNINTERPRETED_____________|   |	  |   |	  |   |
						      |	  |   |	  |   |
			ENABLE 22 BIT MAPPING_________|	  |   |	  |   |
							  |   |	  |   |
			ENABLE CSM INSTRUCTION____________|   |	  |   |
							      |	  |   |
			KERNEL________________________________|	  |   |
								  |   |
			SUPERVISOR________________________________|   |
								      |
			USER__________________________________________|


	BIT #		DESCRIPTION
	-----		-----------

	<15:06> -	NOT USED (R ONLY)
	<05>	-	UNINTERPRETED (R/W)
	<04>	-	ENABLE 22 BIT MAPPING (R/W)
	<03>	-	ENABLE CSM INSTRUCTION (R/W)
	<02>	-	KERNEL DATA SPACE (R/W)
	<01>	-	SUPERVISOR DATA SPACE (R/W)
	<00>	-	USER DATA SPACE (R/W)


				     FIGURE 2
			   MEMORY MANAGEMENT REGISTER 3



     1.1.4	I/D SPACE ADDRESS MAPPING

     When I/D space addressing has been enabled the MMU hardware performs the
     address  mapping  (IN  ADDITION TO ADDRESS RELOCATION WHICH IS PERFORMED
     USING THE APPROPRIATE SET OF APR'S) as follows:

	   1.  The current instruction is ALWAYS fetched from the instruction
	       space.

	   2.  The operands are mapped according to table 2.

									  Page 8


		+---------------+---------------+---------------+-------+
		| OPERAND	| REGISTER	| TYPE		| I OR D|
		| ADDRESSING	| USED		| OF		| SPACE |
		| MODE		|		| ADDRESSING	| USED	|
		+---------------+---------------+---------------+-------+
		| 000		| ANY		| REGISTER	| I	|
		+---------------+---------------+---------------+-------+
		| 001		| ANY		| REGISTER	| D	|
		|		|		| DEFERRED	|	|
		+---------------+---------------+---------------+-------+
		| 010		| 0 THROUGH 6	| AUTOINCREMENT | D	|
		|		|		|		|	|
		|		| 7		| IMMEDIATE	| I	|
		+---------------+---------------+---------------+-------+
		| 011		| 0 THROUGH 6	| AUTOINCREMENT | D (A) |
		|		|		| DEFERRED	| D (D) |
		|		|		|		|	|
		|		| 7		| ABSOLUTE	| I (A) |
		|		|		|		| D (D) |
		+---------------+---------------+---------------+-------+
		| 100		| 0 THROUGH 6	| AUTODECREMENT | D	|
		|		|		|		|	|
		|		| 7		| DO NOT USE !! |	|
		+---------------+---------------+---------------+-------+
		| 101		| 0 THROUGH 6	| AUTODECREMENT | D (A) |
		|		|		| DEFERRED	| D (D) |
		|		|		|		|	|
		|		| 7		| DO NOT USE !! |	|
		+---------------+---------------+---------------+-------+
		| 110		| ANY		| INDEX		| I (A) |
		|		|		|		| D (D) |
		+---------------+---------------+---------------+-------+
		| 111		| ANY		| INDEX		| I (A) |
		|		|		| DEFERRED	| D (A) |
		|		|		|		| D (D) |
		+---------------+---------------+---------------+-------+

			(A) = INDIRECT OR INDEX ADDRESS
			(D) = DATA


				     TABLE 2
		    OPERAND ADDRESSING WITH DATA SPACE ENABLED



     All address mapping is performed using the I space APR's when data space
     addressing is not enabled.

     The most difficult example showing data space addressing  is  the	index
     deferred type of addressing.

	       CLR	@1000(R3)

	   1.  The instruction is  fetched  from  the  instruction  space  at

									  Page 9


	       location PC.

	   2.  The base address 1000 is fetched from the instruction space at
	       location	 PC+2.	 The index in R3 is added to the base address
	       forming the address of the indirect address.

	   3.  The indirect address is fetched from the data space using  the
	       address calculated in step 2.

	   4.  The data is fetched from the  data  space  using	 the  address
	       calculated in step 3.


     1.2	I/D SPACE SOFTWARE

     At the present time I/D space addressing is supported by two (2) Digital
     supplied operating systems, RSX-11M-PLUS and ULTRIX-11.

     RSX-11M-PLUS  provides  linking  of  tasks	 which	utilize	  I/D	space
     addressing	 via  the  task	 builder (TKB) utility.	 Those programs which
     include the data PSECTs in their object files may be  task	 built	using
     the  /ID  switch.	 It should be noted that the task may not make use of
     the entire 32kw data space because RSX-11M-PLUS requires that the	stack
     and  the  task  header  be placed in data space.  Other restrictions may
     apply, consult the task builder manual for further information.

     When using I/D space with	other  operating  systems  or  in  standalone
     programs,	the  user  must	 do all the mapping within the program.	 This
     implies that the mapping of the operating system must be attended to  by
     the user program if operating system features are to be utilized.

     To make use of data space addressing the program must:

	   1.  Separate the instruction space  from  the  data	space.	 (ie.
	       create different regions in memory for instructions and data)

	   2.  Load the instruction space  and	data  space  APR's  with  the
	       appropriate relocation information.

	   3.  Enable I/D space mapping by setting the	MMR3  bit  associated
	       with the execution mode under which the program will run.

     The following restrictions apply to I/D space programs:

	   1.  The instruction space can only contain instructions, immediate
	       operands,  absolute  addresses,	and  index  words.   This  is
	       reflected in table 2.

	   2.  The stack page must be mapped into both instruction  and	 data
	       space  if  the MARK instruction is used because it is executed
	       off the stack.

	   3.	Instruction  space-only	 pages	cannot	 contain   subroutine
	       parameters  which are data.  This precludes the mapping of any
	       pages containing standard PDP-11	 calling  sequences  entirely

									 Page 10


	       into an instruction space page.

	   4.  The trap catcher technique of putting .+2 in the	 trap  vector
	       followed	 by  a	halt must be mapped into both instruction and
	       data space.

     For further information on I/D space addressing under  RSX-11M-PLUS  and
     ULTRIX-11 consult the appropriate documentation set.



     2.0	SUPERVISOR MODE

     The DCJ11 based processors provide three (3) execution  modes:   KERNEL,
     SUPERVISOR,  and  USER.   They  provide  for various forms of memory and
     processor protection and permit additional features to be implemented in
     multiprogramming  environments.   Each  mode  has its own set of mapping
     registers.

     KERNEL mode is the most privileged of the modes, allowing the  execution
     of	 any instruction and the modification of any area in memory including
     the I/O page.

     USER mode prohibits the execution of  privileged  instructions  such  as
     HALT  and	RESET and the modification of areas in memory that the KERNEL
     program does not provide access to.

     SUPERVISOR mode has the same privileges as USER mode with its own set of
     mapping   registers,   thus   providing  another  level  of  protection.
     SUPERVISOR mode is intended for use in  the  mapping  and	execution  of
     programs  to  be  shared  by users while still providing protection from
     them.  Examples of this are command line processors which	are  required
     for  use  by all users on a system, while necessitating write protection
     from them.

     The execution mode is controlled by the state of bits 14 and 15  in  the
     processor status word (PSW).  These bits are changed by the execution of
     traps and interrupts, pushing and popping of old PSW's to and  from  the
     stack, and, when in KERNEL mode, the direct manipulation by the program.
     Bits 12 and 13 reflect the execution mode which  existed  prior  to  the
     event which placed the processor in the current mode.  See figure 3.

     The current and previous mode PSW bits are coded as follows:

		 BIT
		15 14
		13 12		EXECUTION MODE
		-----		--------------

		 0  0		KERNEL
		 0  1		SUPERVISOR
		 1  0		ILLEGAL
		 1  1		USER

									 Page 11


		 PROCESSOR STATUS WORD (PSW)	ADDRESS: 17777776

	  1   1	  1   1	  1   1	  0   0	  0   0	  0   0	  0   0	  0   0
	  5   4	  3   2	  1   0	  9   8	  7   6	  5   4	  3   2	  1   0
	+===+---+---+---+===+===+===+---+---+---+===+===+===+---+---+---+
	|	|	|   | 0 | 0 |	|	    | T | N | Z | V | C |
	+===+---+---+---+===+===+===+---+---+---+===+===+===+---+---+---+
	 |_____| |_____| |_|	     |_| |_________| |_| |_____________|
	    |	    |	  |	      |	      |	      |		|
	 CURRENT PREVIOUS |	      |	   PRIORITY   |	    CONDITION
	   MODE	   MODE	  |	      |	    LEVEL     |	      CODES
			  |	      |		      |
			  |	      |		      |
			 GPR	  SUSPENDED	    TRACE
			GROUP	 INFORMATION	     BIT


	BIT #		DESCRIPTION
	-----		-----------

	<15:14> -	CURRENT MODE (R/W)
	<13:12> -	PREVIOUS MODE (R/W)
	<11>	-	GENERAL PURPOSE REGISTER SET (R/W)
	<10:09> -	NOT USED (R ONLY)
	<08>	-	SUSPENDED INFORMATION (R/W)
	<07:05> -	PROCESSOR PRIORITY LEVEL (R/W)
	<04>	-	TRACE BIT (R/W)
	<03>	-	NEGATIVE CONDITION CODE (R/W)
	<02>	-	ZERO CONDITION CODE (R/W)
	<01>	-	OVERFLOW CONDITION CODE (R/W)
	<00>	-	CARRY CONDITION CODE (R/W)


				     FIGURE 3
			      PROCESSOR STATUS WORD

