.uj
..@a
                          INTRODUCTION



The Disk Jockey/Direct Memory Access (DJDMA) Floppy Disk Control
ler is a single board S-100 subsystem.  It communicates with both 
8 inch and 5 1/4 inch floppy disk drives.  Up to eight drives may 
be  connected to the controller - with  the limitation   that  no 
more than four of each type can be accommodated.

Special  programmable bipolar LSI logic makes it possible to read 
and write media with almost any format,  be it hard or soft  sec
tored.   Presently,  the  controller  supports soft-sectored  IBM 
compatible 8 inch media and hard-sectored North Star compatible 5 
1/4 inch media.  In the spring of 1982, IBM and Radio Shack 5 1/4 
inch  soft-sectored  media  will  also  be  supported.   Existing 
controllers in the field can be upgraded by replacing two of  the 
ICs on the unit.  This is done at moderate cost to the user.
..@i Compatibility, IBM
..@i Compatibility, North Star
..@i Compatibility, Radio Shack

The controller has its own Z-80 4MHz microprocessor which is used 
to supervise data transfers between the disk drive and the system 
memory  without intervention of the main CPU.   This relieves the 
main CPU of time consuming processes which include head position
ing,  rotational delays,  and the usual byte-by-byte transfer  of 
data  from the diskette to main memory.   As a result,  transfers 
are faster and more efficient.   Moreover,  the main CPU has more 
time for data processing,  and thus,  supports more users  and/or 
tasks.
..@i Controller, microprocessor
..@i Controller, supervision of data transfer
..@i Controller, DMA channel

The  main  advantage of the DJDMA controller over almost all  the 
others  is  its glitch free direct memory  access  channel.  This 
advanced  "channel" concept allows the controller to  communicate 
with  S-100  memory by "stealing" bus cycles from the  main  CPU.  
This idea of an intelligent I/O channel was first implemented  by 
IBM on their famous 370 mainframes.  Now for the first time, this 
powerful concept has been implemented on the S100 bus.
..@i Intelligent I/O channel
..@i Stealing bus cycles

The  channel  has the full 24-bits of memory addressing  as  des
cribed in the proposed IEEE standard for the S-100 bus.   Also, a 
great  deal of care has been taken in the design of the interface 
circuitry so it conforms in every detail to this new standard and 
still  allows the controller to work well with  existing  systems 
designed before the standardization effort was started.
..@i IEEE standards and board compatibilty

The  board has priority logic which allows it to contend with  up 
to  sixteen  other  "temporary masters," which may also  want  to 
steal bus cycles from the main CPU (the permanent master).
..@i Temporary master
..@i Permanent master

The  features  associated  with the intelligent  channel  on  the 
controller  make it exceptionally desirable in multi-tasking  and 
multi-user applications.   In fact, many were tailored to enhance 
the performance of Morrow Designs new, powerful DECISION I multi-
processing IEEE 696/S-100 machine.  The DJDMA is an integral part 
of this advanced microcomputer system which incorporates many  of 
the  concepts  originally introduced by IBM in their  famous  370 
series mainframes.

The  DJDMA can boot itself up on the bus and even has a primitive 
serial port which is intended for diagnostic purposes or possibly 
even  integrating the controller into a larger S-100 system  that 
has  I/O the boot disk is not aware of.  Under  no  circumstances  
can  it  be used as a general purpose serial port to the  system, 
however, since it is inactive during disk activity.
..@i DJDMA self boot capability
 
All  in all,  there is nothing on the S-100 bus in the way  of  a 
floppy  disk controller that comes anywhere near the  performance 
and versatility of the DJDMA.  For that matter, we here at Morrow 
Designs  know of no other floppy disk controller on any bus  that 
can match the DJDMA in price,  power, performance, and flexibili
ty.

Good  luck with this product.   One of the purposes of this docu
ment is to detail how the DJDMA controller can improve the  speed 
and performance of your system.  If we've missed anything, please 
let us know.
.pa
..@a
                   PROGRAMMING SPECIFICATIONS


..@b
The Channel Concept

.he Programming Specifications 
The  IBM 370 mainframe was the first computer system to make  use 
of  the  channel concept.   In the traditional  setting,  an  I/O 
controller,  even  one that could do direct memory accesses,  was 
given commands and reported status through I/O  ports.   Usually, 
the  commands  were  sent one at a time and status  was  reported 
after a command had completed.
..@i Channel Concept vs. Traditional Concept
..@i DMA communication with main memory

One  of  the things a Direct Memory Access Controller  does  (and 
should do well) is communicate with main memory.  Having realized 
this,  someone  very clever at IBM reasoned that if a  controller 
could communicate with memory all that easily,  why  shouldn't it 
pick its commands up from memory as well?   For that matter,  why 
not  have  it lay down its status information in the  CPU's  main 
memory also?  

Once the idea of picking up one command from memory is  accepted, 
it  is  only a small step to think about placing strings of  com
mands  in memory and having the controller begin treating  memory 
in the same way as the CPU does itself!   That is,  memory should 
be used for both instructions and data.

There is one detail missing in the above discussion.   How is the 
controller to be started and stopped?  A  CPU starts running when 
power is turned on and continues (in theory) forever.   But  then 
there  is  the situation of a device whose primary job it  is  to 
transfer  information to and from main memory and a mass  storage 
device of some kind; it should remain idle until the CPU tells it 
otherwise.

A  possible  solution to the problem above is to have the  device 
sample  a  memory location for a  start  command.   At  power-up, 
however,  solid state memory does not have a predictable pattern. 
A start command could be present before it was actually issued by 
the  CPU.   The  only fool proof way to issue a start command  is 
through an I/O port.  But doesn't that put us right back where we 
started?  Actually, it doesn't.

It takes very little I/O circuitry to issue a simple pulse  which 
can serve as a start command.  It is also a small price to pay in 
cost  and circuit board real estate for the flexibility and effi
ciency that is obtained.  
..@i Start command, I/O circuitry

Stop commands are much easier.   Simply build an instruction into 
the  controller's  command set that forces it back  to  the  idle 
state  it was in just prior to the initial start pulse issued  by 
the CPU.
..@i Stop command
 
Obviously,  a  channel type of controller needs some kind of  on-
board  intelligence.   At the time that IBM first built this kind 
of  device,  it  was expensive both in terms of  dollars  and  in 
circuit board real estate to implement this intelligence.   Today 
however,  the situation is quite different.   Microprocessors are 
inexpensive  and take only a modest amount of space on a  circuit 
board.

In theory,  the only limitation to the power and flexibility of a 
channel  driven controller is the size of the memory local to the 
resident  microprocessor.   Since  memory is getting  denser  and 
cheaper,  it would seem that time will favor the channel approach 
to I/O controllers.


..@b
The Start Channel Command

Just  as in the general case discussed above,  there is a  single 
primitive I/O port on the DJDMA.  It resides at location EF (hex) 
unless a custom unit has been ordered with a special I/O address.  
The  only  purpose of this port is to send start  pulses  to  the 
DJDMA  controller.   Any  output  instruction to  port  EF  (hex)  
starts  the DJDMA.  It doesn't matter what value is sent nor does 
it matter what kind of device sends the data. Any time any output 
reference  is made to this port by the main CPU  (permanent  mas
ter),  or  even by a temporary master,  the DJDMA begins fetching 
and executing commands.   Where these commands come from and  how 
they work is taken up below.
..@i Primitive I/O port - DJDMA
..@i Permanent master
..@i Temporary master


..@b
The Channel Command Address

When the DJDMA first powers up or is reset, there is a three-byte 
pointer initialized in its local memory.  This pointer determines 
where  the  controller  picks up its first command when  a  start 
pulse is issued via I/O port EF(hex).
..@i Power-up or reset pointer

There  are  actually  two of these three-byte  values  the  DJDMA 
maintains.  The first points to where it should start its command 
sequence.   The  second  points to where it should get  its  next 
command in the event that the current one is not a halt  command.  
The  user needs to be aware of both of these pointers as he  sets 
up command sequences for the controller to execute. 
..@i Program Counter

The  second pointer has the same function as the program  counter 
of  the main CPU:  it always points to the next command that  the 
controller  will  execute.   The first pointer is similar to  the 
value forced into the program counter (PC) of the main CPU when a 
reset signal is issued.  In most cases, a reset signal forces a 0 
into  the PC.  The processor commences to fetch  instructions  at 
this value.
.pa
The  same  is true for the DJDMA,  except that the value  is  not  
zero.  Also, unlike the CPU, this initial location can be changed 
by  a sending the proper command to the controller.  The  initial 
location    that    the   DJDMA   controller   begins    fetching               
commands from is 50 (hex).  The command that alters this starting 
location is described below.


..@b
Command Structure        
 
Commands  to  the DJDMA controller are at least two  bytes  long.  
The  first  byte is always the  command  code.   Parameter  lists 
follow  the command byte (if needed) and the command status  byte 
(if  needed) comes at the end of the command string.   The length 
of a command string varies with the command.  Unless a branch  in 
channel  command is issued,  commands must be arranged in  memory 
one  after the other with no gaps between the end of one  command 
and  the  beginning of another.   Sequences of commands  must  be 
terminated  with either a controller halt command or a branch  in 
channel  command.   If  a sequence ends with a branch in  channel 
command,  another  sequence  of commands must be present  at  the 
location specified in the address parameter list of the branch in 
channel command.
..@i Parameter lists
..@i Command status byte

..@b
DJDMA Controller Commands

The Disk Jockey DMA controller recognizes the following commands:

               - SET DMA ADDRESS
               - READ A SECTOR
               - WRITE A SECTOR
               - SENSE DRIVE STATUS
               - SET INTERRUPT REQUEST
               - SET ERROR RETRY COUNT
               - READ TRACK
               - WRITE TRACK
               - OUTPUT SERIAL PORT
               - SERIAL INPUT ENABLE/DISABLE
               - CONTROLLER HALT
               - BRANCH IN CHANNEL
               - SET CHANNEL ADDRESS
               - SET TRACK SIZE
               - SET DRIVE DESELECT/HEAD UNLOAD TIMEOUT
               - SET LOGICAL DRIVE
               - READ CONTROLLER MEMORY
               - WRITE CONTROLLER MEMORY
               - BRANCH TO CONTROLLER ROUTINE
..@i Listing of DJDMA Controller Commands

The last three commands require great care to use.  They are used 
to  format  diskettes and will be used to support  media  formats 
which  are not yet implemented.   Improper use of any of the last 
three commands could produce unpredictable results and may  cause 
the  loss  of information on write enabled diskettes   in  drives 
connected to the controller.  It could  also cause the controller 
to be inoperative until a bus reset is performed. 


Morrow Designs will have a separate document (at extra cost) that 
describes the firmware on the DJDMA controller.  This information 
should  be  available at the end of first quarter 1982  or  early 
second quarter.   Thus, users with special applications will have 
a  way  to extend the command structure of the DJDMA  controller.  
However,  extended  commands will not be supported by Morrow  De
signs  and  we cannot stress too strongly that  efforts  in  this 
direction  will require a great deal time and  expertise to  com
plete and debug.


..@b
Controller Command Specifications:
.he Command Specifications

..@c
    SET DMA ADDRESS

          Command code:                      23 (hex)
          Command length:                     4 bytes
          Command parameter list length:      3 bytes
          Command status list length:         0 bytes
     
    The  command  length is four bytes.   The first byte  is  the 
    command code:  23 (hex).   The next three bytes specify a 24- 
    bit  address in main memory where data is written to or  read 
    from  during subsequent disk transfers.   This field must  be 
    arranged  so  that the least significant byte of the  address 
    directly follows the command byte.   The byte of next highest 
    significance follows.   The highest order byte of the address 
    is last.  The last byte specifies an extended page as defined 
    in  the proposed IEEE standard for the S-100 bus  and  allows 
    memory addressing to be extended to 24 million bytes. 
..@i Extended addressing

    In  systems that do not support this new extended addressing, 
    the value of this high order byte is not important.  However, 
    it must be present - whether it is used or not.   Other  com
    mands which have three byte address fields in their parameter 
    list  require  the same byte significance order as  described 
    above.   The  firmware that processes commands on  the  DJDMA 
    expects  all address fields to be three bytes long - even  if 
    only  two of the three have effect on the address bus of  the 
    system.

    The  following example is a command that sets the DMA address 
    of  the  controller to location 80 (hex) - the  default  disk 
    data buffer of the popular CP/M operating system:  

                         23 80 00 00  (hex).

.pa
..@c
    READ SECTOR

          Command code:                      20 (hex)
          Command length:                    5 bytes
          Command parameter list length:     3 bytes
          Command status list length:        1 byte

    The  three-byte  parameter field following the  command  code        
    consists of

                                                       
                             1. track

                             2. side/sector

                             3. drive

    in that order.   The side select is encoded in the high order 
    bit  of  the  sector field and merged together  to  form  the 
    second  byte  in the parameter list.   The third byte  deter
    mines which of eight possible drives are read.  If the system 
    has been booted up from a 5 1/4 inch drive,  drives 0 through 
    3 specify this;  drives 4 through 7 specify 8 inch drives. If 
    the system has been booted from an 8 inch drive,  the number
    ing is reversed with the first  four being 8 inch drives  and 
    the  last four being 5 1/4 inch.  The following example is  a 
    command that reads data from sector 3 of track 5 on side 1 of 
    drive 0:

                           20 05 83 00 00

    The  last zero is provided so that the controller can fill in 
    the  status of the transfer after it has completed the  read.  
    Here is a second example that reads sector 2 from track 6  on 
    side 0 of drive 1:

                           20 06 02 01 00

    Again,  the  last byte is for status reporting and it must be 
    there.       

    The  length  of the sector (and consequently  a  valid  range        
    of  sector  values)  depends  on what  size  drive  is  being        
    addressed  and  how  the media has been  formatted.   In  the        
    media  currently supported,  the following sector values  and        
    data field lengths are relevant:

       5 1/4" hard sectored single density:  0 - 9  256 bytes
       5 1/4" hard sectored double density:  0 - 9  512 bytes
       8" soft sectored single density:      1 - 26 128 bytes
       8" soft sectored double density:      1 - 26 256 bytes
       8" soft sectored double density:      1 - 15 512 bytes
       8" soft sectored double density:      1 - 8 1024 bytes
..@i Listing of valid sector values
       
    The  numbers in the above list are all decimal.   The  sector 
    size,  density,  and  valid  range of values for  the  sector 
    number  are all determined automatically by  the  controller.  
    The  controller can inform the system of these parameters  by 
    executing  the  SENSE DRIVE STATUS command which is taken  up 
    below.  These details are presented here because it is neces
    sary to know how much space the controller will use when data 
    is  read from the disk into main  memory.   Also,   an  error 
    occurs  if  incorrect  values are specified for  the  sector, 
    track, or drive.

    All 8 inch drives presently have 77 tracks numbered 0 through 
    76.   This is not the case with 5 1/4 inch drives.  Some have 
    35 tracks numbered 0 through 34,  others have 40 tracks  num
    bered 0 through 39, and finally, the new double track density 
    5 1/4 inch drives have 80 tracks numbered 0 through 79.   The 
    default  value  for  5 1/4 inch drives on the  DJDMA  is  40.  
    However,  this  value can be changed by executing a SET TRACK 
    SIZE command which is discussed below.
..@i Track numbering

    The last byte in the read sector command is called the status 
    byte.   This byte should be filled with some value other than 
    what  the controller might use when it reports  status  after 
    the command is completed.   A 0 is ideal since the controller 
    does not use this value.  For that matter, it does not use FF 
    either.   Either of these values are handy  since they can be 
    tested  easily.   By testing the status byte,  the system can 
    determine when a read  command (among others) has  completed.  
    Below  is a list of status byte codes along with their  mean
    ings.  All values are in hex:
                     
              40 -       normal completion - no errors
              80 -       improper command code
              81 -       illegal disk drive value
              82 -       drive not ready
              83 -       illegal track value
              84 -       unreadable media
              85 -       improper sector header - no sync byte
              86 -       CRC error in sector header read
              87 -       seek error
              88-8D -    compare error in sector header scan
              8E -       CRC error in data field
              8F -       illegal sector value for current media
              90 -       media is write protected (writing only)
              91 -       lost data - DMA channel did not respond
              92 -       lost command - channel did not respond
..@i Listing of status byte codes

    The  above  list is complete and applies to any command  that 
    that reports status in its last byte.  Not all codes apply to 
    all  commands.   For example,  90 (hex) never appears as  the 
    status reported by the read sector command.

.pa
..@c
    WRITE SECTOR

          Command code:                      21 (hex)
          Command length:                     5 bytes
          Command parameter list length:      3 bytes
          Command status list length:         1 byte

    The  three-byte parameter field and the status byte have  the 
    same properties as those in the read sector command.  All the 
    items discussed in the read sector command apply to the write 
    sector  command  with  the exception that  the  write  sector 
    command can report a media write protect error (90 hex).

..@c
    SENSE DRIVE STATUS 

          Command code:                      22 (hex)
          Command length:                     6 bytes
          Command parameter list length:      1 byte
          Command status list length:         4 bytes

    The  single  byte in the parameter list  specifies  a  drive.  
    Legal values range from 0 to 7.   The last byte of the status 
    list  has  codes which were listed above in the  READ  SECTOR 
    command.   The  first three bytes of status are peculiar to a 
    specific  drive and are detailed below.   However,unless  the 
    last  status byte contains a 40 (hex),  the  preceding  three 
    bytes do not accurately  reflect the condition and character
    istics of the drive whose status was supposed to be sensed. 

    If any value other than 40 (hex) is present,  nothing can  be 
    learned  from the first three status bytes.   When the  final 
    byte  contains a 40 (hex),  the first three describe  charac
    teristics  and  status concerning the drive specified in  the 
    parameter byte of the command.


         STATUS BYTE 1: drive characteristic byte.
..@i Status byte descriptions
.pa
    Each bit in this byte describes a different characteristic of 
    the drive specified in the parameter field of the command.

        Bit 0 - Information internal to the controller.

        Bit 1 - If  the media is hard-sectored,  this bit is a 1.         
                When  the  media in the  drive  is  soft-sectored         
                this bit will be a 0.

        Bit 2 - If the drive is 5 1/4 inch,  this bit is a 1.  If 
                the drive is 8 inch, the bit is a 0.

        Bit 3 - If  the  drive  has a DC  motor  with  an  ON/OFF 
                switch,  this bit is a 1.   If there is no ON/OFF         
                switch,  or  if the drive motor is AC,  this  bit         
                is a 0.

        Bit 4 - If the media in the drive is double density, this 
                bit is a 1.   It is 0 only if the media is single 
                density.

        Bit 5 - If  this  bit  is a 1 there is no  "drive  ready"         
                signal supplied by the drive.  For drives with no 
                "ready" signal,  the DJDMA firmware tests for the 
                presence of sector/index holes.  If the drive has 
                an active "ready" signal, this bit is a 0. 

        Bit 6 - If  there is no "head load" command line  to  the         
                drive,  the  controller assumes that the  head(s)         
                are  always loaded against the media and this bit         
                is a 1.  If there is a "head load" command line         
                to the drive, this bit is a 0.

        Bit 7 - If  the head(s) are currently loaded against  the         
                media,  this bit is a 1.  If the head(s) are  not 
                loaded, this bit is a 0.

         STATUS BYTE 2: sector length code - 0, 1, 2, or 3.

    The 0 indicates a sector length of 128 bytes,  1 stands for a 
    length  of 256 bytes,  2 means that the length is 512  bytes,  
    and  3 indicates that the sector is 1024 bytes  long.   These 
    are all decimal numbers.

           STATUS BYTE 3: drive status/characteristic byte.

    There  is an input port on the controller which  can  examine 
    status  signals transmitted directly from the selected drive.  
.pa
    The third status byte is a direct image of this port.

        Bit 0 - Used  internally  by the controller and is of  no         
                meaning to the system.

        Bit 1 - Current  status of the serial input line from  an         
                RS-232 device which may be attached to  connector 
                P3, the serial port of the controller.

        Bit 2 - This  bit  indicates that a double-sided  8  inch 
                drive is currently selected and that double-sided 
                media is present in the drive.   This line is not 
                driven  by 5 1/4 inch drives;  thus,  an indirect 
                means  must be employed to determine if a  5  1/4 
                inch  drive is double-sided and has  double-sided 
                media in it.
                
        Bit 3 - Currently not used.

        Bit 4 - This is the index/sector hole indicator.  If this 
                bit is a 1,  the drive has sensed the presence of         
                either an index hole or a sector hole.

        Bit 5 - If this bit is a 1,  the head(s) of the drive are 
                at  Track  0.   If  the  head(s)  are  positioned         
                over some other track, this bit is a 0.

        Bit 6 - This  bit  is  a 1 if the media in the  drive  is 
                write protected.  A zero indicates that the media         
                is  not write protected and disk  write  commands  
                do not produce "write protect" errors.

        Bit 7 - This  is the drive ready bit.   Most 5  1/4  inch 
                drives have no signal on this line;  thus,  it is 
                not a good "drive ready" indicator in this case.
  
                All  8  inch drives produce a "ready"  signal  at 
                this  bit.   If  the current drive is 8 inch  and 
                this  bit is 1,  the drive is "ready"  to  accept 
                read, write, or step commands.  If it is a 0, the 
                8  inch drive is not "ready" and will not respond 
                to commands from the controller.

.pa
..@c
    SET INTERRUPT REQUEST

          Command code:                      24 (hex)
          Command length:                     2 bytes
          Command parameter list length:      0 bytes
          Command status list length:         1 byte

    This command generates an interrupt to the system bus.  There 
    is  a  bus  driver on the DJDMA circuit  board  whose  output 
    terminates  at a jumper pad near the lower edge of the  board 
    (the exact location is described later in the manual).   This 
    jumper pad is arranged so that the driver can be connected to 
    the main interrupt line of the system bus (PINT*) or any  one 
    of the eight vectored interrupt lines (VI0*, VI1*, ... VI7*). 
..@I Interrupt lines

    The  controller  is shipped from the factory with the  driver 
    uncommitted.   If the DJDMA is to generate interrupts to  the 
    system,  this  driver  must be connected to one of  the  nine 
    interrupt lines.   If the driver is not connected, the INTER
    RUPT  REQUEST  command causes the controller to  pause  until 
    another start pulse is issued by the system.   However,  once 
    an  INTERRUPT REQUEST command is executed,  the controller is 
    put into a special state where the board responds differently 
    to the start pulse than it usually does. 

    Normally   a  start  pulse causes  the  controller  to  begin 
    fetching  commands  at  the location specified  by  the  most 
    recent channel command word address.  When the DJDMA executes 
    an INTERRUPT REQUEST,  it activates the interrupt bus  driver 
    on  the circuit board.   It then pauses with this bus  driver 
    still active. 

    Upon  receipt of the next start pulse,  the controller  turns 
    off  the bus driver generating the interrupt and fetches  the 
    command  which immediately follows the interrupt request com
    mand.   The  controller  thus treats the  first  start  pulse 
    issued  after the interrupt request command has completed  as 
    an  INTERRUPT ACKNOWLEDGE handshake signal. This is the  only 
    circumstance  in which a start pulse to the  controller  does 
    not cause the command pointer to be reset.  

    The  system  can test the status byte following  the  command 
    code  to determine when the command has completed.   When the 
    command completes,  it fills the status byte with a 40 (hex).  
    When  the interrupt request bus driver is not  connected,  an 
    interrupt  request  command  causes the controller  to  pause 
    until  the  next start pulse is received,  at which  time  it 
    resumes executing commands where it left off. 
.pa
..@c
    SET ERROR RETRY COUNT

          Command Code:                      28 (hex)
          Command length:                     2 bytes
          Command parameter list length:      1 byte
          Command status list length:         0 bytes

    This command specifies how many times a sector is read in the 
    event  that a CRC error occurs in the data field.   At  least 
    one  read  always takes place,  so the  smallest  value  that 
    should  appear in the parameter byte is a 1.   This value can 
    be as high as 255 (decimal).   The default value is 10 (deci
    mal).
  
    This command's main purpose is  to ensure that the value  can 
    be  made smaller for diagnostic purposes.   It is also useful 
    when  a diskette becomes worn and data recovery becomes  more 
    difficult.  In this case, the value is made larger. 


..@i Data recovery 
..@C
    SET LOGICAL DRIVE

	  Command code:			     2E (hex)
	  Command length:		      3 bytes
	  Command parameter list length:      1 byte
	  Command status list length:	      1 byte

    This command allows the user to change the logical  numbering     
    assigned  to the 8 inch and  5 1/4 inch drives.   The default 
    values assigned the the 8 inch drives are 0 through 3,  while 
    the 5 1/4 inch drives are assigned values 4 through 7.
  
    If a 4 appears in the parameter list of this command,  the  5 
    1/4 inch drives are assigned drive values 0 through 3,  while 
    the  8 inch drives have their values changed to 4 through  7.  
    A  0  in  the parameter field reverses these  values  to  the 
    original default values.  There is no status  byte associated 
    with  this  command and bit-2 in the parameter field  is  the 
    only part of the byte examined by the command.

    The  status byte reported by the command reflects the logical 
    value  of  the  first  physical 8 inch  drive  prior  to  the 
    execution of the SET LOGICAL DRIVE command.  If the status is 
    40(hex),  the previous logical value of the first physical  8 
    inch  drive was 0.   If the status is 44(hex),  the old value 
    was 4.

    The  logical values assigned to the drives are also  affected 
    by performing a bootstrap operation which is discussed later.
..@I Changing the logical numbering of the drives
.pa
..@C
    SET HEAD UNLOAD/DRIVE DESELECT TIMEOUT

    	  Command Code:			     2F (hex)
    	  Command length:		      2 bytes
    	  Command parameter list length:      1 byte
    	  Command status list length:	      0 bytes

    During periods of disk inactivity, in order to conserve power 
    and maximize diskette life,  the controller unloads the drive 
    head(s)  and  deselects the drive after a certain  number  of 
    revolutions of the diskette.   Normally, the controller waits 
    sixteen  revolutions before it deselects a drive.   This com
    mand allows the user to change this situation.   The value in 
    the  parameter  list determines how  many  revolutions  occur 
    after  no  disk activity before the head(s) are unloaded  and 
    the drive is deselected.   A disk transfer operation requires 
    more time if the drive is not selected and so,  under certain 
    conditions,  it may be desirable to extend the time before  a 
    drive  is deselected after a transfer occurs.   This  command 
    makes it possible to affect this situation.  The value in the
    parameter  field  should  be  between 1  and  255  (decimal).  
    However,  when  the heads are loaded for extended periods  of 
    time with the motor running diskette media life is  shortened 
    considerably.

..@c
    READ TRACK

          Command code:                      29 (hex)
          Command length:                     8 bytes
          Command parameter list length:      6 bytes
          Command status list length:         1 byte

    This command reads an entire track into main memory  starting 
    at  the  value specified by the most recent SET  DMA  ADDRESS 
    command.   The  transfer  begins with the first  full  sector 
    encountered by the controller.  Thus, the buffer may not fill 
    from the beginning.

    As an example,  suppose that the diskette had eight 1024 byte 
    sectors  and  the first full sector of data  encountered  was 
    Sector  6.   In  this case the last 3072 bytes of the  buffer 
    would be filled with Sectors 6,  7,  and 8.  The DJDMA memory 
    pointer would then be reset to the start of the track  buffer 
    and Sectors 1 through 5 would be transferred.

    The first three bytes of the parameter list specify 

                              1. track

                              2. side

                              3. drive

    in that order.  The side bit must appear in the most signifi
    cant bit of the byte.  Thus, the second byte in the parameter 
    list  is either 0 or 80 (hex).   The last three bytes of  the 
    parameter  list  form  a memory pointer to  a  sector  table.  
    There  must be an entry in this table for each sector on  the 
    track. 
    As an example,  if the diskette in the selected drive had 512 
    byte  sectors,  there would be fifteen entries and the  table 
    length would also be fifteen.   This table should be initial
    ized with 0s, 80s (hex), or FFs (hex). 

    As  a sector of the track is read,  the controller fills  the 
    byte  of  the table corresponding to the sector  with  status 
    information  concerning that particular sector (assuming  the 
    initial entry was 0).   Thus,  the system can determine error 
    information individually, sector by sector. 

    If the controller encounters an FF (hex) entry in the  sector 
    table, it skips that sector which corresponds to the entry.

    If a whole section of the table has FFs,  the sectors corres
    ponding to this section are not read.

    If  the  controller  encounters an entry in the table  of  80 
    (hex),  the READ TRACK command  terminates at that point.  An 
    example should illustrate these ideas.

    Suppose  side  1 of track 23 (decimal) is to be read  into  a 
    track  buffer starting at location 00E000 (hex) from drive  2 
    and  that  a  set DMA address command  with  this  value  has 
    already been executed.  Suppose also that there are 1024 byte 
    sectors  on  the  diskette and that the sector  table  is  to 
    immediately precede the track buffer in memory.   The command 
    to read the track would then appear as follows:

                       29 17 80 02 F8 DF 00 00

    The sector table address of 00DFF8 (hex) has a value of eight 
    less  than 00E000 (hex) since there are eight sectors on  the 
    track of the diskette.  The last byte (indicated with a value 
    of  00)  is  the overall status byte for  the  command.   The 
    status  codes are the same as the READ SECTOR  COMMAND  where 
    they are listed.


..@c
    WRITE TRACK

          Command Code:                      2A (hex)
          Command length:                     8 bytes
          Command parameter list length:      6 bytes
          Command status list length:         1 byte

    The  write track command is  similar to the READ  TRACK  com
    mand.   The  six bytes of the parameter list are exactly  the 
    same  and even the sector table entries work the same.   Nor
    mally,  the table has 0s as entries.  Sectors that are not to 
    be  written (or rewritten) are marked with FFs (hex) while an 
    80 (hex) causes the command to terminate.  

    As  with the read track command,  the starting address of the 
    track buffer is initialized with a SET DMA ADDRESS command.
..@c
    OUTPUT TO SERIAL PORT

          Command code:                      2B (hex)
          Command length:                     3 bytes
          Command parameter list length:      1 byte
          Command status list length:         1 byte

    This command communicates with the output portion of the  bit 
    serial port on the DJDMA.   The parameter byte is filled with 
    the ASCII value that is to be transmitted to the RS232 device 
    connected to the port.  The status byte should be initialized 
    to  either 0 or FF (hex).   The command fills the status byte 
    a  40  (hex) when all eight data bits and two stop bits  have 
    been transmitted. 
    ..@i Serial port communication

    The  speed  of this serial port is 9600 baud  and  cannot  be 
    changed.   Also,  it  is  vital that the system refrain  from 
    sending new start pulses to the controller until this command 
    has completed.   Otherwise, transmission of the serial stream 
    is aborted before any or all of the bits have been sent.  

    The main purpose of the port in this subsystem is to allow  a 
    user to boot-up in a system where I/O devices are not defined 
    on the  boot diskette.  This port is not adequate as a system 
    consul  port and will cause the controller to run less  effi
    ciently  while the port is active (there is no disk  activity 
    while  the  serial  port is engaged  in  data  transmission).  
    Input  serial data can also be easily lost if the  controller 
    is supervising data transfer to or from a disk drive.  

    The  input side of this serial port does not work the same as 
    the output and is discussed in the next command.
..@i Undefined I/O devices 


..@c
    SERIAL INPUT ENABLE/DISABLE

          Command Code:                      2C (hex)
          Command length:                     2 bytes
          Command parameter list length:      1 byte
          Command status list length:         0 bytes

    This  command enables or disables input from the  bit  serial 
    RS232  port  on the controller.   Serial input operates in  a 
    slightly different manner than serial output.   If the  input 
    side of the port is enabled,  characters received by the port 
    are deposited at location 00003E (hex). 

    After  loading  a new character at this  location,  the  con
    troller  writes  40  (hex) at location  00003F  (hex).   This 
    second location serves as a status flag for serial input  and 
    should  be  reset to some other value after the  reading  the 
    character. 
..@i Status flag for serial input

    In  the  enable/disable command,  the value of the  parameter 
    byte  determines  whether  the  port  is  to  be  enabled  or 
    disabled.   A 0 in this byte instructs the controller to turn 
    off the port, while a 1 forces the DJDMA to enable input.  At 
    boot-up,  input is enabled,  but if there is no terminal con
    nected to the board, it is automatically disabled. 
..@i Port enable and terminal connection


..@c
    CONTROLLER HALT

          Command code:                      25 (hex)
          Command length:                     2 bytes
          Command parameter list length:      0 bytes
          Command status list length:         1 byte

    This command is used to halt the DJDMA controller.  There are 
    no parameters.  The status byte should be initialized to 0 or 
    FF  (hex).   The controller fills this byte with a  40  (hex) 
    when  the command completes.   As mentioned previously,  this 
    command resets the command pointer.   Hence,  the next  start 
    pulse  causes the controller to begin fetching commands  from 
    the  channel command word address which has an initial  value 
    of  000050 (hex).   This value can be changed with a  command 
    that is described below.
..@i Command Pointer reset


..@c
    BRANCH IN CHANNEL

          Command code:                      26 (hex)
          Command length:                     4 bytes
          Command parameter list length:      3 bytes
          Command status list length:         0 bytes

    The  three  parameter bytes specify a branch address for  the 
    controller.   This  address  is the location from  where  the 
    controller fetches its next command.   The address bytes  are 
    arranged  so that the low order byte immediately follows  the 
    command  code,  the  middle order byte is next and  the  high 
    order byte is last.   There is no status code and immediately 
    after  execution,  the  controller picks up the next  command 
    from the branch address.
.pa
..@c
    SET CHANNEL ADDRESS

          Command code:                      27 (hex)
          Command length:                     4 bytes
          Command parameter list length:      3 bytes
          Command status list length:         0 bytes

    The  three parameter bytes of this command specify  a  memory 
    address.   After this command has executed, start pulses from 
    the  system cause the controller to fetch its first  instruc
    tion at this address.   The order of the bytes is the same as 
    the  branch  in  channel command.   There is no  status  byte 
    associated with this command.


..@c
    SET TRACK SIZE

          Command Code:                       2D (hex)
          Command length:                     4 bytes
          Command parameter list length:      2 bytes          
          Command status list length:         1 byte

    This command allows the system to change the number of tracks 
    that the controller assumes are on a disk drive.   The  first 
    byte  in the parameter list describes a drive and should have 
    values  between 0 and 7.   Other values cause the command  to 
    return an error and not change the track value of any  drive.  

    The second byte must contain a hex number which is one larger 
    than  the  largest numerical track on the diskette.   For  35 
    track  drives,  this  value is 35 since the  track  numbering 
    starts at zero.   For the same reason, the value is 40 for 40 
    track  drives,  77 for 77 track drives,  and 80 for 80  track 
    drives.  (All the numbers used in this paragraph are decimal.  
    They  must be changed to hexadecimal when  incorporated  into 
    the command string.)

    It  is  possible to damage a drive if seeks are performed  to 
    tracks which extend beyond the boundaries of the seek  mecha
    nism.  The controller has no way to determine if a particular 
    value  is improper for a given drive.  The user must exercise 
    care  in executing this command and Morrow Designs  takes  no 
    responsibility for damage that occurs through its misuse.
.pa
..@c
    READ CONTROLLER MEMORY 

          Command Code:                      A0 (hex)
          Command length:                     8 bytes
          Command parameter list length:      7 bytes
          Command status list length:         0 bytes

    The  first  three bytes of the parameter list specify a  main 
    memory address with bytes in ascending order  (just like  the 
    other commands that required a three-byte address field.)

    The  next  two bytes specify a count which  can  have  values 
    anywhere between 0 and FFFF (hex).  The last two bytes speci
    fy  an address in the memory of the on-board Z-80A  micropro
    cessor.   This  command transfers local memory to main memory 
    which  allows the main CPU to read the  controller's  memory.  
    It is not advisable to read location 4001 (hex),  8001 (hex), 
    A000  (hex),  etc.,  since this type of reference  causes the 
    controller  to hang waiting for data from a drive  when  none 
    are  selected.   The  only way to reliably recover from  this 
    fault is to issue a reset to the system.  Morrow Designs does 
    not  recommend use this command and does not  support  appli
    cations that make use of this command or the two that follow.  
    This command reports no status.


..@c
    WRITE CONTROLLER MEMORY

          Command Code:                      A1 (hex)
          Command length:                     8 bytes
          Command parameter list length:      7 bytes
          Command status list length:         0 bytes

    The  first three bytes of the parameter list specify  a  main 
    memory  address in ascending order (just like the other  com
    mands that required a three-byte address field.)

    The  next  two specify a count that can range between  0  and 
    FFFF (hex).  

    The  last two bytes specify an address in the memory space of 
    the  on-board Z-80A microprocessor.   This command  transfers 
    data from main memory to the memory of the controller.  There 
    are only 1024 bytes of RAM on the controller board.  This RAM 
    starts  at location 1000 (hex).   The only locations safe  to 
    write in are between 1030 (hex) and 127F (hex).   Writing  in  
    other  locations  produces unpredictable results and can lead 
    to  loss of data on diskettes which are not  write  protected 
    and  are  inserted  in drives connected  to  the  controller. 
    Morrow  Designs  does  not support the use of  this  command.  
    This command is used in diskette format programs (included in 
    this  manual) but we strongly recommend that it not  be  used 
    for other purposes).  There is no status byte associated with 
    this command.
    ..@i Z-80A - memory transfer


..@c
    EXECUTE CONTROLLER ROUTINE

          Command Code:                      A2 (hex)
          Command length:                     3+ bytes
          Command parameter list length:      2 bytes
          Command status list length:         0+ bytes

    The two bytes in the parameter list specify an address in the 
    memory  space  of the on-board  Z-80A  microprocessor.   This 
    command  forces the on-board processor to branch to and begin 
    executing instructions at this address.  As with the previous 
    command,  it is extremely dangerous and should not be used by 
    anyone  except those well versed with the inner  workings  of 
    the controller.   The status list length is given as 0+ bytes 
    because  the  length and type of status varies  depending  on 
    the nature of the routine at the specified address.  As  with 
    the  previous two commands,  Morrow Designs does not  support 
    use of this command.     
.pa
..@b
Command Summary:
.he  Command Summary

   - Set DMA (low, med, high)
   - Read Sector (track, side/sector, drive, status)
   - Write Sector (track, side/sector, drive, status)
   - Sense Status (dstat1, dstat2, dstat3, status)
   - Set Interrupt Request (status)
   - Set Error Retry Count (count)
   - Set Logical Drive (drive, type)
   - Set Head Unload/Drive Deselect Timeout (revolution count)  
   - Read Track (track, side, drive, low, med, high, status)
   - Write Track (track, side, drive, low, med, high, status)
   - Serial Port Output (ASCII byte)
   - Serial Input Enable/disable (control byte)
   - Controller Halt (status)
   - Branch in Channel (low, med, high)
   - Set Channel Address (low, med, high)
   - Set Track Size (drive, hitrack)

 Commands not supported in the field:
   - Read CMemory (tlow, tmed, thigh, lcnt, hcnt, slow, shigh)
   - Write CMemory (slow, smed, shigh, lcnt, hcnt, tlow, thigh)
   - Execute Controller Routine (low, high, ..., ...)



..@b
Status Code Summary:

     STATUS CODE         DESCRIPTION

     40 ................ Normal completion - no error encountered
     80 ................ Improper Command Code
     81 ................ Improper Disk Drive Value
     82 ................ Disk Drive Not Ready
     83 ................ Improper Track Value
     84 ................ Unreadable Media
     85 ................ Improper Sector Header - No Sync Byte(s)
     86 ................ CRC Error in Sector Header Scan
     87 ................ Seek Error
     88 - 8D ........... Compare Error in Sector Header Scan
     8E ................ CRC Error in Data Field
     8F ................ Improper Sector Value
     90 ................ Media Write Protected
     91 ................ Lost Data - DMA Channel did not respond
     92 ................ Lost  Command - Channel did not respond
.he IEEE 696 (S-100) Bus Considerations
.pa
..@a
               IEEE 696 (S-100) BUS CONSIDERATIONS

The  DJDMA  controller  has been designed to  meet  the  IEEE/696 
proposed standard for the S-100 bus and will operate properly  in 
any  S-100  mainframe which meets this proposed standard and  can 
accommodate temporary bus masters.   In fact,  the DJDMA  runs in 
most  existing S-100 systems in  operation  today.   However,  we 
cannot  guarantee  that the controller will operate in  a  system 
unless  it meets all the specifications contained in the IEEE/696 
document.

In  transferring  data  from  a floppy disk  directly  into  main 
memory, the DJDMA assumes that the permanent master in the system 
will  respond  to bus requests by the controller fast  enough  so 
that data will not be lost.   If an 8  inch double density  drive 
is connected to the controller, a byte of data is read or written 
every 16 microseconds.
..@i Data transfer

The  transfer  rate for single density 8 inch drives  and  double 
density 5 1/4 inch drives is a byte every 32 microseconds.  

Single density 5 1/4 inch drives have a transfer rate of one byte 
every  64 microseconds.   If some device,  such as a front panel, 
holds the READY line of the bus down for extended periods  during 
disk  transfers,  data is lost and the controller cannot function 
properly.

Morrow Designs assumes that the user has made the proper determi
nation  concerning  the ability of his system to respond  to  bus 
requests  from  the DJDMA so that data is not  lost  during  disk 
transfers.   Morrow  Designs is not  responsible for operation of 
the controller in systems that cannot respond to bus requests  at 
least  as  fast as those detailed above for the various types  of 
floppy disk drives.



..@a
                           INTERRUPTS
.he Interrupts

At the lower left area of the DJDMA circuit board, just above the 
edge  connector fingers,  is a jumper area designed so users  can 
connect  the board's interrupt request bus driver to one  of  the 
nine interrupt request lines: VI0*, VI1*, VI2*, VI3*, VI4*, VI5*, 
VI6*,  VI7*,  or PINT* (See the component layout for an illustra
tion of this area).

If  the system does not use interrupts,  there is no need to con
nect J3 to any of these lines.  If J3 is not jumpered, it appears 
to the system that the controller has entered a pause state  when 
it  executes  an interrupt request command.   All activity  stops 
(just  as  it does after a halt command).   When the  next  start 
pulse is sent to the controller, it picks up its next instruction 
from the memory location immediately following the status byte of 
the  interrupt  request command (this is not the same as  a  halt 
command).
.HE I/O Connectors   Jumpered Settings
..@i Considerations for jumpering interrupt request lines
The  DJDMA  is  shipped from the factory  without  any  jumpering 
between J3 and the interrupt request lines.  If the controller is 
to generate interrupt requests,  the user must determine which of 
the nine possible connections is appropriate for his system.  The 
DECISION  I user reference manuals contain information about  how 
the DJDMA communicates with the interrupt controller on the MULT-
I/O and WUNDERBUSS I/O boards,  and should serve as an example of 
how interrupts from the DJDMA could work in other systems.



..@a
                         I/O CONNECTORS

Refer to the component layout drawing included in this manual for 
a more complete understanding of the discussion in this section.


There  are three I/O connectors at the top of the  DJDMA  circuit 
board: P1, P2, and P3.

P3 is at the top left-hand side of the board and is the connector 
for  the bit serial RS232 port.   It has three pins,  numbered  1 
through 3 from left to right.   Pin-1 is the RS232 ground signal, 
pin-2 is the input and pin-3 is the RS232 output signal.

To the right of P3 is P2.   P2 has 34 pins and is used to connect 
5  1/4 inch drives to the controller.   The pins are arranged  in 
two  rows - the odd numbered pins being just above the even  num
bered ones.   The pins are numbered 1 through 33,  odd from right 
to left,  and 2 through 34, even from right to left.  All the odd 
numbered  pins  are connected to ground while the  even  numbered 
pins carry information to and from 5 1/4 inch floppy disk drives.
          
P1  is the right-most connector and has 50 pins.   This connector 
is  used to connect 8 inch drives to the controller and has  pins 
arranged in two rows, the same as P2.  The upper pins are odd and 
are  numbered 1 through 49,  right to left.   The lower pins  are 
even and are numbered 2 to 50, right to left.  As before, all odd 
pins  are  grounds  while  even pins carry  signals  between  the 
controller  and 8 inch drives. 



..@a
                        JUMPERED SETTINGS

Refer to the component layout drawing included in this manual for 
a more complete understanding of the discussion in this section.
.HE Jumpered Settings

..@B
EPROM Replacement

The  jumpered  setting  at J1 (located in the  upper  right  hand 
corner of the board) is factory set B to C for a 2732 EPROM.   It 
may  be jumpered A to B,  effectively replacing it  with  a  2716 
EPROM.   But  please note that the factory setting must be  main
tained for proper system operation.  The optional setting reduces 
the  address  space available and is only to be used in  special, 
limited applications.



..@b
Bootstrap Program

J2 (located in the lower mid-section of the board) is jumpered  B 
to C for conditional bootstrap operation.   This mode is used for 
the Decision I and controllers are shipped from the factory  with 
a jumper between these two pins.

J2  is  jumpered A to B for non bootstrap mode in  systems  which 
cannot allow a temporary master to hog the bus and intend to boot 
the DJDMA controller by external means.



..@A
                        BOOTSTRAP LOADING

.he Bootstrap Loading
The  DJDMA   performs  an automatic bootstrap load  at  reset  or 
power-on  if J2 is jumpered B to C and a shunt jumper  is  placed 
between  pins 2 and 3 of P3 or if a terminal is connected to  P3.  
In  either  case,  the controller halts the  main CPU  by  taking 
control  of the bus and reads the first 38(hex) locations in main 
memory into its own local memory.  Next it loads zeros into these 
first  38(hex)  bytes and places a short (19 byte decimal)  hand
shake  routine between 000038(hex) and 00004A(hex).  The  bus  is 
then  released  and when the main CPU executes the first part  of 
the handshake routine,  the controller restores the first 38(hex) 
locations of main memory to its original  state.   Next,  80(hex) 
bytes  are  loaded between 000080(hex) and 0000FF(hex)  from  the 
first sector on track zero of the disk.   Finally, the controller 
writes  a control byte to the handshake routine which causes  the 
main CPU to branch to location 000080(hex).   A listing of the 19 
byte handshake routine is givin below

     000038    21 4A 00       START:    LXI  H,4A
     00003B    36 00                    MVI  M,0
     00003D    7E             LOOP:     MOV  A,M
     00003E    B7                       ORA  A
     00003F    CA 3D 00                 JZ   LOOP
     000042    FE 40                    CPI  40H
     000044    C2 3D 00                 JNZ  LOOP
     000047    C3 80 00                 JMP  80H
     00004A    FF                       DB   0FFH


The  controller will boot from either the  first drive  connected 
to the 8 inch port or the first drive connected to the 5 1/4 inch 
port.   The  decision as to which port to choose is determined by 
testing for a "drive  ready" signal.   The 8 inch port is  tested 
first.   The  controller  will alternately continue to  test  for 
"drive  ready" indefinitely  to allow  the user time to insert  a 
diskette.   This is evidenced by the indicator lights on the disk 
drives.  They will alternately blink as the controller checks for 
the ready signal.

The following is the proper procedure for booting the DJDMA:

     1.  Open the door of any drive the DJDMA could boot from.

     2.  Insert  a bootstrap diskette in the boot  drive  WITHOUT          
         closing the driver door.

     3.  Depress the RESET switch.

     4.  While  the  RESET switch is depressed,  close the  drive          
         door.

     5.  Release the RESET switch.

It  is possible that the above procedure will have to be repeated 
twice depending on the value of location 0.


If a shunt jumper across pins 2 and 3 of P3 is not in place or if 
a terminal is not connected to P3,  the controller powers  itself 
up  in normal "cycle steal" mode and waits for commands from  the 
system.
..@i Cycle steal mode


..@a
                       DISKETTE FORMATTING

.he Diskette Formatting
There  are no firmware commands on the DJDMA to format  diskettes 
for  two  reasons:   Formatting is a dangerous  operation.  If  a 
diskette is in  a drive with valuable information written on  it, 
an  accidental format command could destroy this data.   The con
troller is also capable of formatting a wide variety of diskettes  
and the EPROM is not large enough to accommodate both the command 
processor code and all of the desirable format routines.
..@i Dangers of formatting diskettes

For  these  reasons,  the format routines are  loaded  from  main 
memory  using  the WRITE CONTROLLER MEMORY command and   executed 
using the EXECUTE CONTROLLER ROUTINE command.   A listing of  two 
format programs for  IBM soft-sectored 8 inch diskettes and North 
Star hard-sectored 5 1/4 inch diskettes appears as an appendix to 
this manual.   These programs are also available on diskettes for 
a  modest cost for those who wish to avoid using controller  com
mands  not supported in the field.

When a CP/M operating system is shipped with either a lone  DJDMA 
controller  or  a disk system which includes a DJDMA  controller, 
there  are  built-in commands on the system diskette  which  will 
format both types of diskettes.
.pa
.HE Parts List
..@a
                           PARTS LIST


Amount    Function            Description

  1       PC board            DJDMA
  5       Diode               1N914
  1       Transistor          2N3904
  6       Transistor          2N3906

  2       Regulator           +5 volts
  1       Regulator           +12 volts
  1       Regulator           -12 volts

  1       Resistor            1K Ohm 1/4W 5%
  2       Resistor            1 Meg Ohm  1/4W  5%
  1       Resistor            12K Ohm 1/4W 5%
  1       Resistor            1.2K Ohm 1/4W 5%
  1       Resistor            1.5K Ohm 1/4W 5%
  1       Resistor            180 Ohm 1/4W 5%
  2       Resistor            27K Ohm 1/4W 5%
  4       Resistor            330 Ohm 1/4W 5%
 11       Resistor            3.3K Ohm 1/4W 5%
  1       Resistor            390 Ohm 1/4W 5%
  3       Resistor            4.7K Ohm 1/4W 5%
  1       Resistor            47K Ohm 1/4W 5%

  1       Resistor            2.0K Ohm 1/4W 1%
  1       Resistor            20.0K Ohm 1/4W 1%
  1       Resistor            28.0K Ohm 1/4W 1%

  1       SIP                 180K 1/8W 5% (10-pin)
  1       SIP                 3.3K 1/8W 5% (8-pin

  1       Inductor            4.7uh

  1       Capacitor           .001mf ceramic disk
 13       Capacitor           .1uf mono cap
  1       Capacitor           .01 mylar cap
  1       Capacitor           33pf silver/mica
  2       Capacitor           47pf silver/mica 
  2       Capacitor           100pf silver/mica
  1       Capacitor           1200pf silver/mica
  1       Capacitor           620 pf silver/mica
  8       Capacitor           1uf dip. tant.

  1       Crystal             4 MHz

  1       PCB Header          SIN RT> NHD 3
  1       PCB Header          DIN RT> HD 34
  1       PCB Header          DIN RT> HD 50

  2       Slide Jumpers       

  2       Screws              632 X 5/16 Pan Phil
                          Parts List, Cont.

  2       Hex Nuts            632

  2       Heat Sinks          Low Profile 3 Fin
  2       Heat Sinks          Slimline 5 prong

  1       IC Socket           Low Profile (8-pin)
 13       IC Sockets          Low Profile (14-pin)
 12       IC Sockets          Low Profile (16-pin)
  2       IC Sockets          Low Profile (18-pin)
 15       IC Sockets          Low Profile (20-pin)
  1       IC Socket           Low Profile (24-pin) 
  1       IC Socket           Low Profile (28-pin)
  1       IC Socket           Low Profile (40-pin)            

  1       IC                  1458

  2       IC                  2114-3 RAM

  1       IC                  7404
  1       IC                  7406

  1       IC                  74LS02
  1       IC                  74LS04
  1       IC                  74LS08
  1       IC                  74LS10
  2       IC                  74LS138
  1       IC                  74LS139
  1       IC                  74LS153
  3       IC                  74LS221
  1       IC                  74LS244
  2       IC                  74LS273
  1       IC                  74LS279
  1       IC                  74LS299
  4       IC                  74LS373
  4       IC                  74LS374
  1       IC                  74LS38
  1       IC                  74LS393
  3       IC                  74LS74
  1       IC                  74LS75

  1       IC                  81LS95
  1       IC                  81LS96

  1       IC                  PAL
  1       IC                  FPLA
  5       IC                  PROM

  





