PLE5P8                                     PLE DESIGN SPECIFICATION
P5028                                            S. HORIKO 11/29/83
TIMING GENERATOR FOR PAL SECURITY FUSE PROGRAMMING
MMI JAPAN
.ADD A0 A1 A2 A3 A4
.DAT NA0 NA1 NA2 NA3 NA4 TVCC TP01 TP11

; NEXT ADDRESS GENERATOR
;  ( THE COUNTER LOCKS UP AT COUNT-22 )

NA0  = /A4*        /A1*/A0       ; INCREMENTER (LSB)
     + /A4*         A1*/A0       ; INCREMENTER (LSB)
     +  A4*/A3*/A2*    /A0       ; INCREMENTER (LSB)
     +  A4*/A3* A2*/A1           ; INCREMENTER (LSB)

NA1  = /A4*        /A1* A0       ; INCREMENTER (BIT1)
     + /A4*         A1*/A0       ; INCREMENTER (BIT1)
     +  A4*/A3*/A2*/A1* A0       ; INCREMENTER (BIT1)
     +  A4*/A3*/A2* A1*/A0       ; INCREMENTER (BIT1)

NA2  = /A4*     A2*/A1           ; INCREMENTER (BIT2)
     + /A4*     A2*    /A0       ; INCREMENTER (BIT2)
     + /A4*    /A2* A1* A0       ; INCREMENTER (BIT2)
     +  A4*/A3* A2*/A1           ; INCREMENTER (BIT2)
     +  A4*/A3*/A2* A1* A0       ; INCREMENTER (BIT2)

NA3  = /A4* A3*/A2               ; INCREMENTER (BIT3)
     + /A4* A3*    /A1           ; INCREMENTER (BIT3)
     + /A4* A3*        /A0       ; INCREMENTER (BIT3)
     + /A4*/A3* A2* A1* A0       ; INCREMENTER (BIT3)

NA4  = /A4* A3* A2* A1* A0       ; INCREMENTER (MSB)
     +  A4*/A3*/A2               ; INCREMENTER (MSB)
     +  A4*/A3*    /A1           ; INCREMENTER (MSB)

; TIMING WAVEFORMS

TVCC = /A4                       ; TIMING FOR VCC
     +  A4*/A3*/A2*/A1 
     +  A4*/A3*/A2*    /A0 

TP01 = /A4*/A3* A2               ; TIMING FOR PIN 01
     + /A4*/A3*     A1 
     + /A4*/A3*         A0 
     + /A4* A3*/A2*/A1*/A0 

TP11 = /A4* A3* A2               ; TIMING FOR PIN 11
     + /A4* A3*     A1 
     +  A4*/A3*/A2*/A1


FUNCTION TABLE

A4 A3 A2 A1 A0 NA4 NA3 NA2 NA1 NA0 TVCC TP01 TP11

;          NNNNN
;AAAAA     AAAAA   TIMING WAVEFORMS
;43210     43210   TVCCP  TP01 TP11     ; ## ;    COMMENTS
--------------------------------------------------------------------------
 LLLLL     LLLLH     H     L    L       ; 01 ;    ASSERT TVCC, START HERE
 LLLLH     LLLHL     H     H    L       ; 02 ;    ASSERT TP01
 LLLHL     LLLHH     H     H    L       ; 03 ; 
 LLLHH     LLHLL     H     H    L       ; 04 ;
 LLHLL     LLHLH     H     H    L       ; 05 ;
 LLHLH     LLHHL     H     H    L       ; 06 ;
 LLHHL     LLHHH     H     H    L       ; 07 ;
 LLHHH     LHLLL     H     H    L       ; 08 ;
 LHLLL     LHLLH     H     H    L       ; 09 ;    CLEAR TP01
 LHLLH     LHLHL     H     L    L       ; 10 ;    ASSERT TP11
 LHLHL     LHLHH     H     L    H       ; 11 ; 
 LHLHH     LHHLL     H     L    H       ; 12 ;
 LHHLL     LHHLH     H     L    H       ; 13 ;
 LHHLH     LHHHL     H     L    H       ; 14 ;
 LHHHL     LHHHH     H     L    H       ; 15 ;
 LHHHH     HLLLL     H     L    H       ; 16 ;
 HLLLL     HLLLH     H     L    H       ; 17 ;
 HLLLH     HLLHL     H     L    H       ; 18 ;
 HLLHL     HLLHH     H     L    L       ; 19 ;    CLEAR TP11
 HLLHH     HLHLL     L     L    L       ; 20 ;    CLEAR TVCC
 HLHLL     HLHLH     L     L    L       ; 21 ; 
 HLHLH     HLHLH     L     L    L       ; 22 ;    LOOP HERE UNTIL RESET
--------------------------------------------------------------------------


DESCRIPTION

THIS LOGIC SPECIFICATION IS A TIMING SIGNAL GENERATOR TO BE USED FOR
SECURITY FUSE PROGRAMMING OF PAL DEVICES.  A PLE5P8 FOLLOWED BY AN
8-BIT REGISTER ARE USED TO IMPLEMENT THIS FUNCTION.

THE PLE CONTAINS TWO FUNCTIONS IN THE SINGLE CHIP.  THE FIRST FUNCTION
IS A UNIQUE COUNTER USED FOR NEXT ADDRESS GENERATION.  THE COUNTER
INCREMENTS UP TO COUNT-21 AND THEN LOCKS UP THE INCREMENTAL OPERATION AT
COUNT-22.  THE SECOND FUNCTION IS A TIMING GENERATOR USED FOR DEFINING
TIMING RELATIONSHIP AMOUNG VCC, P01, AND P11 SIGNALS (SEE "PAL
PROGRAMMING" IN THE PAL DATA SHEET FOR MORE DETAILS.)

THE SCHEMATIC IS AS FOLLOWS:

                  PLE       REGISTER
                 ------      ------
                 |    |      |    |
                 |    |      |    |---\ TVCC, TP01, TP11
        A(0:4)   |    |-----\|    |---/
            |---\|    |-----/|    |----|
            | |-/|    |      |    |--| | NA(0:4)
            | |  |    |      |    |  | |
            | |  ------      ------  | |
            | |      CLK _____|  |   | |
            | |      RESET ______|   | |
            | |----------------------| |
            |--------------------------|
                PLE5P8        8-BIT REGISTER

THIS LOGIC OUTPUTS A SEQUENCE OF TIMING PATTERNS DURING THE INCREMENTAL
OPERATION AND THEN HOLDS ALL OUTPUTS LOW UNTIL RESET SIGNAL FOR THE
8-BIT REGISTERED IS APPLIED.

APPLYING 200 KHz CLOCK SIGNAL TO THE CLK INPUT OF THE REGISTER, THE
FOLLOWING TIMINGS ARE GENERATED:

 1. VCC WIDTH  : 95 usec
 2. TPP        : 40 usec
 3. tD         :  5 usec

BY APPLYING THIS DESIGN METHOD, WE CAN EASILY GENERATE A SEQUENCE OF
UNIQUELY DEFINED PATTERNS EACH TIME THE RESET PULSE IS APPLIED.
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