ASMB,A,B,L,C
      HED 2100 SERIES MEMORY DIAGNOSTIC(LOW)
      ORG 2B
*     UNL 
*     REP 62
*     OCT 106077
      UNL 
      REP 62
      OCT 106077
      LST 
* 
********************************************************************
* 
* 
* DIAGNOSTIC CHECKS MEMORY OPERATION
* 
* DIAGNOSTIC ASSUMES THE FOLLOWING TESTS HAVE BEEN RUN
* 
*    MEMORY REFERENCE GROUP  DSN 101000 
*    ALTER-SKIP GROUP        DSN 101001 
*    SHIFT-ROTATE GROUP      DSN 101002 
* 
* RUNS IN 4K MEMORY 
* 
* CONSOLE NOT REQUIRED
* 
* DIAGNOSTIC CONFIGURATOR IS OPTIONAL 
* 
* DIAGNOSTIC SERIAL NO(DSN) 102200
* 
* OPERATING INSTRUCTIONS: 
* 
*     1.  LOAD AND CONFIGURE DIAGNOSTIC CONFIGURATOR (OPTIONAL) 
* 
*     2.  LOAD MEM DIAGNOSTIC.
* 
*     3.  SET P REGISTER = 100. (SET P = 130 TO START WITH LOW
*         MEMORY MODULE(RESIDES LOW(2-1777) AND TESTS HIGH).) 
* 
*     4.  SELECT PROGRAM OPTIONS IN SWITCH REGISTER.
* 
*     5.  PRESS PRESET(INT. & EXT. IF PRESENT) AND RUN. 
* 
*     NOTE-WHEN PROGRAM IS TESTING LOW MEMORY(2-1777),THE DSN AT
*         LOCATION 126 IS WIPED OUT. IT SHOULD BE LOCATED AT
*         ADDRESS 3624. 
      SKP 
* 
*************** SWITCH REGISTER OPTIONS ****************************
* 
* 
* 
*   BIT        MEANING
* 
*    0         RUN ADDRESS TEST(BIT/DECODER-21MX) 
*    1         RUN ALT WORD PATTERN TEST(COLUMN-21MX) 
*    2         RUN WORD PATTERN TEST(ROW-21MX)
*    3         RUN BIT 0 TEST(DISTURBANCE-21MX) 
*    4         RUN RANDOM NUMBER TEST 
*             *NOTE-BITS 0 THRU 4 CLEAR WILL RESULT IN TESTS 0-3
*                   BEING RUN.
*    5         STORE ERROR OCCURRING ABOVE 8K AND NOT DUE TO MOVE 
*              COMPARISONS IN THE ERROR TABLE.(LIMITED TO FOUR
*              ERRORS PER 4K).
*    6         CLEAR ERROR TABLE(LOW MEMORY MODULE ONLY). 
*    7         RESERVED.
*    8         CLEAR IF CONFIGURATOR IS LOADED AND CONFIGURED.
*              SET IF CONFIGURATOR IS NOT LOADED. 
*    9         RESERVED.
*    10        EXIT TO RESTART LOW MEMORY MODULE
*    11        HALT UPON RETURN TO LOW MEMORY MODULE. 
*    12        LOOP ON DIAGNOSTIC. CLEAR TO HALT AT END OF PASS.
*    13        LOOP ON SELECTED TEST. 
*    14        SUPPRESS ERROR HALTS.
*    15        HALT AT END OF TEST
* 
* 
********************************************************************
* 
      SKP 
* 
* 
*************** COMPUTER HALTS *************************************
* 
*   HALT       MEANING
* 
*  102005      ERROR TABLE DISPLAY (A=NXT AVAILABLE ADDRESS OF TABLE
*                                  (B= # OF ERRORS) 
*  102006      ERROR TABLE RAN OVER LOCATION 2000. PROGRAM WIPED OUT
*  102007      PARITY ERROR IN PGM AREA 
*  102013      PARITY ERROR IN TEST AREA
*  1020XX      MEMORY ADDRESS/DATA ERROR
* 
*                XX  TEST 
*                10  PROGRAM NOT MOVED CORRECTLY. AN ERROR
*                    OCCURRED WHILE RELOCATING A SECTION OF 
*                    THE PROGRAM. DETERMINE HIGH OR LOW AND 
*                    START FROM THE GOOD MODULE. (A) = GOOD DATA, 
*                    (B) = BAD DATA. PRESS RUN FOR ADDRESS. 
*                20   1    (A)= DATA WRITTEN INTO MEMORY
*                30   2    (B)= DATA READ FROM MEMORY 
*                40   3 
*                50   4A
*                52   4B
*                60   5 
*  1020YY      MEMORY ADDRESS/DATA ERROR
*              YY=XX+1 (A)=FAILING ADDRESS
*  102076      HALT AT END OF EACH TEST 
*  102077      END OF TEST CYCLE
*  103004      UNEXPECTED POWER FAIL
*  103077      NONEXISTENT MEMORY READ OTHER THAN ALL 0'S 
*  106005      MEMORY PROTECT INTERRUPT 
*  106077      UNEXPECTED TRAP CELL INTERRUPT 
* 
* 
* 
* 
******************************************************************* 
* 
      SKP 
* 
*     ERROR TABLE FORMAT: 
* 
*     M   ADDRESS OF ERROR
*     M+1 GOOD DATA(DATA WRITTEN) 
*     M+2 BAD DATA(DATA READ) 
*     M+3 RESERVED
*     M+4 NUMBER OF TIMES AN ERROR OCCURRED AT THIS ADDRESS 
* 
*     THE ERROR TABLE STARTS AT 1600. FIVE LOCATIONS PER ERROR. 
*     FOUR ERRORS PER 4K ABOVE 8K(ADDITIONAL ERRORS WITHIN THE
*     4K MODULE ARE IGNORED). 
* 
*              TABLE ADDRESSES
*              RESERVED FOR THE 
*     MODULE   MODULE 
* 
*     2        1600-1623
*     3        1624-1647
*     4        1650-1673
*     5        1674-1717
*     6        1720-1743
*     7        1744-1767
* 
      SKP 
* 
*              WORST CASE MEMORY PATTERN EQUATIONS
* 
********************************************************************
* 
* 
*   COMPUTER       EQUATION                         MEMORY TYPE 
* 
*    2100A          (M5 EOR M6)F                       CUPERTINO 4/8
*    21MX           M6F                                SEMICONDUCTOR
* 
* 
*** NOTE  MX= MEMORY ADDRESS BITS  ***
***       EOR = EXCLUSIVE OR       ***
* 
********************************************************************
* 
* 
*        SEMICONDUCTOR MEMORY FUNCTIONAL TESTS
* 
********************************************************************
* 
*   COMPUTER       TEST                             MEMORY TYPE 
* 
*    21MX                                           SEMICONDUCTOR 
* 
*                  CHIP TEST :         PATTERN USED : 
* 
*                   (1) BIT/DECODER 
*                         *    *       P = ADDRESS
*                   (2) COLUMN
*                         *    *       P = M0 PASS 1 0'S,1'S
*                         *    *              PASS 2 1'S,O'S
*                   (3) ROW 
*                         *    *       P = M5 PASS 1 32-O'S,32-1'S
*                         *    *              PASS 2 32 1,S,32-O'S
*                   (4) DISTURBANCE 
*                         *    *       P = M5 PASS 1 SLIDING O,1 32L
*                         *    *              PASS 2 SLIDING 1,O 32L
* 
* 
********************************************************************
* 
      SKP 
      ORG 2B
      NOP 
      DEF HMPPE 
      HLT 4,C       POWER FAIL INT
LPEIT JSB LMPPE     MEMORY PROTECT/PARITY ERROR INT 
      ORG 100B
      JMP L2000,I   GO START WITH HIGH MEMORY TEST
      ORG 105B
      DEF FWAM
      ORG 126B
      OCT 102200
      SPC 3 
A     EQU 0 
B     EQU 1 
SWR   EQU 1 
      ORG 130B
      JMP LPE       GO START WITH LOW MEMORY TEST 
BJMP1 JMP NEXT9     JMP NEXT9 INSTRUCTION 
LTYPE OCT 0 
LSTBL OCT 17        TESTS 0-3 
LWTBL OCT 2 
      OCT 2000
      OCT 4777
LFRST EQU LWTBL+1 
LFWA  EQU LWTBL+1 
LLAST EQU LWTBL+2 
LLWA  EQU LWTBL+2 
LDM16 DEC -16       LOOP COUNT
LMMG  OCT 10
LMFG  OCT 0 
LADDR OCT 0         CURRENT WORKING ADDRESS 
LPTN1 OCT 0         DATA PATTERN 1
LPTN2 OCT 0         DATA PATTERN 2
LLPC  OCT 0         LOOP COUNTER
LBPT1 OCT 1         BIT PATTERN 1 
LBPT2 OCT 177776    BIT PATTERN 2 
LBPTS OCT 0         BIT PATTERN SAVE
LMSB  OCT 77777     BIT 15 MASK 
MB4   OCT -4
M10K  OCT -10000
M30K  OCT -30000
B4    OCT 4 
B5    OCT 5 
L10   EQU LMMG
LB20  OCT 20
B24   OCT 24
LB30  OCT 30
LB37  OCT 37
LB40  OCT 40
LB50  OCT 50
LB52  OCT 52
LB60  OCT 60
LHLTS OCT 0 
LHLT  HLT 0 
L2000 OCT 2000
B3500 OCT 3500
B4700 OCT 4700
B4777 OCT 4777
B5000 OCT 5000
B6500 OCT 6500
LLDCM BSS 1         CONFIGURATOR ADDRESS
TEMP  BSS 1 
LMAX  BSS 1         MAXIMUM MEMORY ADDRESS
* 
* 
*    LRST TESTS SWR BIT 10 FOR PROGRAM RESTART
*         IF IT IS SET THE PROGRAM RESTARTS SKIPPING
*            CONFIGURATION SECTION
*         IF IT IS NOT SET A NORMAL RETURN IS MADE
* 
LRST  NOP 
      LIA SWR 
      ALF,RAL 
      SSA           TEST FOR RESTART
      JMP LPE2
      JMP LRST,I
      SKP 
* 
* 
*    LPE  START OF PROGRAM
* 
LPE   EQU * 
      JSB MEMRY     GO DETERMINE PARAMETERS 
      LDA LTYPE 
      CPA LMMG      TEST FOR NEW TYPE 
      RSS 
      CLA 
      STA LMFG
      LDA LTYPE 
      ADA LMSK1     FORM MASK 1 POINTER 
      STA LMS1      SAVE
      LDA LTYPE 
      ADA LMSK2     FORM MASK 2 POINTER 
      STA LMS2      SAVE
      LDA LSDM1 
      STA LSDS1 
      NOP 
      NOP 
      NOP 
      LDB LJPE
      NOP 
      NOP 
      STB LPEIT 
      LDA B5000     MOVE HIGH MEMORY
      STA LADDR      TEST MODULE
      CLE             TO LOCATIONS
      LDA B3500        5000-6477
      LDB L2000 
      JSB MOVE
      LDA B4777     SET TEST
      STA LWTBL+2    LIMITS OF
      LDB L2000       2000-4777 
      STB LWTBL+1 
LPE2  EQU * 
      LIA SWR 
      STA LWTBL 
      ALF 
      SSA,RSS       TEST FOR HALT AT RESTART
      JMP LTS0
      LDA LPNT1 
      LDB LCNT
      HLT 5         YES, A=ADDR, B=ERROR COUNT
      SKP 
* 
************** TEST SELECTION CONTROL  *****************************
* 
LTS0  EQU * 
      LIA SWR       SAVE
      STA LWTBL      PROGRAM OPTIONS
      AND LB37      DEFAULT SET 
      SZA,RSS        OF TESTS?
      LDA LSTBL     YES 
      STA LTSW      INITIALIZE TEST SELECT WORD 
      LDA LTSOL 
      STA LTADR     SET POINTER TO FIRST TEST ADR 
      LDA LWTBL 
      ALF,ALF 
      RAL           POSITION TEST BITS
      SSA           TEST FOR ERROR TABLE RESET
      JSB LRSET     RESET ERROR TABLE 
LTS2  LDA LTSW
      SLA,RSS       PERFORM TEST ?
      JMP LTS3      NO
LTS   JSB LTADR,I   YES 
      LIA SWR 
      SSA           TEST FOR HALT REQUEST 
      HLT 76B 
      LIA SWR 
      RAL,RAL 
      SSA           TEST FOR LOOP ON PGM
      JMP LTS 
LTS3  LDA LTSW
      ARS 
      STA LTSW      MODIFY TEST SELECT WD FOR NXT TST 
      ISZ LTADR 
      LDA LTADR 
      CPA LTEOL     TEST FOR LAST ADR 
      RSS 
      JMP LTS2      LOOK FOR NEXT TEST
BREAK NOP 
      LDA L2000     MOVE HIGH MEMORY
      STA LADDR      MODULE BACK
      CCE             TO LOCATIONS
      LDB B5000        2000-3477
      LDA B6500 
      JSB MOVE
      LDA BJMP1     SET INSTRUCTION IN
      STA BREAK      BREAK TO SKIP THIS SECTION 
      LDA B3500     MOVE CONFIGURATOR 
      STA LADDR      AND LDCM DOWN
      CCE             TO LOCATIONS
      LDA LMAX         3500-4777
      INA 
      LDB LLDCM 
      JSB MOVE
      LDA B5000     SET TEST
      STA LWTBL+1    LIMITS OF
      LDB LMAX        5000-MAXIMUM ADDRESS
      STB LWTBL+2 
      JMP LTS0      DO ANOTHER PASS W/NEW LIMITS
NEXT9 EQU * 
      LDA LLDCM     MOVE CONFIGURATOR 
      STA LADDR      BACK TO
      CLE             LOCATIONS 
      LDA B4700        X6500-X7700
      LDB B3500 
      JSB MOVE
      CLA           RESTORE NOP 
      STA BREAK      TO BREAK 
      LIA SWR       CHECK 
      ALF,RAR        BIT 12 
      SSA,RSS 
      HLT 77B 
      JMP 100B      DO ANOTHER PASS 
LTADR BSS 1 
LTSW  BSS 1 
LTSOL DEF *+1,I 
      DEF LADRT 
      DEF LSWRD 
      DEF LWORD 
      DEF LPATT 
      DEF LRNT
LTEOL DEF *,I 
      SKP 
*************** LOW MEMORY ADDRESS TEST ****************************
* 
*    LADRT PERFORMS ADDRESS TEST BY 
* 
*         (1) WRITING LOC ADDRESS INTO LOCATION FOR 
*             ALL AVAILABLE MEMORY LOCATIONS
*         (2) READING AND TESTING ALL LOCATIONS 
* 
LADRT NOP 
      LDA LB20
      STA LHLTS     SAVE HALT TYPE
      CLO           INDICATE WRITING MEMORY 
      LDA LFWA      STORE ADDRESS INTO
LAW1  STA A,I       LOCATION
      CPA LLWA      TEST FOR LAST ADDRESS 
      JMP LAR       EXIT
      INA           NEXT ADDRESS
      JMP LAW1
LAR   STO           INDICATE READING MEMORY 
      LDB LFWA      INITIALIZE
      STB LADDR     ADDRESS POINTER 
      STB LHLD2     PATTERN HOLD
      LDB LADDR,I 
      CPB LADDR     ADDRESS = TO ADDRESS CONTENTS 
      RSS 
      JSB LER1      NO
      JSB LRST      TEST FOR PGM RESTART
      LDB LADDR     YES 
      CPB LLWA      LAST ADDRESS
      JMP LAW2      GO DO ADDRESS COMPLIMENT TEST 
      INB           INCREMENT 
      JMP LAR+2     CONTINUE
LAW2  CLO           INDICATE WRITING MEMORY 
      JSB LRST      TEST FOR PGM RESTART
      LDB LFWA      LOAD 1ST ADDRESS
LAW3  LDA B         LOAD A
      CMA           COMPLIMENT ADDRESS
      STA B,I       STORE TO LOCATION 
      CPB LLWA      TEST FOR LAST ADDRESS 
      JMP LAR2      GO TO READ
      INB           NEXT ADDRESS
      JMP LAW3
LAR2  STO           INDICATE READING MEMORY 
      LDB LFWA      INITIALIZE
LAR3  STB LADDR     ADDRESS POINTER 
      CMB 
      STB LHLD2     PATTERN HOLD
      LDB LADDR,I 
      CPB LHLD2     ADDRESS COMP = TO ADDRESS CONTS 
      RSS 
      JSB LER1      NO
      LDB LADDR     RELOAD CURRENT ADDRESS
      CPB LLWA      LAST ADDRESS
      JMP LADRT,I   YES 
      INB           NO
      JMP LAR3      CONTINUE
      SKP 
*************** LOW MEMORY PATTERN (ALT WD) TEST *******************
* 
*    LSWRD PERFORMS ALTERNATE 1/0 PATTERN TEST
* 
LSWRD NOP 
      LDA LB30
      STA LHLTS     SAVE HALT TYPE
      LDA LJC1      SET UP
      STA LP0              PATTERN
      STA LR0                      SELECTION CALL 
      CCA 
      STA LPFG      SET PATTERN CHG FLAG
      CLA 
      CCB 
      JSB LPTN
      CCA 
      CLB 
      JSB LPTN
      JMP LSWRD,I 
      SKP 
*************** LOW MEMORY PATTERN (WORD) TEST *********************
* 
*    LWORD PERFORMS WORD PATTERN TESTING BY 
* 
*         (1) WRITING PATTERN (WORSE CASE NOISE) INTO 
*             MEMORY. PATTERN BASED ON CPU/MEMORY TYPE. 
* 
*         (2) READING AND TESTING EACH LOCATION FOR 
*             CORRECT PATTERN 
* 
*         (3) SAVING PATTERN,WRITING,READING TESTING
*             COMPLIMENT OF ORIGNAL PATTERN AND RESTORING 
*             ORIGNAL PATTERN 
* 
*         (4) REPORTING ERRORS ENCOUNTERED DURING ALL TESTING 
* 
*         (5) TEST IS PERFORMED TWICE, ONCE USING WORSE CASE
*             PATTERN AND SECOND TIME USING COMPLIMENT PATTERN
* 
LWORD NOP 
      LDA LB40
      STA LHLTS     SAVE HALT TYPE
      LDA LMFG      DETERMINE 
      SZA,RSS                 WHICH 
      JMP LW0                       PATTERN TO USE
      LDA LJC2      SET UP DIAGNONAL
      STA LP0              PATTERN
      STA LR0                      SELECTION CALL 
      JMP LW1 
LW0   LDA LJC1      SET UP NORMAL 
      STA LP0              PATTERN
      STA LR0                        SELECTION CALL 
LW1   CLA 
      STA LPFG      CLEAR PATTERN CHG FLAG
      CCB 
      JSB LPTN      PERFORM WORD PATTERN
      CCA 
      CLB 
      JSB LPTN      PERFORM ALT WD PATTERN
      JMP LWORD,I   EXIT
      SKP 
*************** LOW MEMORY PATTERN (BIT) TEST **********************
* 
*    LPATT PERFORMS BIT PATTERN TESTS 
* 
*         (1) BIT 0 PATTERN 
* 
*         (2) BIT 1 PATTERN 
* 
LPATT NOP 
      LDA LJC1      SET UP
      STA LP0              PATTERN
      STA LR0                      SELECTION CALL 
      JSB LBITO     PERFORM BITO TEST 
      JSB LBIT1     PERFORM BIT1 TEST 
      JMP LPATT,I   EXIT
      SPC 5 
* 
*    LBITO IS SAME AS LWORD WITH THE EXCEPTION OF 
* 
*         (1) PATTERN USED
* 
*         (2) TEST IS RUN 16 TIMES EACH TIME CHANGING PATTERN 
* 
LBITO NOP 
      LDA LB50
      STA LHLTS     SAVE HALT TYPE
      LDA LBPT1 
      LDB LMFG
      SZB           TEST FOR PATTERN TO BE USED 
      LDA LBPT2 
      STA LBPTS     INITIALIZE BIT O PATTERN
      LDA LDM16 
      STA LLPC      INITIALIZE LOOP COUNT 
LBOO  CLA 
      STA LPFG      CLEAR PATTERN CHG FLAG
      LDB LBPTS 
      JSB LPTN      PERFORM BIT O PATTERN 
      LDA LBPTS 
      CLB 
      JSB LPTN      PERFORM BIT O ALT PATTERN 
      LDA LBPTS 
      RAL           CHANGE BIT O PATTERN
      STA LBPTS 
      ISZ LLPC      BUMP COUNT
      JMP LBOO      CONTINUE
      JMP LBITO,I   EXIT
      SKP 
* 
*    LBIT1 IS THE SAME AS LBIT0 EXCEPT FOR INITIAL
*         PATTERN USED. 
* 
LBIT1 NOP 
      LDA LB52
      STA LHLTS     SAVE HALT TYPE
      LDA LBPT2 
      LDB LMFG
      SZB           TEST FOR PATTERN TO USED
      LDA LBPT1 
      STA LBPTS     INITIALIZE BIT 1 PATTERN
      LDA LDM16 
      STA LLPC      SET UP LOOP COUNT 
      CLA 
      STA LPFG      SET PATTERN CHG FLAG
LBT10 CCA 
      LDB LBPTS 
      JSB LPTN      PERFORM BIT 1 PATTERN 
      LDA LBPTS 
      CCB 
      JSB LPTN      PERFORM BIT 1 ALT PATTERN 
      LDA LBPTS 
      RAL           CHANGE BIT 1 PATTERN
      STA LBPTS 
      ISZ LLPC      BUMP LOOP COUNT 
      JMP LBT10     CONTINUE
      JMP LBIT1,I   EXIT
      SPC 3 
* 
*    LPTN PERFORMS ACTUAL TEST BY 
* 
*         (1) SAVING PATTERNS TO BE WRITTEN 
* 
*         (2) WRITING MEMORY
* 
*         (3) READING/TESTING MEMORY
* 
LPTN  NOP 
      STA LPTN1     SAVE PATTERN 1
      STB LPTN2     SAVE PATTERN 2
      CLO           INDICATE WRITING MEMORY 
      JSB LWT       WRITE PATTERN 
      STO           INDICATE READING MEMORY 
      JSB LRD       READ AND TEST PATTERN 
      JMP LPTN,I    EXIT
      SKP 
* 
*    LWT  WRITES PATTERN INTO MEMORY BASED ON CPU/MEMORY
*         TYPE BEING TESTED 
* 
LWT   NOP 
      JSB LRST      TEST FOR PGM RESTART
      LDA LFRST 
      STA LADDR     INITIALIZE FIRST ADDRESS
LP0   JSB LACK      CHECK ADR FOR PTN TYPE
      JMP LP1 
      LDA LPTN1 
      JMP LP1+1 
LP1   LDA LPTN2 
      STA LADDR,I   STORE PATTERN 
      LDA LADDR 
      CPA LLAST     TEST FOR LAST ADR 
      JMP LWT,I     EXIT
      ISZ LADDR     BUMP CURRENT ADR
      JMP LP0       CONTINUE
      SPC 3 
* 
*    LRD  READS/TESTS MEMORY BASED ON PATTERN WRITTEN 
* 
LRD   NOP 
      JSB LRST      TEST FOR PGM RESTART
      LDA LFRST 
      STA LADDR     INITIALIZE FRST ADDRESS 
LR0   JSB LACK      CHECK ADR FOR PATTERN TYPE
      JMP LR1 
      LDA LPTN1 
      JMP LR1+1 
LR1   LDA LPTN2 
      STA LGDS
      STA LHLD2     SAVE GOOD DATA
      LDB LADDR,I   READ LOCATION 
      CPB A         PATTERN OK ?
      RSS 
      JSB LER1      NO
      JSB LCMP      YES, COMPLIMENT AND TEST PTN
      LDA LADDR 
      CPA LLAST     TEST FOR LAST ADR 
      JMP LRD,I     EXIT
      ISZ LADDR     BUMP CURRENT ADR
      JMP LR0       CONTINUE
      SKP 
* 
*    LACK DETERMINES PATTERN TO BE WRITTEN INTO MEMORY
*         BASED ON THE EQUATIONS DEFINING WORSE CASE
*         PATTERN FOR A PARTICULAR CPU/MEMORY TYPE
* 
LACK  NOP 
      LDA LPFG
      SZA           TEST FOR PATTERN CHG
      JSB LSACK 
      LDA LADDR 
      AND LMS1,I    AND ADDRESS WITH MASK 1 
      ALF,ALF 
      RAL,RAL       POSITION BITS 
      STA LRNS1 
      JSB LPS 
      LDA LMS2,I
      SZA           TEST FOR ONE TERM 
      JMP LACK1     NO
      LDA LMSV2 
      SZA           TEST PARITY FOR "0" 
      ISZ LACK
      JMP LACK,I    EXIT
LACK1 AND LADDR 
      SZA,RSS       TEST FOR T OR F 
      JMP LACK2     F 
      CLA,INA 
      AND LMSV1 
      STA LMSV3     SAVE AND TERM 1 
      CLA 
      JMP LACK3 
LACK2 STA LMSV3     SAVE AND TERM 1 
      CLA,INA 
      AND LMSV2 
LACK3 STA LMSV4     SAVE AND TERM 2 
      IOR LMSV3     FORM OR OF TERM 1 & 2 
      SZA           TEST FOR "0"
      ISZ LACK
      JMP LACK,I    EXIT
                                                                                                                                                                  