
		MSV11-D Block Logic Diagram 

Qbus                                              4Kbit or 16Kbit
Signal                                              RAM Chips 

BS7 --------------------                          +-------+ +-------+     
                        \ Enable                  |       | |       |
                       +-------+  Memory SEL      |       | |       | High
BDAL17      )    5     |       | ------------     |       | |       |
BDAL16       >-------- |Address|                  |       | |       |
BDAL15      )      --  | Decode|                  +-------+ +-------+
BDAL14 -    )     |    | Logic | ----------\                          <------\
BDAL13  \   )     |    +-------+           |      +-------+ +-------+        |
       \ \        |                    ----)----> |       | |       |        |
        \ \     5 Switches            /    |      |       | |       | Low    |
         \ \                         /     |      |       | |       |        |
          \ \                       /      |      |       | |       |        |
           \ \                     /       |      +-------+ +-------+        |
BDAL12    ) \ \                   /        |        High   ^   Low           |
BDAL11    )  \ \     6/7         /         |               |                 |
BDAL10     >---->---------------/          \---------------/                 |
BDAL9     )    \               /              Bank Select                    |
BDAL8     )     \             /                                              |
BDAL7     )      \           /                                               |
                  \         /                                                |
BDAL6     )        \       /                                                 |
BDAL5     )         \ 6/7 /                                                  |
BDAL4      >--------->---/                                                   |
BDAL3     )                                                                  |
BDAL2     )                                                                  |
BDAL1     )                                                                  |
                         Byte Select                                         |
BDAL0   ---------------------------------------------------------------------/



		FM Block Logic Diagram 

Qbus                                                 256Kbit
Signal                                              RAM Chips 

BS7 ------------|>0-----                          +-------+ +-------+     
                        \ Enable                  |       | |       |
                       +-------+  Memory SEL      |       | |       | High
BDAL12      )    5     |       | ------------     |       | |       |
BDAL11       >-------- |Address|                  |       | |       |
BDAL10      )      --  | Decode|  Buffer SEL      +-------+ +-------+
BDAL9       )     |    | Logic | ------------                         <------\
BDAL8       )     |    +-------+                  +-------+ +-------+        |
                  |      |   |             /----> |       | |       |        |
            5 Switches   |   |             |      |       | |       | Low    |
                         |   |             |      |       | |       |        |
                                           |      |       | |       |        |
          (  Read:  Parity Error Bit       |      +-------+ +-------+        |
     CSR <                                 ^        High   ^   Low           |
          (  Write: 12 Bits --------------/|               |                 |
                                           |               |                 |
                                           |               |                 |
                                           |  Bank Select  |                 |
BDAL7   -----------------------------------)---------------/                 |
                                           |                                 |
BDAL6     )                                |                                 |
BDAL5     )           6                    |                                 |
BDAL4      >-------------------------------/                                 |
BDAL3     )                                                                  |
BDAL2     )                                                                  |
BDAL1     )                                                                  |
                         Byte Select                                         |
BDAL0   ---------------------------------------------------------------------/


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