



                 



                        Digital's Storage Systems Interconnect




                             ECO Controlled Version 1.0.0

                                    RELEASE VERSION

        |                            27 March 1990



                      Send inquiries and comments to SSAG::SSAG.




                                       Abstract

                   This document defines the Digital Storage Systems
                   Interconnect (DSSI).  DSSI is based on the higher
                   layer protocols of the CI (DEC STD 161)  using  a
                   different data-link and physical interconnect.







              DIGITAL EQUIPMENT CORPORATION CONFIDENTIAL AND PROPRIETARY

               This  document  is  an  unpublished  work  and  contains
               valuable   trade  secrets  which  are  confidential  and
               proprietary to Digital Equipment  Corporation,  and  may
               only be disclosed to individuals who have entered into a
               confidentiality agreement with Digital, and may  not  be
               copied or reproduced in whole or in part.

               Copyright (c) Digital Equipment Corporation  1990.   All
               Rights Reserved.






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           Digital's Storage System Interconnect               Version 1.0.0
           CONTENTS                                                  Page ii
                                                               27 March 1990


                                           CONTENTS

                   1       Preface To Version 1.0.0 . . . . . . . . . . viii


           CHAPTER 1       INTRODUCTION

                   1.1     SCA Overview . . . . . . . . . . . . . . . .  1-1
                   1.2     CI PPD Layer . . . . . . . . . . . . . . . .  1-3
                   1.3     Overview Of The DSSI Bus . . . . . . . . . .  1-5
                   1.4     Scope Of This Document . . . . . . . . . . .  1-7
                   1.5     References . . . . . . . . . . . . . . . . .  1-8


           CHAPTER 2       TERMINOLOGY AND NOTATIONAL CONVENTIONS

                   2.1     Notational Conventions . . . . . . . . . . .  2-5
                   2.1.1     Numeric Notation . . . . . . . . . . . . .  2-5
                   2.1.2     Time Unit Abbreviations  . . . . . . . . .  2-5
                   2.1.3     Bit Field Notation . . . . . . . . . . . .  2-5
                   2.1.4     Naming Conventions For Variables . . . . .  2-5


           CHAPTER 3       PORT ADDITIONS AND/OR CLARIFICATIONS

                   3.1     Port Additions And/or Clarifications . . . .  3-1
                   3.2     Unrecognized Packets . . . . . . . . . . . .  3-1
                   3.3     Self Directed Commands   . . . . . . . . . .  3-1
                   3.4     Loop Back Packets  . . . . . . . . . . . . .  3-1
                   3.5     Multibit Sequence Numbers  . . . . . . . . .  3-1
                   3.6     CI ID Response Packet Fields . . . . . . . .  3-2
                   3.7     Only Single Path In DSSI.  . . . . . . . . .  3-4


           CHAPTER 4       THE DSSI DATALINK

                   4.1     The DSSI Datalink  . . . . . . . . . . . . .  4-1
                   4.2     Overview Of A DSSI Data Transfer . . . . . .  4-1
                   4.3     DSSI Datalink Logical Description  . . . . .  4-3
                   4.4     Channel Control Services . . . . . . . . . .  4-6
                   4.5     Data Transmit And Error Recovery Layer . . .  4-7
                   4.5.1     Error Recovery Procedure . . . . . . . . .  4-8
                   4.5.2     Example Of Random Number Generator . . . .  4-9
                   4.6     Interface To The CI Port Layer . . . . . . . 4-11






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                                                               27 March 1990


           CHAPTER 5       THE DSSI PHYSICAL BUS PROTOCOL

                   5.1     The DSSI Physical Bus Protocol . . . . . . .  5-1
                   5.2     Logical Description Of The DSSI  . . . . . .  5-2
                   5.3     Signal Definitions . . . . . . . . . . . . .  5-2
                   5.4     DSSI Bus Timing [1]  . . . . . . . . . . . .  5-3
                   5.4.1     Arbitration Delay [ 2.4us ]  . . . . . . .  5-4
                   5.4.2     Assertion Period [ 90ns ]  . . . . . . . .  5-4
                   5.4.3     Bus Clear Delay [ 800ns ]  . . . . . . . .  5-4
                   5.4.4     Bus Free Delay [ 800ns ] . . . . . . . . .  5-5
                   5.4.5     Bus Set Delay [ 1.8us ]  . . . . . . . . .  5-5
                   5.4.6     Bus Settle Delay [ 400ns ] . . . . . . . .  5-5
                   5.4.7     Cable Skew Delay [ 10ns ]  . . . . . . . .  5-5
                   5.4.8     Data Release Delay [ 400ns ] . . . . . . .  5-5
                   5.4.9     Deskew Delay [ 45ns ]  . . . . . . . . . .  5-5
                   5.4.10    Hold Time [ 45ns ] . . . . . . . . . . . .  5-5
                   5.4.11    Negation Period [ 90ns ] . . . . . . . . .  5-5
                   5.4.12    Reset Hold Time [ 25us ] . . . . . . . . .  5-6
                   5.4.13    Transfer Period [  180ns ] . . . . . . . .  5-6
                   5.5     Bus Protocol . . . . . . . . . . . . . . . .  5-6
                   5.5.1     General Requirements . . . . . . . . . . .  5-8
                   5.5.1.1     Implicit Signal State  . . . . . . . . .  5-8
                   5.5.1.2     Definition Of Initiator And Target Nodes  5-8
                   5.5.1.3     Use Of And Reaction To Bus Reset ( RST )  5-8
                   5.5.1.4     Watchdog Timers  . . . . . . . . . . . .  5-9
                   5.5.2     DSSI Bus Phases And Signal Sources . . . . 5-10
                   5.5.3     BUS FREE Phase . . . . . . . . . . . . . . 5-12
                   5.5.4     ARBITRATION Phase  . . . . . . . . . . . . 5-12
                   5.5.5     Fair ( Round-Robin ) Arbitration . . . . . 5-12
                   5.5.5.1     Specification Of DSSI Arbitration 
                               Algorithm  . . . . . . . . . . . . . . . 5-13
                   5.5.5.2     Rules For Enabled Nodes  . . . . . . . . 5-14
                   5.5.5.3     Rules For Disabled Nodes . . . . . . . . 5-15
                   5.5.5.4     Rules For Manipulating The 
                               Enabled/Disabled Flag  . . . . . . . . . 5-16
                   5.5.5.5     ARBITRATION Phase Transitions  . . . . . 5-17
                   5.5.6     SELECTION Phase  . . . . . . . . . . . . . 5-18
                   5.5.6.1     SELECTION Phase Transitions  . . . . . . 5-20
                   5.5.7     Information Transfer Phases  . . . . . . . 5-22
                   5.5.7.1     Asynchronous Information Transfer  . . . 5-24
                   5.5.7.2     Synchronous Data Transfer  . . . . . . . 5-25
                   5.5.7.3     Signal Restrictions Between Information 
                               Phases . . . . . . . . . . . . . . . . . 5-27
                   5.5.7.4     Information Phase Error Conditions . . . 5-27
                   5.5.7.5     The COMMAND OUT Phase  . . . . . . . . . 5-28
                   5.5.7.6     Command Out Descriptor Validation 
                               Precedence . . . . . . . . . . . . . . . 5-31



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           CONTENTS                                                  Page iv
                                                               27 March 1990


                   5.5.7.6.1     Reserved Field Validation  . . . . . . 5-32
                   5.5.7.6.2     COMMAND OUT Phase Transitions  . . . . 5-32
                   5.5.8     The DATA OUT Phase . . . . . . . . . . . . 5-34
                   5.5.8.1     Data Block Length  . . . . . . . . . . . 5-35
                   5.5.8.2     DATA OUT Phase Transitions . . . . . . . 5-35
                   5.5.8.3     The STATUS IN Phase  . . . . . . . . . . 5-37
                   5.5.8.4     STATUS IN Phase Transitions  . . . . . . 5-37
                   5.6     Performance And Diagnostic Counters  . . . . 5-39
                   5.6.1     Counter Descriptions . . . . . . . . . . . 5-39


           CHAPTER 6       DSSI BUS ELECTRICAL AND PHYSICAL SPECIFICATION

                   6.1     Introduction . . . . . . . . . . . . . . . .  6-1
                   6.2     Electrical Description . . . . . . . . . . .  6-1
                   6.2.1     Required Signal Termination  . . . . . . .  6-1
                   6.2.2     Terminator Package . . . . . . . . . . . .  6-2
                   6.2.3     DSSI Driver  . . . . . . . . . . . . . . .  6-3
                   6.2.4     Electrical Characteristics . . . . . . . .  6-3
                   6.2.4.1     Output Characteristics . . . . . . . . .  6-3
                   6.2.4.2     Input Characteristics  . . . . . . . . .  6-5
                   6.2.5     Terminator Power Characteristics . . . . .  6-5
                   6.2.5.1     Terminator Power Dissipation . . . . . .  6-7
                   6.2.5.2     Noise Margin . . . . . . . . . . . . . .  6-8
                   6.3     PHYSICAL CHARACTERISTICS . . . . . . . . . .  6-9
                   6.3.1     Maximum Length . . . . . . . . . . . . . .  6-9
                   6.3.2     STUB LENGTH  . . . . . . . . . . . . . . . 6-10
                   6.3.3     STUB SEPARATION  . . . . . . . . . . . . . 6-10
                   6.3.4     MODULE ETCH REQUIREMENTS . . . . . . . . . 6-10
                   6.3.5     INTERNAL CONNECTOR REQUIREMENTS  . . . . . 6-10
                   6.3.5.1     Device Connectors  . . . . . . . . . . . 6-10
                   6.3.5.1.1     Female Cable Connector . . . . . . . . 6-10
                   6.3.5.1.2     Male Cable Connector   . . . . . . . . 6-11
                   6.3.6     INTERNAL CABLE REQUIREMENTS  . . . . . . . 6-11
                   6.3.7     EXTERNAL CONNECTOR REQUIREMENTS  . . . . . 6-11
                   6.3.8     EXTERNAL CABLE REQUIREMENTS  . . . . . . . 6-11
                   6.3.9     Connecting And Disconnecting A Device From 
                             The DSSI Bus . . . . . . . . . . . . . . . 6-12
                   6.3.9.1     Hot Swap Prohibited  . . . . . . . . . . 6-12
                   6.3.9.2     Power Supply Requirements  . . . . . . . 6-13
                   6.3.9.3     Mechanical Requirements  . . . . . . . . 6-13
                   6.3.9.3.1     Printed Circuit Board Wiring And 
                                 Layout Rules . . . . . . . . . . . . . 6-13
                   6.3.9.3.2     Ground Connection  . . . . . . . . . . 6-13
                   6.3.9.3.3     Pin Sequencing . . . . . . . . . . . . 6-13





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           CONTENTS                                                   Page v
                                                               27 March 1990


           APPENDIX A      FAIR ARBITRATION ALGORITHM TIMING PARAMETERS


           APPENDIX B      SII


           APPENDIX C      DSSI PARAMETER VALUES


           APPENDIX D      IMPLEMENTATION FUNCTIONALITY

                   D.1     Section 5.5.8.1 "Data Block Length"  . . . .  D-1
                   D.1.1     SWIFT And SII  . . . . . . . . . . . . . .  D-1
                   D.1.2     SHAC And DASH  . . . . . . . . . . . . . .  D-2
                   D.2     Table 5-2, "Summary Of Channel Control Layer 
                           Status Values" . . . . . . . . . . . . . . .  D-2
                   D.3     CI Port Maintenance I/D's  . . . . . . . . .  D-3


           APPENDIX E      USE OF CREDITS IN SCA/MSCP SPECIFICATIONS

                   E.1     DSSI Device Credit Management  . . . . . . .  E-4


           APPENDIX F      SCA AND MSCP CLARIFICATIONS

                   F.1     SCA Additions And/or Clarifications  . . . .  F-1
                   F.2     Format Of Buffer Descriptors And Use In 
                           SNTDAT/DATREQn Packets . . . . . . . . . . .  F-1
                   F.3     Port And VC Concepts . . . . . . . . . . . .  F-1
                   F.3.1     Example Port State Diagram In DSSI Drives   F-2
                   F.3.1.1     Uninitialzed State . . . . . . . . . . .  F-2
                   F.3.1.2     Uninitialized/Maint State  . . . . . . .  F-2
                   F.3.1.3     Enabled/Maint State  . . . . . . . . . .  F-3
                   F.4     Generation Of Unique Node Parameters . . . .  F-3
                   F.4.1     SCA And MSCP Parameters  . . . . . . . . .  F-3
                   F.4.1.1     SCA System Name  . . . . . . . . . . . .  F-3
                   F.4.1.2     SCS SYSTEMID . . . . . . . . . . . . . .  F-4
                   F.5     SCA Packet Format Clarification  . . . . . .  F-5


           APPENDIX G      REVISION HISTORY








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           CONTENTS                                                  Page vi
                                                               27 March 1990


           APPENDIX H      EXCEPTIONS

                   H.1     Policy . . . . . . . . . . . . . . . . . . .  H-1
                   H.2     Exceptions For Products Using The SII Bus 
                           Interface Chip . . . . . . . . . . . . . . .  H-1
                   H.2.1     SII Fixed Priority Arbitration Scheme  . .  H-2
                   H.3     Exceptions For SHAC/DASH . . . . . . . . . .  H-3
                   H.3.1     Target Timeout Enforcement . . . . . . . .  H-3


           APPENDIX J      TERMINATOR SELECTION


           FIGURES

                   1-1     The SCA Model  . . . . . . . . . . . . . . .  1-2
                   1-2     CI PPD Architectural Layers  . . . . . . . .  1-4
                   1-3     Comparison of CI and DSSI features . . . . .  1-7
                   4-1     Simplified DSSI Atomic Bus Sequence  . . . .  4-2
                   4-2     DSSI Datalink Model  . . . . . . . . . . . .  4-4
                   4-3     Format of Unique Initial Seed  . . . . . . . 4-10
                   5-1     Datalink Channel Control Layer . . . . . . .  5-1
                   5-2     ARBITRATION Phase Transitions  . . . . . . . 5-17
                   5-3     SELECTION Phase Transitions  . . . . . . . . 5-21
                   5-4     Format of DSSI Command Out Descriptor Block  5-29
                   5-5     COMMAND OUT Phase Transitions  . . . . . . . 5-33
                   5-6     DSSI Data Format . . . . . . . . . . . . . . 5-34
                   5-7     DATA OUT Phase Transitions . . . . . . . . . 5-36
                   5-8     DSSI STATUS IN Data Formats  . . . . . . . . 5-37
                   5-9     STATUS IN Phase Transitions  . . . . . . . . 5-38
                   6-1     DSSI Bus Electrical Configuration  . . . . .  6-1
                   6-2     DSSI Bus Terminator Arrangement  . . . . . .  6-2
                   6-3     Terminator Package Configuration . . . . . .  6-3
                   6-4     Terminator Power Configuration . . . . . . .  6-6
                   6-5     DSSI Noise Margin Definition . . . . . . . .  6-9
                   F-1     Minimum Port State Diagram in DSSI Drives  .  F-2
                   F-2     Format of PPD START Datagram . . . . . . . .  F-6
                   F-3     Detail of PPD START Datagram . . . . . . . .  F-6
                   F-4     PPD Start Datagram Packet  . . . . . . . . .  F-7
                   F-5     SCA Message Packet containing MSCP Command .  F-8
                   F-6     Format of VAX CI Port Packet . . . . . . . . F-11
                   F-7     Format of CI Packet  . . . . . . . . . . . . F-12
                   F-8     DSSI Packet Format . . . . . . . . . . . . . F-13
                   F-9     SCS Application Message in VAX CI Port 
                           Packet . . . . . . . . . . . . . . . . . . . F-14
                   F-10    SCS Application Message in DSSI Data Block . F-15




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           Digital's Storage System Interconnect               Version 1.0.0
           CONTENTS                                                 Page vii
                                                               27 March 1990


           TABLES

                   5-1     DSSI Bus Timing Values . . . . . . . . . . .  5-4
                   5-2     Summary of Channel Control Layer Status 
                           Values . . . . . . . . . . . . . . . . . . .  5-7
                   5-3     DSSI Signal Sources  . . . . . . . . . . . . 5-11
                   5-4     Information Transfer Phases  . . . . . . . . 5-23
                   6-1     DSSI Electrical Output Characteristics . . .  6-4
                   6-2     DSSI Electrical Input Characteristics  . . .  6-5
                   6-3     Terminator Power Characteristics . . . . . .  6-7
                   6-4     Terminator Power Dissipation . . . . . . . .  6-8
                   6-5     DSSI Noise Margins . . . . . . . . . . . . .  6-9
                   6-6     DSSI Signal Assignments  . . . . . . . . . . 6-12
                   C-1     DSSI General Parameters  . . . . . . . . . .  C-1
                   C-2     Selected DSSI Timing Parameters  . . . . . .  C-1
                   D-1     SHAC/DASH Differences in Channel Control 
                           Layer Status . . . . . . . . . . . . . . . .  D-3
                   D-2     CI Port Maintenance I/Ds . . . . . . . . . .  D-3
































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           Preface                                                 Page viii
           Preface To Version 1.0.0                            27 March 1990


           1  Preface To Version 1.0.0

           This release of the  specification  is  the  final  form  version
           approved  by  the  DSSI  Review  Committee on 27 March 1990.  All
           further changes to the document shall be made by ECO.













































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           INTRODUCTION                                             Page 1-1
                                                               27 March 1990


     1                                 CHAPTER 1

     2                               INTRODUCTION


     3     This specification  defines  the  architecture  for  the  Digital
     4     Storage  Systems Interconnect ( DSSI ).  The DSSI, supporting the
     5     needs of low-end and mid-range systems, is one  in  a  family  of
     6     high-performance computer-to-computer interconnects ( CI's ) that
     7     combine  a  common  host  interface  and  port  layer   with   an
     8     implementation-specific datalink and physical interconnect.

     9     1.1  SCA Overview

    10     CI-class interconnects provide the transmission services required
    11     by  Digital's  Systems Communication Architecture - a four-tiered
    12     set of protocols and interfaces as shown in figure 1-1.

































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           SCA Overview                                        27 March 1990


     1                     Node                              Node
     2               +----------------+                +----------------+
     3               |  System        |    SYSAP       | System         |
     4               |  Application   |<-------------->| Application    |
     5               |  ( SYSAP )     |    Protocol    | ( SYSAP )      |
     6               +----------------+                +----------------+
     7               | System         |    SCS         | System         |
     8               | Communications |<-------------->| Communications |
     9               | Services       |    Protocol    | Services       |
    10               | ( SCS )        |                | ( SCS )        |
    11               +----------------+    PPD         +----------------+
    12               | Port/Port      |<-------------->| Port/Port      |
    13               | Driver         |    Protocol    | Driver         |
    14               | Layer          |                | Layer          |
    15               +----------------+                +----------------+
    16                       |                                  |
    17                       -------------/......../-------------
    18                               Physical Interconnect

    19                        Figure 1-1:  The SCA Model

    20     This architecture consists of the following layers:

    21           o  System Application ( SYSAP ) - A process whose  services
    22              and  protocol  are specific to a given application.  The
    23              disk class driver is an example of such a process.  It's
    24              protocol is the Mass Storage Control Protocol ( MSCP ).

    25           o  Systems  Communications  Services   (SCS)   -   Provides
    26              facilities     for    establishing    and    maintaining
    27              communications between two Sysaps.

    28           o  Port/Port Driver Layer (PPD) - A combination of hardware
    29              and   software   that   provides   the   host   with   a
    30              device-independant.    packet-oriented   interface   for
    31              node-to-node data transfers.

    32           o  Physical  Interconnect  -   The   physical   media   and
    33              signalling  protocols  used  to  transmit  the  raw  bit
    34              stream.


    35     The basic function of the PPD layer is the delivery of packets to
    36     the  receiving  node that are free of detectable errors.  The PPD
    37     provides the following services:





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           INTRODUCTION                                             Page 1-3
           SCA Overview                                        27 March 1990


     1           o  Datagram service - The delivery of  independant  packets
     2              to  another  node  with  high  probability  of  success.
     3              Datagrams may be discarded  if  buffers  to  accommodate
     4              them are not available in the receiving node.

     5           o  Virtual Circuit Services - The transfer of data  between
     6              nodes without duplication or loss.  Virtual circuits are
     7              established between node pairs and support the following
     8              classes of service:

     9              1.  Message Service - The delivery in  correct  sequence
    10                  of one or more packets comprising a message.

    11              2.  Buffered Data Service - The  efficient  transfer  of
    12                  large   blocks  of  data  directly  to  or  from  an
    13                  application's  memory.   This   service   is   often
    14                  performed with the assistance of dedicated hardware.



    15     A  CI  implementation  consists  of  the  physical  interconnect,
    16     combined  with  hardware  and software within the PPD layer, that
    17     implements  SCA  packet  tranmission  services.   The   following
    18     section presents an overview of this layer.

    19     1.2  CI PPD Layer

    20     Figure 1-2 illustrates the layers of a PPD  implementation  built
    21     on  a CI-class interconnect.  The specifications controlling each
    22     functional element are listed in section 1.5.




















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           INTRODUCTION                                             Page 1-4
           CI PPD Layer                                        27 March 1990


     1                                                           <-----+
     2                         +---------------------+                 |  
     3                         | Port Driver         |                 |    
     4                         | Layer               |                 |    
     5                         | ( SCA Specification)|                 |    
     6                         +---------------------+                 |    
     7                                   |                             |    
     8                                   |                             |        
     9                         .......................                 |    
    10                         . CI Port Adapter     .                 |
    11                         . ( eg: VAX CI Port ) .                 |   
    12                         .......................                 |  
    13                                   |                             | P
    14       +------>                    |                             | P
    15       |                 +---------------------+                 | D
    16       |                 |     CI Port         |                 |  
    17     C |                 |     Layer           |                 | L
    18     I |                 |   ( DEC Std 161 )   |                 | A
    19       |                 +---------------------+                 | Y
    20     A |                    |               |                    | E
    21     R |             +------+               +------+             | R
    22     C |             |                             |             |     
    23     H |  +----------------------+      +---------------------+  |     
    24     I |  | DSSI Datalink        |      |    CI Datalink      |  |     
    25     T |  |    Layer             | .... |      Layer          |  |
    26     E |  | ( DSSI Spec. )       |      |  ( Dec Std 161 )    |  |
    27     C |  +----------------------+      +---------------------+  |
    28     T |             |                             |       <-----+
    29     U |             |                             |       <-----+ P L
    30     R |  +----------------------+      +---------------------+  | H A
    31     E |  |    DSSI Physical     |      |    CI Physical      |  | Y Y
    32       |  |    Interconnect      |      |    Interconnect     |  | S E
    33       |  |    ( DSSI Spec. )    |      |   ( DEC Std 161 )   |  | I R
    34       |  +----------------------+      +---------------------+  | C   
    35       +------>                                            <-----+ A  
    36                                                                   L

    37                 Figure 1-2:  CI PPD Architectural Layers

    38     The topmost layer, the port driver, provides a device-independant
    39     interface to the data transfer services provided by lower layers.
    40     It is also responsible  for  managing  the  startup  and  orderly
    41     shutdown of virtual circuits.

    42     The CI port adapter is the hardware interface that  performs  the
    43     physical transfer of packets between host memory and the CI port.
    44     The architecture of such hardware interfaces is outside the scope



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           INTRODUCTION                                             Page 1-5
           CI PPD Layer                                        27 March 1990


     1     of  SCA.   In some implementations, this function is performed by
     2     host software.

     3     The port implements the  protocols  that  provide  the  datagram,
     4     block  data and message services defined by the architecture.  It
     5     is responsible for error recovery, the detection of lost  packets
     6     within  a  message  or  block  data  transfer  and the sequential
     7     delivery of message packets.

     8     The Datalink layer is responsible for:

     9          1.  Channel control including channel access arbitration.

    10          2.  The transformation of outgoing packets into bit  streams
    11              for  transmission  over  the physical medium through the
    12              addition of addressing  data,  framing  information  and
    13              error-detection codes.

    14          3.  Recovery from transmission errors.

    15          4.  The conversion of incoming data streams into packets  in
    16              memory  free  of  detectable  errors.  This includes the
    17              detection and removal of  framing  information,  address
    18              detection, error detection and receipt acknowledgment.


    19     The Physical Interconnect layer consists  of  the  line  drivers,
    20     wires,  bus  arbitration  and  electrical  signalling  rules that
    21     control the physical transfer of data over the bus.

    22     As indicated in the diagram, the CI architecture  consists  of  a
    23     common  port  protocol, defined in DEC standard 161, coupled with
    24     unique datalink and physical channel layers.

    25     1.3  Overview Of The DSSI Bus

    26     This section presents an overview of the DSSI bus and its  design
    27     goals in comparision to the CI.

    28     The DSSI is designed to support low-end  and  mid-range  systems,
    29     including  VAX  clusters,  where  an  application  can tolerate a
    30     reduction in availability and performance in exchange for reduced
    31     cost.  The main features of DSSI are:

    32           o  Multidrop electrical topology





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     1           o  8-bit parallel data bus.

     2           o  DC coupling between nodes

     3           o  Use of low-cost, single-ended drivers and receivers.

     4           o  Restricted length ( 6  meters  maximum  )  suitable  for
     5              one-, two-, or three-box systems.

     6           o  Single electrical path.


     7     In contrast, the CI is designed to support the needs of  high-end
     8     systems where availability and performance are the primary goals.
     9     The main features of the CI are:

    10           o  "Star" electrical  topology  to  isolate  the  bus  from
    11              single-point node failures,

    12           o  Passive star coupler for reliability

    13           o  Active, redundant-element star coupler for large  arrays
    14              of intelligent subsystems

    15           o  Bit-serial signalling to simplify  star  coupler  design
    16              and facilitate inter-system isolation.

    17           o  Dual-path for redundancy

    18           o  End-to-end length  suitable  for  interconnecting  large
    19              systems in a 'computer room' environment.


    20     The  following  table  summarizes  the  characteristics  of  each
    21     interconnect:















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     1                            CI                      DSSI             
     2                            --                      ----             

     3     Format of         Bit-serial, embedded      8-bit parallel,     
     4     transmitted       clock.                    'synchronous burst' 
     5     Data:                                                           

     6     Data Bandwidth:   70Mbits/sec               4Mbytes/sec         
     7     (unformatted)                               ( ~32Mbits/sec )    

     8     Maximum Number    16 ( Passive Hub )              8             
     9     of Nodes per      224 ( Active Exchange )                       
    10     Datalink:                                                       

    11     Data Format:      Packets, 7 - 4100 bytes   Packets, 2 - 4114   
    12                       ( excluding bit synch,    bytes               
    13                       header and trailer )                          

    14     Distance:         45 meters max from        6 meters end-to-end 
    15                       center of hub, 90                             
    16                       meters node-to-node.                          

    17     Medium:           2 send-receive            Single, 50-conductor
    18                       coaxial cable pairs       cable with multiple 
    19                                                 taps.               


    20     Electrical        Transformer-coupled       DC-coupled, single- 
    21     Interface:        line drivers for high     ended line drivers. 
    22                       dc isolation.                                 

    23             Figure 1-3:  Comparison of CI and DSSI features


    24     1.4  Scope Of This Document

    25     This document is the functional specification of  the  DSSI  bus.
    26     Its purpose is to specify the interconnect to the level of detail
    27     necessary to build a DSSI node and configure a  series  of  nodes
    28     into an operational system.

    29     The following elements are specified:


    30          1.  The DSSI Data Link Protocol.





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     1          2.  The physical bus protocol including  signal  definitions
     2              and timing.

     3          3.  The   bus   electrical   requirements   including    the
     4              specification  for  line drivers and receivers and rules
     5              for signal integrity.

     6          4.  The mechanical requirements, including the definition of
     7              connectors, cables and mounting rules.

     8          5.  The electrical and mechanical rules  for  configuring  a
     9              system of DSSI nodes.


    10     1.5  References

    11     The following documents may be useful in fully understanding DSSI
    12     and  its  relationship  with Digital's Storage Architecture (DSA)
    13     and other I/O architectures.

    14          1.  Mass Storage Control Protocol (MSCP); Revision  2.1.1  (
    15              13 March 1988 )

    16          2.  Tape Mass Storage  Control  Protocol  (TMSCP);  Revision
    17              2.0.2 ( 8 November 1987 )

    18          3.  Diagnostics and Utilities Protocol (DUP);  Revision  1.0
    19              (May 15, 1984)

    20          4.  Systems Communications Architecture  (SCA);  Revision  7
    21              (August 8, 1985)

    22          5.  Computer  Interconnect  Specification  (DEC  STD   161);
    23              Revision A (November 24, 1986)

    24          6.  VAX-11  CI  Port  Architecture  (CIPORT);  Revision  5.0
    25              (August 17, 1987)

    26          7.  Storage  Systems  Port;  Revision  3.1.0  ( November  9,
    27              1989 )










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           TERMINOLOGY AND NOTATIONAL CONVENTIONS                   Page 2-1
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     1                                 CHAPTER 2

     2                  TERMINOLOGY AND NOTATIONAL CONVENTIONS



     3     Active Node

     4         During an atomic bus sequence, the node that controls the bus
     5         and  drives  bus-level  commands.   Either  the  initiator or
     6         target will assume the role of  active  node.   See  'Passive
     7         Node'.


     8     Asynchronous Mode

     9         A mode of  DSSI  data  transfer  that  requires  an  explicit
    10         send/receive handshake for each byte transferred.


    11     Atomic Bus Sequence

    12         The  sequence  of  DSSI  bus  phases  associated   with   the
    13         transmission  of one data block from an initiator to a target
    14         device.  The sequence is performed atomically with respect to
    15         other  nodes  on  the  bus  in that bus ownership and control
    16         remain with the  target-initiator  pair  until  the  sequence
    17         completes.


    18     Bus Phase

    19         The sequence of bus states comprising one step in  an  Atomic
    20         Bus  Sequence.   The  ARBITRATION phase, through which a node
    21         bids for ownership of the bus, is one such phase.


    22     Command Descriptor Block

    23         Six  bytes  of  control  information  (   plus   checksum   )
    24         transmitted  to the target during the DSSI COMMAND OUT phase.
    25         This  block  contains  parameters   used   to   control   the
    26         transmission of information during the DATA OUT phase.







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     1     Data Block

     2         The block of information ( with checksum )  transmitted  from
     3         the  initiator  to  the target during the DATA OUT phase of a
     4         DSSI bus transaction.


     5     DSSI Node


     6         The site of a DSSI datalink.   The  terms  'node'  and  'DSSI
     7         node' are used synonymously in this specification.


     8     DSSI Packet


     9         The Command Out descriptor block and Data  block  transmitted
    10         by the initiator during an atomic bus sequence.


    11     Hot-swap

    12         The act of physically connecting  or  disconnectiong  a  node
    13         from the bus while the node is powered on.


    14     Initiator


    15         A DSSI  node  that  has  arbitrated  for  the  bus  with  the
    16         intention of sending a data packet.


    17     May

    18         Denotes a lack of prohibition when used as a  directive.   It
    19         is  used  to  indicate  an  option or options architecturally
    20         permissible for an implementation.  No bias  for  or  against
    21         the  option is implied.  "May not" denotes strict prohibition
    22         when used as a directive.


    23     Node

    24         See 'DSSI node'.




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     1     Nugatory

     2         Of little or no consequence:  Trifling, Inconsequential.


     3     Passive Node


     4         During a bus phase, the DSSI node that  reacts  to  bus-level
     5         commands.   For  each  phase of an atomic bus sequence either
     6         the initiator or target will assume the role of passive node.
     7         See 'Active Node'.


     8     Physical Bus Protocol

     9         The electrical signalling rules and  timing  required  for  a
    10         DSSI  node to properly transmit control signals and data over
    11         the DSSI physical interconnect.


    12     Shall

    13         Denotes an  architectural  requirement.   It  is  used  as  a
    14         directive to express what is mandatory for an implementation.
    15         "Shall not" denotes strict prohibition.


    16     Should

    17         Denotes an emphatic recommendation when used as a  directive.
    18         It  is  used where "shall" might be too strong because of the
    19         possibility of technical,  implementation-specific  obstacles
    20         or other overriding considerations.


    21     Synchronous Mode

    22         Synonymous with "synchronous burst mode".


    23     Synchronous Burst Mode

    24         A mode of data transmission over the DSSI bus in  which  data
    25         bytes  are  transmitted  in  bursts,  without  waiting for an
    26         explicit send/receive "handshake" after each byte.  This mode
    27         requires  that  each  DSSI  implementation  have  a dedicated



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     1         hardware buffer ( FIFO ) that is tightly coupled to the bus.


     2     Target

     3         A DSSI node that has been signalled by an initiator, via  the
     4         physical bus protocol, that it is to receive a packet.


     5     Warm-swap

     6         The act of physically disconnectiong or connecting a node  to
     7         the bus while node power is off.





































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     1     2.1  Notational Conventions

     2     2.1.1  Numeric Notation

     3     All numbers are decimal unless otherwise specified.   Hexadecimal
     4     numbers are noted by a suffix of "h", for example, 1Ah.

     5     2.1.2  Time Unit Abbreviations

     6     The following time unit abbreviations are used:

     7          1.  ms - Milliseconds

     8          2.  us - Microseconds

     9          3.  ns - Nanoseconds


    10     2.1.3  Bit Field Notation

    11     A string of contiguous bits is described by the notation:

    12                             field_name< m:n >

    13     where:

    14         "field_name" is an ascii string describing  the  function  or
    15         field

    16         "m" is the bit position of the left-most (  highest  order  )
    17         bit in the field.

    18         "n" is the bit position of the right-most (  lowest  order  )
    19         bit in the field.

    20     2.1.4  Naming Conventions For Variables

    21     Throughout  this  specification,   variable   names   designating
    22     parameters and function values, are constructed in the form:

    23         <xx>_<value_mnemonic>

    24     Where:

    25         "<xx>" is a  two-character  abbreviation  for  the  layer  or
    26         function   that   establishes   the   variable's   value  and
    27         "<value_mnemonic>" is a string suggestive of the parameter or



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     1         condition represented.

     2     Variables associated with the physical bus  always  have  a  null
     3     prefix string.

     4     So, for example, the name "CC_NAK" represents a value returned by
     5     the  datalink  Channel  Control layer, whereas "NAK" represents a
     6     value returned over the DSSI bus during the STATUS IN phase.










































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           PORT ADDITIONS AND/OR CLARIFICATIONS                     Page 3-1
                                                               27 March 1990


     1                                 CHAPTER 3

     2                   PORT ADDITIONS AND/OR CLARIFICATIONS


     3     3.1  Port Additions And/or Clarifications

     4     This section clarifies or adds to the Port  section  of  DEC  STD
     5     161.   These  changes  are due to past experience with the CI, or
     6     due to different requirements of  the  underlying  DSSI  Physical
     7     Channel.

     8     3.2  Unrecognized Packets

     9     When an unrecognized packet (unrecognized port layer  opcode,  or
    10     invalid  packet  length)  is  received  by a DSSI node, it should
    11     close the virtual circuit to the corresponding node.

    12     3.3  Self Directed Commands

    13     All DSSI adapters  other  than  KFQSA  should  support  the  self
    14     directed  commands  (CI Port commands with Port Field the same as
    15     their own node number).  Two SYSAP processes within a system  may
    16     communicate with each other through self directed commands.  They
    17     should be supported with all variations of the specific  commands
    18     (such  as  R  bit  set or clear) like all other non-self directed
    19     commands.   It  is  further  recommended  that  they  should   be
    20     implemented  to  use the same code paths (to the extent possible)
    21     as non-self directed commands.  Such an approach will  provide  a
    22     loop back mechanism and help diagnosis.

    23     3.4  Loop Back Packets

    24     CI Port Architecture and DEC STD 161 support loop back packets on
    25     the CI wires.  The SNDLB command (Sec 7.8, Ref [6]) requires that
    26     the packet should be transmitted and received on the wires at the
    27     same  time.   CI data link supports such a feature.  However DSSI
    28     (more specifically  the  SII)  does  not  support  such  feature.
    29     However  DSSI  adapters  other  than KFQSA should treat the SNDLB
    30     commands similar to the self directed commands.

    31     3.5  Multibit Sequence Numbers

    32     CI port layer uses  single  bit  sequenced  numbers  in  all  the
    33     sequenced message packets (refer to section 4.1 in DEC STD 161).





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     1     Single bit sequence numbers have the problem that if a single NAK
     2     status  turns into an ACK, (i.e., the receiver sent a NAK and the
     3     sender received the status as ACK due to 8 bit errors  in  9  bit
     4     DSSI  status), two sequenced message packets will be discarded at
     5     the receiver and both nodes will be unaware of the lost  packets.
     6     To  overcome  the above problem DSSI uses 3 bit sequence numbers.
     7     All references  to  NS  and  NR  in  DEC  STD  161  and  CI  Port
     8     Architecture  should  be  treated  as 3 bit fields.  The sequence
     9     number field, NS, is located in bits <3:1> of the FLAGS byte.

    10     When a frame is received, a DSSI node should  use  the  following
    11     rule for validating sequence numbers:

    12          1.  If NS =  NR,  the  node  should  accept  the  frame  and
    13              increment NR.

    14          2.  If NS = NR-1, the node should  discard  the  frame,  and
    15              should not increment NR.

    16          3.  With any other combination of NS and NR, the node should
    17              break VC, and report a sequence number mismatch error to
    18              higher layers.


    19     3.6  CI ID Response Packet Fields

    20     Sec 7.9.3 of CI Port Architecture (Ref[6]), describes ID Response
    21     packet format.  The fields relevant to DSSI are in this section.

    22     The only sub-field of PORT_FCN_EXT that is  currently  meaningful
    23     for DSSI devices is MAX_BODY_LEN, which is the low 13 bits of the
    24     high order word of the PORT_FCN_EXT longword.   The  contents  of
    25     this  field  are  the  maximum  number  of bytes in a packet BODY
    26     supported by the sending node.  The  packet  body  comprises  the
    27     data  bytes  passed  during  the  DSSI  data phase --- the packet
    28     opcode byte, flags byte,  and  other  data  bytes,  but  not  the
    29     checksum.

    30     It should be noted that the MAX_BODY_LEN value reported by a DSSI
    31     node  must  reflect  the  size  of the buffers on the SII receive
    32     queue (target queue).

    33     Nodes that do not have internal data buffers (SHAC)  must  always
    34     report the maximum size, (4114).






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     1     Block data transfer packets  include  18  bytes  of  overhead  in
     2     addition to data --- packet opcode (1), flags (1), transaction ID
     3     (8), buffer name (4), and offset (4).  Thus transferring 4K bytes
     4     of  data  per packet requires that MAX_BODY_LEN be 4114 (4096+18)
     5     or larger.

     6     DSSI nodes should return zero  in  all  other  currently  defined
     7     sub-fields  of  PORT_FCN_EXT.  XNR, AARB, XPRE, and AST report CI
     8     data link parameters  that  are  inapplicable  to  DSSI.   A  CSZ
     9     (cluster size) value of zero means 16 nodes, which is the closest
    10     value available to the 8 nodes supported by DSSI.

    11     DSSI nodes  must  ignore  all  the  inapplicable  fields  of  the
    12     PORTFCNTEXT  field  (as  well  as other fields of the ID response
    13     packet).  They should ignore whatever values they receive in  the
    14     XNR,  AARB, XPRE, AST and MBZ (Must Be Zero) fields.  They should
    15     also ignore the CSZ (cluster size) field.

    16     DSSI nodes  should  use  the  contents  of  the  MAX_BODY_LEN  to
    17     determine   the   maximum   size   of   a  block  data  transfer.
    18     Specifically, DSSI disk and tape drives should do the following:

    19          1.  The drive has its own MAX_BODY_LEN that  corresponds  to
    20              its  native or preferred data transfer size --- that is,
    21              to the size of its data buffers.  While it  is  strongly
    22              recommended  that  this  be  4114  (4K  data  bytes  per
    23              packet), smaller values can  be  justified  so  long  as
    24              their effect on system performance (not just device cost
    25              or performance)  is  considered  and  verified  (through
    26              simulation, performance testing, etc.).

    27          2.  The drive determines the host's  MAX_BODY_LEN  from  the
    28              configuration polling process.

    29          3.  For  each  host,  the  drive  determines  an   effective
    30              MAX_BODY_LEN   equal  to  the  minimum  of  the  drive's
    31              MAX_BODY_LEN and the host's MAX_BODY_LEN.

    32          4.  DSSI drives may only initiate data byte  transfers  with
    33              base packet size of 512 bytes (P=0).

    34          5.  The drive determines the packet multiple  (M  value)  to
    35              use   for  the  block  data  transfers  that  the  drive
    36              initiates on each host as follows:


    37        if (effective MAX_BODY_LEN < 530) then begin



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     1            { host either does not implement the CI ID response ECO,   }
     2            { in which case MAX_BODY_LEN is zero, or the host returned }
     3            { a MAX_BODY_LEN value smaller than one 512 byte block.    }
     4            { In either case use M=0, or one 512 byte block per packet.}
     5            M := 0;
     6        end else begin
     7            M := (effective MAX_BODY_LEN - 18) div 512 - 1;
     8            { div means integer division with truncation towards zero. }
     9            if M < 0 then M := 0;
    10            if M > 7 then M := 7;
    11        end;

    12        The drive supplies this M value in all DATREQn packets and uses
    13        it to limit the size of all SNTDAT packets.  It should be noted
    14        that the drive determines a separate value of M for each host.

    15     DSSI host nodes should do the following:

    16          1.  All native DSSI host nodes (all host ports  that  attach
    17              to  a  DSSI  cable  or bus) should return a MAX_BODY_LEN
    18              value of 4114 in ID response packets.

    19              DSSI host nodes should also support  packets  with  body
    20              lengths up to 4114 bytes.

    21          2.  All DSSI host nodes shall support 512 byte block packets
    22              (P=0).

    23          3.  DSSI nodes are not required to support  576  byte  block
    24              packets.   Any  such node that does not support 576 byte
    25              block packets should verify that P=0 in received DATREQn
    26              packets,  and treat the packet as invalid (and close the
    27              virtual circuit) if P=1.



    28     3.7  Only Single Path In DSSI.

    29     Unlike the CI, DSSI has only a single `path'.

    30     Section 4.3 of DEC STD 161 which specifies path selections is not
    31     applicable  to  DSSI.   All  senders  in  DSSI  must set the path
    32     field(s) so that it appears that path zero (0) is being used  for
    33     all communication.  Receivers may ignore path fields.






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           THE DSSI DATALINK                                        Page 4-1
                                                               27 March 1990


     1                                 CHAPTER 4

     2                             THE DSSI DATALINK


     3     4.1  The DSSI Datalink

     4     The  datalink  layer,  the  next  to  lowest  tier  of  DSSI,  is
     5     responsible  for  the  reliable  delivery  of  single  frames  of
     6     information over the physical channel.  To meet the  requirements
     7     of the port layer the datalink must:

     8          1.  deliver sequential, error free text from one  DSSI  node
     9              to another (duplication can occur), and

    10          2.  perform error recovery by retransmission, only notifying
    11              the Port Layer of failures.


    12     Datalink functions are separated  into  two  areas,  higher-level
    13     mechanisms  for  error recovery and packet exchange with the Port
    14     layer and a low level Channel  Control  layer  that  manages  the
    15     exchange  of  packets  with  the  remote  node  over the physical
    16     interconnect.

    17     An overview of the datalink layer and a detailed  description  of
    18     these  higher  level  mechanisms is presented in this chapter.  A
    19     complete description of the Channel Control  layer  is  given  in
    20     chapter 5.

    21     4.2  Overview Of A DSSI Data Transfer

    22     The transfer  of  data  packets  from  one  node  to  another  is
    23     accomplished by the Channel Control layer through a series of bus
    24     phases defined as  the  DSSI  atomic  bus  sequence.   Since  bus
    25     ownership  and control remain with the sending and receiving node
    26     pair  until  the  transfer  completes,  the  sequence  is  atomic
    27     relative to other nodes on the bus.

    28     A simplified diagram of this sequence, omitting exception  paths,
    29     is shown below (figure 4-1).









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     1                        +--------+
     2                        |Bus Free|<-----------+
     3                        +--------+            |
     4                            |                 |
     5                            v                 |
     6                      +-----------+           |
     7                      |Arbitration|           |
     8                      +-----------+           |
     9                            |                 |
    10                            v                 |
    11                    +----------------+        |
    12                    |   Selection    |        |
    13                    +----------------+        |
    14                            |                 |
    15                  +--->     v                 |
    16                  |   +-----------+           |
    17                  |   |  Cmd Out  |           |
    18                  |   +-----------+           |
    19                  |         |                 |
    20     Information  |         v                 |
    21     Transfer     |    +----------+           |
    22     Phases       |    | Data Out |           |
    23                  |    +----------+           |
    24                  |         |                 |
    25                  |         v                 |
    26                  | +----------------+        |
    27                  | |    Status In   |--------+
    28                  | +----------------+
    29                  +--->

    30             Figure 4-1:  Simplified DSSI Atomic Bus Sequence


    31     After detecting the bus free phase, a node  wishing  to  start  a
    32     transfer  must  successfully  arbitrate for exclusive bus access.
    33     The node winning arbitration, referred to as the initiator,  then
    34     attempts  to  select  a  receiving  node.   When  a  response  to
    35     selection is detected, the initiator passes bus ownership to  the
    36     selected  node, or target, who controls the remaining information
    37     transfer phases.

    38     The transfer of a data packet requires a three-step  exchange  of
    39     information between initiator and target.

    40          1.  During the Command Out phase, the target  solicits  from
    41              the   intitiator  a  6-byte  Command  Descriptor  Block,
    42              containing parameters required by the  target's  Channel



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           Overview Of A DSSI Data Transfer                    27 March 1990


     1              Control Layer for the Data Out phase

     2          2.  During the  Data Out  phase,  the  target  receives  and
     3              buffers  a  Data  block containing the actual port layer
     4              data packet.

     5          3.  During the Status In phase, the target returns a  single
     6              byte  of  status to the initiator.  One of two values is
     7              returned:

     8               o  ACK - Indicates that the data  packet  was  received
     9                  and buffered successfully,

    10               o  NAK -  Indicates  a  receive  failure  and  requests
    11                  retransmission.



    12     All data is transmitted via an 8-bit, parity-protected data path.
    13     In  addition,  vertical  checksums  are  appended  to the Command
    14     Descriptor and Data blocks.

    15     Should an error occur, the initiator's datalink will  attempt  to
    16     recover  by resending the packet.  If this fails, the initiator's
    17     port layer will be notified of an unrecoverable error.

    18     4.3  DSSI Datalink Logical Description

    19     Figure 4-2 is schematic of datalink layer functions.  The purpose
    20     of  this  model  is  to  facilitate  the description of essential
    21     datalink functions.  It is not  meant  to  represent  or  suggest
    22     actual implementations.


















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           DSSI Datalink Logical Description                   27 March 1990


     1                                +-----------------+              
     2                                | Interface to    |              
     3                                | Port Layer      |              
     4                                +-----------------+              
     5                                  |      |      |                
     6                     +------------+      |      +------+         
     7                     |                   |             |         
     8            +----------------+    +-------------+      |         
     9            | Datalink Xmit  |    |   Receive   |      |         
    10            |     and        |    |   Packet    |      |         
    11            | Error Recovery |    |   Buffer    |      |         
    12            +----------------+    +-------------+      |         
    13                     |                   |             |         
    14                     +---+           +---+             |         
    15                         |           |                 |         
    16                      +-----------------+     +-----------------+
    17                      | Channel Control |     |Internal Event   |
    18                      | Layer           |     |Logs and Counters|
    19                      +-----------------+     +-----------------+
    20                         |           |                           
    21                 +-------------+     |                           
    22                 |   Transmit/ |     |                           
    23                 |   Receive   |     |                           
    24                 |   FIFO      |     |                           
    25                 +-------------+     |                           
    26                         |           |                           
    27                         |           |                           
    28                    <------------------------------> DSSI Bus    

    29                     Figure 4-2:  DSSI Datalink Model

    30     The Port  Interface  layer  provides  the  Port  with  access  to
    31     datalink  channel  control  services  and the ability to read and
    32     reset various datalink internal counters and event logs.

    33     For  outgoing  data,  this  layer  interacts  with  the  Datalink
    34     Transmit  and  Error  Recovery layer to forward the packet to the
    35     target and return the results of the transfer to the Port.

    36     For incoming data, the Port Interface signals the  Port  that  an
    37     incoming  packet has been received and unloads the Receive Packet
    38     buffer on request.

    39     The event  logs  and  counters  maintained  by  a  DSSI  datalink
    40     implementation  are  described  in section 5.6.  They are read by
    41     the Port Layer and returned to higher layers as described in that
    42     section.



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           DSSI Datalink Logical Description                   27 March 1990


     1     The Receive Packet Buffer represents a generic delivery site  for
     2     incoming  data from the Channel Control Layer.  The potential for
     3     congestion exists when the  arrival  rate  for  incoming  packets
     4     exceeds  the  rate  at  which such packets are consumed by higher
     5     layers.

     6     The function of the Datalink Transmit and Error Recovery Layer is
     7     the  reliable  delivery  of  outgoing  packets to the target.  It
     8     initiates error  recovery  by  retransmission  according  to  the
     9     policy  described  in  section 4.5, notifying the port layer only
    10     when an unrecoverable transmission error occurs.

    11     As viewed by higher layers, the Channel  Control  Layer  provides
    12     the following services:

    13          1.  Transmits   outbound   packets   over    the    physical
    14              interconnect  and  reports  delivery status.  Error-free
    15              delivery is not guaranteed.

    16          2.  Buffers incoming packets, returning delivery  status  to
    17              the  remote  node  and  notifying  higher layers when an
    18              error-free packet has been received.


    19     At the physical interconnect, this layer is responsible  for  the
    20     following

    21          1.  Bus arbitration,

    22          2.  Initiating and responding to target selection,

    23          3.  Receipt of incoming data,  including  the  detection  of
    24              checksum and parity errors

    25          4.  Packetization of outgoing data through the  addition  of
    26              parity and checksum information.

    27          5.  Detection of bus protocol errors and exceptions

    28          6.  Returning delivery status to the remote node.


    29     The Channel Control  layer  provides  two  data  transfer  modes:
    30     asynchronous  mode, characterized by the transfer of single bytes
    31     directly to or from the bus, and synchronous  burst  mode,  which
    32     moves  data  by  way  of  the  Transmit/Receive  FIFO.   The less
    33     efficient asynchronous mode requires an  explicit  bus  handshake



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     1     for   each   byte  transferred  and  thus  has  a  throughput  of
     2     approximately 1.5Mb/sec.  This  mode  is  used  to  transmit  the
     3     Command Descriptor block and the Status In byte.

     4     Synchronous burst mode is  used  to  efficiently  transfer  large
     5     blocks  of  data during the DATA OUT phase by pipelining requests
     6     for data.  Using this mode, a data transfer rate of  4Mb/sec  can
     7     be achieved.

     8     4.4  Channel Control Services

     9     The Channel Control layer  provides  the  following  services  to
    10     higher layers:

    11           o  Transmit a data  packet  and  return  status  to  higher
    12              layers,

    13           o  Receive and buffer a data packet.


    14     After transmitting a  packet,  the  initiator's  Channel  Control
    15     Layer  shall  return one of the following status values to higher
    16     datalink layers:

    17           o  CC_ACK - The packet  was  successfully  transmitted.   A
    18              value  of  ACK  was  received from the target during the
    19              STATUS IN phase.

    20           o  CC_NAK - The Channel Control layer has detected a 'short
    21              term'     error,     probably     correctable    through
    22              retransmission.   Such  errors   usually   result   from
    23              congestion  in  the  target  node due to lack of receive
    24              buffers.

    25           o  CC_NORSP - The Channel Control Layer has  detected  what
    26              is   probably  a  persistent  error.   Such  errors  are
    27              frequently  caused  by  polling  traffic  addressed   to
    28              non-existent nodes.


    29     Implementations may differ in the ability to discriminate between
    30     various  error  conditions.  An implementation may, as a minimum,
    31     return CC_NAK whenever a transmit  request  terminates  with  NAK
    32     status  from  the  target, reporting all other errors with status
    33     CC_NORSP.





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           Channel Control Services                            27 March 1990


     1     When receiving a packet, the target's Channel Control Layer shall
     2     only notify higher layers, and return a STATUS IN value of ACK to
     3     the initiator, when the packet is received and  buffered  without
     4     error.

     5     4.5  Data Transmit And Error Recovery Layer

     6     This layer performs only one function:  The reliable transmission
     7     of  a  single data packet.  Any failure status returned to higher
     8     layers indicates a non-recoverable error.

     9     In DSSI, the procedure for error recovery is to retry the failing
    10     transmission.   The  goals  of  an  efficient retry procedure are
    11     recovery from errors in the  shortest  possible  time  using  the
    12     fewest  retransmissions.   For  that  reason,  DSSI  transmission
    13     failures are  divided  into  two  types:   short-term,  transient
    14     failures  -  likely  to  last  for  only a few milliseconds - and
    15     persistent, long-term errors.  For transient failures, caused  by
    16     bus  errors  or  short-term  receiver  congestion,  the initiator
    17     recovers by generating a burst of retransmissions within a  short
    18     time.   For  persistent  failures,  usually  caused  by polling a
    19     non-existent node, such retries are widely spaced and extend over
    20     a much longer time.

    21     To reduce or prevent bus congestion caused by  recovery  traffic,
    22     DSSI  nodes  use  a  random  coin-toss  to control retries during
    23     long-term recovery.

    24     The retry procedure consists of the following steps:

    25          1.  When a transmission fails, the recovery  procedure  uses
    26              the  transmit  status  returned  by  the Channel Control
    27              layer to infer whether the condition  is  of  short-  or
    28              long-term duration.

    29          2.  If a  transient  problem  is  indicated,  the  procedure
    30              performs  up  to 8 retries within approximately 2.0ms as
    31              described in section 4.5.1.

    32          3.  If a  persistent  error  occurs  or  immediate  recovery
    33              fails,  a  series of 'delayed' retry events is scheduled
    34              at 10ms intervals.  At each interval,  the  decision  to
    35              retransmit is made by 'coin-toss'.







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     1     In the procedure described below, certain steps are contingent on
     2     the  existence of the target node.  For DSSI implementations, the
     3     probable existence of a node is determined at  a  protocol  layer
     4     above  the  Datalink.   To  avoid knowlege of packet contents and
     5     higher layer protocols, it  is  assumed  that  the  higher  layer
     6     passes   an  appropriate  'existence'  flag  ( see  the  PL_EXIST
     7     parameter in section 4.6 ).  with each outgoing data packet.  For
     8     the  CI  port  protocol,  this  flag  shall  be  set - unless the
     9     following conditions are true:

    10          1.  The virtual circuit to the addressed  port  is  'closed'
    11              and

    12          2.  The CI port data packet is 'IDREQ'


    13     4.5.1  Error Recovery Procedure


    14          1.  After a failed transmission attempt with CC_NAK  status,
    15              the  sender shall perform immediate retries as described
    16              below.  Otherwise the delayed retry procedure  shall  be
    17              executed starting at step 5.

    18          2.  Immediate retries shall consist of up to 8 evenly spaced
    19              retry attempts over an interval of 2.0ms - the immediate
    20              retry duration.  This represents an average of  1  retry
    21              every 250us.

    22          3.  The initiator shall  guarantee  that  immediate  retries
    23              conform to the following constraints:

    24              a.  The first retransmission  shall  be  delayed  by  at
    25                  least 250us from the initial attempt.

    26              b.  The immediate retry duration shall be at least 2.0ms
    27                  for  90%  of  all  immediate  retries that perform 8
    28                  attempts.  The sender should attempt to achieve this
    29                  minimum  duration  for  all retry sequences.  If the
    30                  immediate retry limit is ever changed,  the  minimum
    31                  immediate  retry  duration shall scale linearly with
    32                  the retry limit.

    33              c.  The sender may  interleave  immediate  retries  with
    34                  transmissions to other nodes.  A node having several
    35                  immediate  retries  in  progress  shall  limit   the
    36                  aggregate  rate  of retries to an average of no more



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     1                  than 1 attempt every 250us.


     2          4.  Immediate retries shall  continue  until  the  immediate
     3              retry  limit  is  reached  or a status other than NAK is
     4              received after a retransmission.  If  immediate  retries
     5              fail, the sender shall perform delayed retries.


     6          5.  Delayed retry events are scheduled  at  10ms  intervals.
     7              When  the  interval  elapses,  the sender shall randomly
     8              determine, by means of a 'coin-toss', whether or  not  a
     9              retransmission is required.  The sender shall retransmit
    10              the failed packet according to the coin-toss  result  or
    11              if  10  delayed retry events in a row have occurred with
    12              no retransmission attempt.

    13              The random coin-toss algorithm shall generate a sequence
    14              of  'heads'  and  'tails' that is unique to each node on
    15              the bus.  See section 4.5.2 for an example  of  such  an
    16              algorithm.

    17          6.  If the 'existence' flag is asserted, as described above,
    18              delayed   retries  shall  terminate  when  a  CC_ACK  is
    19              received from the Channel Control  later  or  after  256
    20              delayed retransmissions have occurred.

    21          7.  When the 'existence' flag is deasserted  only  a  single
    22              delayed retransmission shall be performed.


    23                                   NOTE

    24             While delayed retries are in progress, the sender
    25             shall  interleave such retries with transmissions
    26             to other nodes.


    27     4.5.2  Example Of Random Number Generator

    28     The following pseudo-code is an example of a coin tossing routine
    29     that  generates  a  random  number using a seed that is unique to
    30     each node on the bus.  The value returned is TAILS if the  result
    31     is less than zero and HEADS otherwise.






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     1     The procedure for random number generation is  derived  from  VMS
     2     library routine MTH$RANDOM.

     3     The initial seed is a 32-bit integer, derived  by  concantenating
     4     the  first  three  characters  of the SCS system I/D and the node
     5     number as shown in figure 4-3:

     6                      31    24|23  16|15   8|7     0
     7                      +-------+------+------+------+
     8                      | Node  | Char | Char | Char |
     9                      | Number|  2   |  1   |  0   |
    10                      +-------+------+------+------+


    11                Figure 4-3:  Format of Unique Initial Seed


    12     procedure coin_toss()

    13     {                                                            }
    14     { All variables are 32-bit integers.
    15     {                                                            }
    16     { Multiply operations generate 64-bits. The low order        }
    17     { 32 bits are assigned to the specified variable. The        }
    18     { high-order portion is discarded.                           }
    19     {                                                            }
    20     BEGIN

    21     { Variables current_seed and cold_start are assigned to      }
    22     { static storage to preserve their values across calls.      }

    23     o allocate current_seed in static storage.
    24     o allocate cold_start in static storage with an initial value
    25       of 0

    26     if ( cold_start is 0 ) then
    27         BEGIN
    28         o cold_start := 1
    29         o current_seed := initial_seed
    30         END

    31     o current_seed := ( current_seed * 69069 ) + 1

    32     if ( current_seed is less that 0 ) then

    33        return ( TAILS )




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     1     else

     2        return ( HEADS )

     3     END

     4     4.6  Interface To The CI Port Layer

     5     The interface to the CI Port Layer is the highest Datalink layer.
     6     As  noted  earlier,  this  layer  is  responsible  for delivering
     7     incoming data blocks to the CI Port  Layer,  forwarding  outgoing
     8     packets to the Data Transmit layer and returning transmit status.

     9     Parameters passed to or from the Port layer with each Port  layer
    10     packet are:

    11          1.  PL_EXIST -- existence flag.  For outgoing  packets,  set
    12              to a non-zero value by the Port layer if the target node
    13              is believed to exist.  The rules for setting or clearing
    14              this flag are given in section 4.5.

    15          2.  DL_DST -- for outgoing packets, the DSSI I/D of the node
    16              to  receive  the  packet; for incoming packets, the DSSI
    17              I/D of this node.

    18          3.  DL_SRC -- for outgoing packets, the  DSSI  I/D  of  this
    19              node;  for  incoming  packets,  the DSSI I/D of the node
    20              that sent the packet.

    21          4.  DL_LEN -- The length of the packet in  bytes  ( excludes
    22              the checksum appended by the Channel Control layer ).

    23          5.  DL_STATUS --  packet  status  passed  with  each  packet
    24              received or transmitted.


    25     Possible received packet status values are:

    26           -  DL_OK -- Packet successfully received in its entirety.

    27           -  DL_OVERSIZE -- Packet was successfully received into the
    28              Datalink  Receve  buffer but was too large to deliver in
    29              its entirety to the Port layer buffer.   The  packet  is
    30              truncated to fit into the Port layer buffer.






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           THE DSSI DATALINK                                       Page 4-12
           Interface To The CI Port Layer                      27 March 1990


     1     Possible transmit packet status values  ( after  attempted  error
     2     recovery ) are:

     3           -  DL_ACK -- Successful transmission.  A value of  ACK  was
     4              received from the target during the STATUS IN phase.

     5           -  DL_NAK  --  The  target  exists  but   was   unable   to
     6              succesfully  receive the packet, most likely due to lack
     7              of a Receive Packet buffer.

     8           -  DL_NORSP -- transmission was  attempted  to  a  possibly
     9              non-existent target node.






































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                                                               27 March 1990


     1                                 CHAPTER 5

     2                      THE DSSI PHYSICAL BUS PROTOCOL


     3     5.1  The DSSI Physical Bus Protocol

     4     The following figure ( figure 5-1 ) shows  the  datalink  Channel
     5     Control  layer,  with  its  interfaces to the DSSI bus and higher
     6     datalink layers.

                                                           
     7                        Transmit   Transmit  Received
     8                         Data      Status    Data    
     9                           |          ^        ^     
    10                           v          |        |     
    11                         +------------------------+  
    12                         |   Channel Control      |  
    13                         |   Layer                |  
    14                         +------------------------+  
    15                                    ^                
    16                                    | Physical Bus   
    17                                    v Protocol       
    18                            <------------------>     
    19                                 DSSI Bus            



    20               Figure 5-1:  Datalink Channel Control Layer



    21     As indicated in the  diagram,  the  DSSI  physical  bus  protocol
    22     defines  the  interface between the Channel Control Layer and the
    23     DSSI bus.   This  signalling  protocol,  used  to  exchange  data
    24     packets  between  an  initiator and target over the interconnect,
    25     supports the following Channel Control services:

    26          1.  Transmit a data packet, returning  status  to  a  higher
    27              layer,

    28          2.  Receive a packet, notifying higher layers only when  the
    29              packet is delivered without error.







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     1     The following  sections  specify  the  logical  behavior  of  the
     2     interconnect  when  servicing  a transmit request, including data
     3     formats, bus signals, bus phases,  timing,  error  detection  and
     4     conditions reported to higher datalink layers.

     5     The electrical and physical bus  requirements  are  specified  in
     6     chapter 6.

     7     5.2  Logical Description Of The DSSI

     8     The DSSI is a daisy-chained bus, connecting up to 8  nodes,  that
     9     uses  low-cost,  open-collector  drivers  and  receivers for data
    10     transfer and  control.   The  physical  bus  contains  16  active
    11     signals, 9 of which comprise an 8-bit, parity protected data bus.

    12     The bus protocol is designed for the transfer of data in  packets
    13     between  an  initiator and target node.  Other nodes are excluded
    14     from the bus while such a transfer is in progress.  All nodes  on
    15     the bus are capable of acting as either an initiator or target.

    16     5.3  Signal Definitions

    17     Signals on the bus are defined as  TRUE  ( asserted )  when  low.
    18     With  open-collector  logic, signals are driven low by the driver
    19     and pulled high by the terminator.

    20     The DSSI bus contains the following signals:

    21           o  DATA<7:0>, PARITY - Signals that comprise an 8-bit  wide
    22              data  path plus odd parity.  Collectively, these signals
    23              are referred to as the DATA BUS.

    24           o  BSY ( Busy) - When asserted, indicates that the DSSI bus
    25              is currently in use.

    26           o  SEL  ( Select )  -  When  asserted,  indicates  that  an
    27              initiator is attempting to address ( Select ) a target.

    28           o  C/D ( Command/Data ) - When asserted, indicates that the
    29              data lines are being used to pass control information to
    30              or from the target; when deasserted, indicates that data
    31              is being transferred.

    32           o  I/O ( Input/Output ) -  When  asserted,  indicates  that
    33              data  movement  is toward the initiator; when deasserted
    34              indicates that data movement is toward the target.




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     1           o  REQ ( Request ) - Asserted by the target to request  the
     2              transfer  of one byte of data in the direction specified
     3              by the I/O signal.

     4           o  ACK  ( Acknowlege )  -  Asserted  by  the  initiator  in
     5              response to a REQ.  When I/O is asserted, indicates that
     6              the initiator has read data placed on  the  bus  by  the
     7              target.   When  I/O  is  deasserted,  indicates that the
     8              initiator has placed data on the bus to be read  by  the
     9              target.

    10           o  RST ( Reset ) - When asserted, indicates  that  a  reset
    11              condition exists.


    12     The 8-bit data path is also used to convey DSSI I/Ds  during  the
    13     arbitration  and  selection  phases.   In  this  case,  each  bit
    14     corresponds to the DSSI I/D of a node, where DATA<0>  corresponds
    15     to I/D 0, DATA<1> to I/D 1, and so forth.

    16     [1]

    17     5.4  DSSI Bus Timing [1]

    18     Unless otherwise indicated, the delay-time measurements for  each
    19     DSSI  device  shown  in table 5-1 shall be calculated from signal
    20     conditions  existing  at  that  DSSI  device's   own   DSSI   bus
    21     connection.   Thus,  these  measurements  ( except for cable skew
    22     delay ) can be made without considering delays in the cable.  The
    23     timing  characteristics  of  each  signal  are  described  in the
    24     following paragraphs.











    25     ---------------

    26      [1]  The bus signals, timing and the  low  level  bus  protocols
    27           ( bus  phases )  are  derived  from  Small  Computer System
    28           Interface (SCSI, ANSI Standard, X3T9.2/82.2 - Rev17B)



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     1        +---------------------------------------------------------+
     2        | Arbitration Delay                      2.4 microseconds |
     3        | Assertion Period                        90 nanoseconds  |
     4        | Bus Clear Delay                        800 nanoseconds  |
     5        | Bus Free Delay                         800 nanoseconds  |
     6        | Bus Set Delay                          1.8 microseconds |
     7        | Bus Settle Delay                       400 nanoseconds  |
     8        | Cable Skew Delay                        10 nanoseconds  |
     9        | Data Release Delay                     400 nanoseconds  |
    10        | Deskew Delay                            45 nanoseconds  |
    11        | Hold Time                               45 nanoseconds  |
    12        | Negation Period                         90 nanoseconds  |
    13        | Reset Hold Time                         25 microseconds |
    14        +---------------------------------------------------------+

    15                    Table 5-1:  DSSI Bus Timing Values

    16     5.4.1  Arbitration Delay [ 2.4us ]

    17     The minimum time a DSSI device shall wait from asserting BSY  for
    18     arbitration  until  the  DATA  BUS  can  be  examined  to  see if
    19     arbitration has been won.  There is no maximum time.

    20     5.4.2  Assertion Period [ 90ns ]

    21     The minimum time that a  target  shall  assert  REQ  while  using
    22     synchronous  data  transfers.   Also,  the  minimum  time that an
    23     initiator  shall  assert  ACK  while   using   synchronous   data
    24     transfers.

    25     5.4.3  Bus Clear Delay [ 800ns ]

    26     The maximum time for a  DSSI  device  to  stop  driving  all  bus
    27     signals after:

    28          1.  The BUS FREE phase is detected ( BSY and SEL both  false
    29              for a bus settle delay [ 400ns ] ),

    30          2.  SEL is received from  another  DSSI  device  during  the
    31              arbitration phase,

    32          3.  The transition of RST to true.








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     1     5.4.4  Bus Free Delay [ 800ns ]

     2     The minimum time that a DSSI device shall wait from its detection
     3     of  the  BUS FREE phase ( BSY and SEL both false for a bus settle
     4     delay ), until its assertion of BSY when going to the ARBITRATION
     5     phase.

     6     5.4.5  Bus Set Delay [ 1.8us ]

     7     The maximum time for a DSSI device to assert BSY and its DSSI I/D
     8     bit  on  the  data line after it detects BUS FREE phase ( BSY and
     9     SEL both false for a  bus  settle  delay )  for  the  purpose  of
    10     entering the ARBITRATION phase.

    11     5.4.6  Bus Settle Delay [ 400ns ]

    12     The time to wait for the bus to  settle  after  changing  certain
    13     control signals as called out in the protocol definitions.

    14     5.4.7  Cable Skew Delay [ 10ns ]

    15     The maximum difference in propagation time  allowed  between  any
    16     two DSSI bus signals when measured between any two DSSI devices.

    17     5.4.8  Data Release Delay [ 400ns ]

    18     The maximum time for an initiator to release the Data bus signals
    19     following the transition of the I/O signal from false to true.

    20     5.4.9  Deskew Delay [ 45ns ]

    21     The minimum time required for the deskew of certain signals.

    22     5.4.10  Hold Time [ 45ns ]

    23     The minimum time added between the assertion of REQ and  ACK  and
    24     the  changing  of  the  data  lines  to  provide hold time in the
    25     initiator or target, respectively while  using  synchronous  data
    26     transfers.

    27     5.4.11  Negation Period [ 90ns ]

    28     The minimum time that a  target  shall  negate  REQ  while  using
    29     synchronous  data  transfers.   Also,  the  minimum  time that an
    30     initiator  shall  negate  ACK  while   using   synchronous   data
    31     transfers.




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     1     5.4.12  Reset Hold Time [ 25us ]

     2     The minimum time for which RST is asserted.  There is no  maximum
     3     time.

     4     5.4.13  Transfer Period [  180ns ]

     5     The Transfer Period specifies the minimum  time  allowed  between
     6     the  leading edges of successive REQ pulses and of successive ACK
     7     pulses while using synchronous data transfers.

     8     5.5  Bus Protocol

     9     The following sections specify  the  physical  bus  protocol  and
    10     exception  handling  associated  with  packet transmission.  Each
    11     section describes:

    12          1.  The associated bus activity,

    13          2.  The required initiator and target behavior,

    14          3.  The status returned to higher  datalink  layers  in  the
    15              initiator.


    16     As discussed in section 4.4, that status shall reflect one of the
    17     following conditions:

    18           o  CC_ACK -  The  initiator's  Channel  Control  layer  has
    19              successfully transmitted the packet to the target.

    20           o  CC_NAK - The Channel Control Layer has detected a  short
    21              term error.

    22           o  CC_NORSP - The Channel  Control  Layer  has  detected  a
    23              persistent error.


    24     The conditions under which each  value  should  be  returned  are
    25     summarized in table 5-2 below.










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     1     Status           Condition                    Section/Page
     2     ------           ---------                    ------------
     3     CC_ACK           Succesful packet trans-      Section 5.5.8.4,
     4                      mission.                     page 5-37.


     5     CC_NORSP         Bus Reset detected           Section 5.5.5.5,
     6                      after winning arbi-          page 5-17
     7                      tration but before
     8                      selection phase.

     9                      No response to selection     Section 5.5.6.1,
    10                                                   page 5-21

    11                      Initiator timeout ( if       Section 5.5.7.4,
    12                      node does not support        page 5-27.
    13                      selection timeout ).


    14     CC_NAK           NAK Received during STATUS   Section 5.5.6.1,
    15                      IN phase or parity error     page 5-21.
    16                      detected during STATUS IN.

    17                      Premature BUS FREE Phase     Section 5.5.7.4,
    18                      detected during any infor-   page 5-27.
    19                      mation transfer phase.

    20                      Initiator timeout detected.  Section 5.5.7.4,
    21                                                   page 5-27.

    22                      Invalid information trans-   Section 5.5.7.4,
    23                      fer phase.                   page 5-27.

    24                      "Third party" bus reset de-  Section 5.5.7.4,
    25                      tected.                      page 5-27.

    26                      Phase other than BUS FREE    Section 5.5.8.4,
    27                      following the STATUS IN      page 5-37.
    28                      phase.

    29        Table 5-2:  Summary of Channel Control Layer Status Values









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     1     5.5.1  General Requirements

     2     5.5.1.1  Implicit Signal State

     3     Unless otherwise noted in  the  following  descriptions,  signals
     4     that are not mentioned shall not be asserted.

     5     5.5.1.2  Definition Of Initiator And Target Nodes

     6     The  following  sections  define  requirements  that   apply   to
     7     initiator  or  target  nodes.  A node becomes an initiator if and
     8     only if it decides it has won arbitration ( see step  4  on  page
     9     5-15 ).   A  node shall continue as an initiator until it detects
    10     the BUS FREE phase ( see section 5.5.3 )

    11     A node becomes a target if and only if it decides to  assert  BSY
    12     in  response  to  SEL  during  the  SELECTION phase ( see section
    13     5.5.6 ).  A node shall continue as a target until it releases all
    14     signals to enter the BUS FREE phase.

    15     5.5.1.3  Use Of And Reaction To Bus Reset ( RST )

    16     The bus reset signal ( RST ) allows a node not in control of  the
    17     bus  to  force  the  BUS FREE  phase  in response to an exception
    18     condition.  Any DSSI device  can  create  a  reset  condition  by
    19     asserting RST for a minimum of 25us.

    20     The processing of Bus Reset shall take precedence over all  other
    21     bus  phases.   All  DSSI  devices  shall release all DSSI signals
    22     within 800ns of the transition of RST to true.  Nodes  shall  not
    23     drive any other bus signals while RST is true.

    24     A Bus Reset shall only be asserted:

    25           o  When explicitly required in the following sections,

    26           o  Whenever a node is powered up as  described  in  section
    27              6.3.9.3.3.

    28           o  Whenever  an  initiator  detects   an   internal   error
    29              condition ( for example, a parity error in the local RAM
    30              while transferring data on the  bus,  or  a  bus  parity
    31              error during the STATUS IN phase).







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     1                                   NOTES


     2             1.  The assertion of a DSSI Bus Reset  shall  not
     3                 cause any node on the bus to suffer a loss of
     4                 context (i.e., the receipt of reset by a node
     5                 on  the  bus  is  not  sufficient  reason for
     6                 breaking any virtual circuit).

     7             2.  The detection of Reset  by  an  initiator  or
     8                 target  shall  cause the transfer in progress
     9                 to be aborted.  The initiator  shall  respond
    10                 by  invoking  the  error  recovery  procedure
    11                 defined in section  4.5.   The  target  shall
    12                 consider  a bus reset as equivalent to a data
    13                 error and shall not forward the  data  packet
    14                 to  higher  layers.   In  particular, a reset
    15                 that occurs after the  target  has  otherwise
    16                 successfully   completed   the  DATA OUT  and
    17                 STATUS IN phases should prevent such  packets
    18                 from being forwarded.



    19     5.5.1.4  Watchdog Timers

    20     The datalink  shall  maintain  watchdog  timers,  which  cause  a
    21     transfer  to  be  aborted  in  the  event  of  a bus lockup.  The
    22     following conditions shall be detected:

    23          1.  Selection Timeout [ 20us to 30us ] - failure of  a  node
    24              to  respond  to  selection  within  a predetermined time
    25              limit.  The initiator shall enforce Selection Timeout as
    26              described in section 5.5.6.

    27          2.  Initiator Timeout [ 2800us ] - The maximum time  allowed
    28              between  consecutive  occurrences of the BUS FREE phase.
    29              This interval shall be enforced by an initiator  or  any
    30              node monitoring bus state with the intention of entering
    31              into  arbitration  for  the  bus.   A   node   detecting
    32              Initiator Timeout shall generate a Bus Reset.

    33          3.  Target Timeout [ 2400us ] - The maximum time between the
    34              detection  of  selection  and  observation  of  the next
    35              BUS FREE condition by the target Node.  The target shall
    36              respond  by  releasing  all  signals  and  entering  the
    37              BUS FREE phase.



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     1     5.5.2  DSSI Bus Phases And Signal Sources

     2     As discussed in chapter 4, a data transfer requires the following
     3     sequence of bus phases:

     4           o  BUS FREE - The bus is not in use,  nodes  may  arbitrate
     5              for bus access.

     6           o  ARBITRATION  -  A  prospective  initiator  competes  for
     7              exclusive bus ownership.

     8           o  SELECTION - The initiator selects the target node.

     9           o  COMMAND OUT   -   The   initiator   sends    a    6-byte
    10              Command Descriptor block to the target.

    11           o  DATA OUT - The initiator transmits the data block.

    12           o  STATUS IN -  The  target  returns  the  results  of  the
    13              transfer to the initiator.


    14     The table below ( table 5-3 ) summarizes the signals  present  on
    15     the bus during each phase and the nodes driving each signal.


























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     1     Bus Phase    BSY   SEL   <C/D,I/O,REQ>   ACK   <DB<0-7>, PARITY>
     2     ---------    ---   ---   -------------   ---   -----------------

     3     BUS FREE     None  None       None       None   None     None   
     4     ARBITRATION  All   Winner     None       None   DSSI ID  N/A    
     5     SELECTION    I&T   Init       None       None   Init     Init   
     6     COMMAND      Targ  None       Targ       Init   Init     Init   
     7     DATA OUT     Targ  None       Targ       Init   Init     Init   
     8     STATUS IN    Targ  None       Targ       Init   Targ     Targ   


     9     All:        The signal shall be driven by all DSSI  devices  that
    10                 are actively arbitrating.

    11     DSSI I/D:   A unique data bit shall be driven by each DSSI device
    12                 that  is  actively  arbitrating; the other seven data
    13                 bits shall be released ( ie:   not  driven )  by  the
    14                 DSSI  device.   The  parity  bit  may  be released or
    15                 driven to the true state.

    16     I&T:        The signal shall be driven by the initiator,  target,
    17                 or  both,  as  specified in the SELECTION phase ( see
    18                 section 5.5.6 ).


    19     Init        If driven, this signal shall be driven  only  by  the
    20                 active initiator

    21     None:       This signal shall be released; that is, not be driven
    22                 by  any  DSSI  device.  The bias circuitry of the bus
    23                 terminators pulls the signal to the false state.

    24     Win:        The signal shall be driven by  the  one  DSSI  device
    25                 that wins arbitration.


    26     Targ:       If the signal is driven, it shall be driven  only  by
    27                 the active target.

    28                     Table 5-3:  DSSI Signal Sources


    29     The following sections describe the signal timing and  sequencing
    30     requirements associated with each phase.






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     1     5.5.3  BUS FREE Phase

     2     This phase is present when SEL and BSY have  been  simultaneously
     3     and  continuously false for a Bus Settle delay [ 400ns ].  A node
     4     may not begin  arbitration  for  the  bus  until  this  phase  is
     5     detected.

     6     DSSI devices shall be prepared to detect BUS FREE at any time and
     7     shall  respond  by  releasing  all  DSSI  bus  signals  within  a
     8     Bus Clear delay [ 800ns ].

     9     A BUS FREE phase, caused by the target's release  of  BSY,  might
    10     occur because of:

    11          1.  Completion of the STATUS IN phase ( target  successfully
    12              delivers the status byte to the initiator ).

    13          2.  After a Bus Reset is detected ( see section 5.5.1.3 ).

    14          3.  After certain target-detected errors.


    15     An initiator shall be prepared to detect the drop of BSY  by  the
    16     target  at  any  other  time.   When  this  occurs, the target is
    17     indicating an error condition to the  initiator.   The  initiator
    18     shall  treat  this  as  an unsuccessful packet transmission to be
    19     handled by its error recovery mechanism ( see section 4.5  ).

    20     The BUS FREE phase may also  be  entered  after  an  unsuccessful
    21     selection  ( see  section  5.5.6 ).   In  that  case,  it  is the
    22     initiator's drop of SEL, after selection  timeout  elapses,  that
    23     establishes the BUS FREE phase.

    24     5.5.4  ARBITRATION Phase

    25     This phase allows a device to compete for control of the DSSI bus
    26     for the purpose of selecting another device.

    27     The mechanism uses the round-robin or 'fair' arbitration  scheme,
    28     described  below,  to  distribute  bus access equally to all DSSI
    29     nodes.

    30     5.5.5  Fair ( Round-Robin ) Arbitration

    31     Round-robin arbitration  insures  that  all  devices  have  equal
    32     access to the bus.  Except for the products listed in appendix H,
    33     which use the fixed  priority  arbitration  scheme  described  in



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     1     section  H.2.1,  all  DSSI  nodes shall implement the round robin
     2     arbitration algorithm described in this  section.   As  described
     3     below,  both  types  of  bus  arbitration  can be intermixed on a
     4     single bus.

     5     The basic concept of Round Robin arbitration is that  DSSI  nodes
     6     can  be  enabled or disabled.  An enabled node may participate in
     7     arbitration if it has a message to send, a disabled node may not.
     8     The  normal  sequence  of  events  starts with all nodes enabled.
     9     Each node in turn wins arbitration, sends a message, and disables
    10     itself.  Eventually all nodes are disabled, resulting in the DSSI
    11     bus becoming idle.  All the nodes recognize that the bus is  idle
    12     (BSY  and  SEL  both  false for a long enough time) and re-enable
    13     themselves.

    14     When fixed priority and round  robin  implementations  share  the
    15     same  bus,  nodes  that use priority arbitration behave as though
    16     they are permanently enabled.  So long as  such  nodes  use  less
    17     than  the  total bus bandwidth, the bus will periodically go idle
    18     and the fair arbitration nodes will re-enable  themselves.   This
    19     criteria  for  correct  operation  ---  that  nodes  using  fixed
    20     priority arbitration use less than the DSSI bus bandwidth ---  is
    21     exactly  the  same  as the requirement for correct operation of a
    22     DSSI bus that  only  contains  nodes  supporting  fixed  priority
    23     arbitration.

    24     5.5.5.1  Specification Of DSSI Arbitration Algorithm

    25     This section is the exact specification of the DSSI  round  robin
    26     arbitration algorithnm.

    27     The following timing parameters are defined:


    28     DSSI Arbitration Skew Delay [600ns]


    29         The maximum allowable skew for a DSSI node to assert BSY  and
    30         its DSSI ID during arbitration.


    31     DSSI Idle Delay [2200ns]


    32         The minimum time a DSSI node must wait before concluding that
    33         no enabled nodes are arbitrating for the bus.




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     1     The  rationale  for  using  the  above  two  parameters  and  the
     2     derivation of their values are described in Appendix A.

     3     Signal definitions and all other timing parameters are  the  same
     4     as  in sections 5.3, Signal Definitions, and 5.4 DSSI Bus Timing.
     5     All timing measurements  shall  be  calculated  from  the  signal
     6     conditions existing at each DSSI node's own DSSI connection (that
     7     is, the DSSI bus side of drivers and receivers).

     8     Each DSSI node implements an internal flag indicating whether  it
     9     is enabled or disabled.  This arbitration algorithm specification
    10     is divided into three sections:


    11          1.  Rules for enabled nodes.  Enabled  nodes  that  wish  to
    12              send a message participate in arbitration.  Upon winning
    13              arbitration, the node disables itself  and  attempts  to
    14              send the message.

    15          2.  Rules  for  disabled  nodes.   Disabled  nodes  do   not
    16              participate  in  arbitration.   However,  disabled nodes
    17              monitor  the  DSSI  bus,  and  enable  themselves   upon
    18              detecting that the bus is idle.

    19          3.  Rules for manipulating the enabled/disabled flag.



    20     5.5.5.2  Rules For Enabled Nodes

    21     Enabled nodes that do not have a message to send should  normally
    22     remain  enabled.   However,  node  resets or other conditions may
    23     cause a node to spontaneously become disabled.

    24     An enabled DSSI node that has a message to send  shall  arbitrate
    25     for the DSSI bus as follows:

    26          1.  The enabled DSSI node with a message to send shall first
    27              wait  for  the  BUS  FREE  phase to occur.  The BUS FREE
    28              phase  is  detected  whenever  both  BSY  and  SEL   are
    29              simultaneously and continuously false for a minimum of a
    30              bus settle delay [400ns]

    31          2.  The DSSI node shall wait a minimum of a bus  free  delay
    32              [800ns]  after  detection  of  the  BUS FREE phase (i.e.
    33              after BSY and SEL are both false for a bus settle  delay
    34              [400ns]) before driving any signal.



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     1          3.  Following the bus free delay [800ns] in step 2, the DSSI
     2              node shall assert both BSY and its own DSSI ID within an
     3              Arbitration Skew Delay  [600ns].   The  node  shall  not
     4              arbitrate  (i.e.   assert  BSY  and its DSSI ID) if more
     5              than a bus free delay [800ns] plus  a  DSSI  Arbitration
     6              Skew  Delay [600ns] have passed since the BUS FREE phase
     7              was last observed.  However, it  should  be  noted  that
     8              whenever   BSY   and   SEL   are   simultaneously,   and
     9              continuously false for  more  than  400ns,  a  node  may
    10              detect the BUS FREE phase at any time during that period
    11              and thus start its reference point (i.e., start at  Step
    12              1).

    13          4.  After waiting at least  an  arbitration  delay  [2200ns]
    14              (measured from its assertion of BSY) the DSSI node shall
    15              examine the DATA BUS.  If a higher priority DSSI ID  bit
    16              is  true  on the DATA BUS (DATA<7> is the highest), then
    17              the DSSI node has lost the arbitration and the DSSI node
    18              shall  release  its signals and return to step 1.  If no
    19              higher priority DSSI ID bit is true  on  the  DATA  BUS,
    20              then  the DSSI node has won the arbitration and it shall
    21              assert SEL.  Any other DSSI node that  is  participating
    22              in  the  ARBITRATION  phase has lost the arbitration and
    23              shall release BSY and its DSSI ID bit within a bus clear
    24              delay  [800ns] after SEL becomes true.  A DSSI node that
    25              loses arbitration may return to step 1.

    26          5.  The DSSI node that wins arbitration shall wait at  least
    27              a  bus  clear  delay  [800ns]  plus  a  bus settle delay
    28              [400ns] after asserting SEL before changing any signals.

    29          6.  The DSSI node that wins arbitration shall disable itself
    30              prior  to  releasing both BSY and SEL.  It shall disable
    31              itself regardless  of  the  outcome  of  the  subsequent
    32              SELECTION phase or message transmission attempt.


    33     5.5.5.3  Rules For Disabled Nodes


    34          1.  Disabled DSSI nodes that have a message  to  send  shall
    35              monitor  the DSSI bus for an idle condition as described
    36              below.  Disabled DSSI nodes that do not have  a  message
    37              to  send may or may not monitor the DSSI bus for an idle
    38              condition.  DSSI nodes that always monitor the DSSI  bus
    39              for  an idle condition will exhibit improved performance
    40              over DSSI nodes that  do  not.   A  DSSI  node  that  is



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     1              disabled  shall  not become enabled for any reason other
     2              than detection of a DSSI bus idle condition as described
     3              below.

     4          2.  DSSI nodes monitoring the bus shall detect DSSI bus idle
     5              condition  whenever  BSY  and SEL are simultaneously and
     6              continuously false for a  minimum  of  DSSI  Idle  Delay
     7              [2200ns].  DSSI nodes intending to gain bus access which
     8              are not previously monitoring the bus and are  currently
     9              disabled  shall monitor the bus and detect DSSI bus idle
    10              condition when both BSY and SEL are simultaneously false
    11              for  a minimum of DSSI Idle Delay [2200ns].  A DSSI node
    12              shall become enabled upon  detecting  a  DSSI  bus  idle
    13              condition.

    14          3.  A disabled DSSI node that has a message  to  send  shall
    15              arbitrate  for  the DSSI bus only after detecting a DSSI
    16              bus idle condition and becoming enabled.  The  node  may
    17              omit arbitration step 1, since detecting a DSSI bus idle
    18              condition implies that the node has  also  detected  the
    19              BUS  FREE  phase.   After  detecting  a  DSSI  bus  idle
    20              condition, a disabled DSSI node that has  a  message  to
    21              send   shall   wait   the  bus  free  delay  [800ns]  of
    22              arbitration step 2, then assert BSY and its DSSI ID  for
    23              arbitration step 3.


    24     5.5.5.4  Rules For Manipulating The Enabled/Disabled Flag

    25     This  section  states  all  the  rules   for   manipulating   the
    26     enabled/disabled flag, repeating the rules stated in the previous
    27     two sections.  The rules are:


    28          1.  A newly initialized DSSI node or a DSSI  node  that  has
    29              otherwise  lost  track  of  DSSI  bus  context  shall be
    30              initially disabled.

    31          2.  An enabled DSSI node may spontaneously  become  disabled
    32              for any reason.  However, doing so will impair that DSSI
    33              node's performance.

    34          3.  A disabled DSSI node shall not become  enabled  for  any
    35              reason   other   than  detection  of  a  DSSI  bus  idle
    36              condition.





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     1          4.  Upon winning arbitration,  a  DSSI  node  shall  disable
     2              itself  prior  to  releasing  BSY  or  SEL (whichever it
     3              releases last).

     4          5.  A DSSI node shall enable itself upon  detecting  a  DSSI
     5              bus idle condition.


     6     5.5.5.5  ARBITRATION Phase Transitions

     7     ARBITRATION phase transitions are shown in the following figure.

     8                              +------------+           
     9                              |  BUS FREE  |<---------+
    10                              +------------+          |
    11                                     .                |
    12                                     .                ^
    13                             +---------------+        |
    14                             |  ARBITRATION  |--->----+
    15                             +---------------+ (2)(3)  
    16                                     |(1)      (4)     
    17                                     v                 
    18                             +---------------+         
    19                             |  SELECTION    |         
    20                             +---------------+         
    21                                     .                 
    22                                     .                 

    23                Figure 5-2:  ARBITRATION Phase Transitions

    24     All DSSI implementations shall detect the  following  events  and
    25     respond as described.

    26          1.  The node successfully arbitrates for the bus and  enters
    27              the SELECTION phase.

    28          2.  The node loses arbitration.   Upon  losing  arbitration,
    29              the  node  shall  release  all  signals,  wait  for  the
    30              BUS FREE phase and restart arbitration without notifying
    31              higher layers.

    32          3.  The node detected a Bus Reset condition.   If  the  node
    33              has  not  yet  become an initiator, it should treat this
    34              condition  as  if  the  node   had   lost   arbitration.
    35              Otherwise,   the  node  should  terminate  the  transmit
    36              request with a status of CC_NORSP.




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     1          4.  The node detected an Initiator Timeout.  The node  shall
     2              generate a Bus Reset and proceed as in event 3 above.


     3     5.5.6  SELECTION Phase

     4     This section describes the bus signals and timing associated with
     5     the  SELECTION phase, the phase used by the initiator to select a
     6     target device to receive information.

     7     Upon winning arbitration, the initiator is  asserting  SEL,  BSY,
     8     and the DATA BUS line corresponding to its DSSI ID.  To begin the
     9     transition from arbitration to selection, the initiator shall:

    10          1.  Wait at least 1200 ns after asserting SEL then,

    11          2.  Change the data bus to the  inclusive-or,  with  correct
    12              (asserted)  parity, of the initiator's and target's DSSI
    13              IDs.


    14     The initiator may "glitch" the data bus  by  first  releasing  it
    15     then  asserting the DSSI IDs, provided that the data bus does not
    16     change until at least 1200 ns after the initiator asserted SEL.

    17     After asserting the DSSI IDs onto the  data  bus,  the  initiator
    18     shall  wait  at  least  90ns, then release BSY.  The elapsed time
    19     from assertion of SEL to the release  of  BSY  shall  not  exceed
    20     2000ns.   The  initiator  shall  wait  a  minimum of 400 ns after
    21     releasing BSY before testing if BSY  has  been  asserted  by  the
    22     target.

    23     A device determines that an initiator has selected it as a target
    24     by observing that:

    25          1.  SEL is asserted,

    26          2.  BSY negated and,

    27          3.  the data bus has the target device's own and exactly one
    28              other   DSSI   ID   asserted,   and  parity  is  correct
    29              (asserted).


    30     Devices shall determine that they are selected whenever they  are
    31     not  the  initiator  and  such  a pattern is stable on the bus as
    32     described below.



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     1     The device shall determine that it is  selected  no  sooner  than
     2     after  SEL,  BSY,  and  the target device's own DSSI ID have been
     3     stable for a minimum of 400 ns, and the remaining data lines plus
     4     parity  are  correct at the end of the stable period.  The device
     5     shall determine that it is selected no later than 20us after  all
     6     signals have been stable.

     7     A device that determines it has been selected as a target:

     8          1.  Shall respond to selection by  asserting  BSY  no  later
     9              than 20 us after BSY became stable and negated,

    10              and preferably as quickly as possible.

    11          2.  Shall not assert BSY, and not consider itself  selected,
    12              if any bus signals change,

    13          3.  Shall save the initiator's DSSI ID, determined from  the
    14              data bus.


    15     After asserting BSY, the target device may assert or  change  C/D
    16     and/or I/O to prepare for an information transfer phase.

    17                                   NOTE

    18             As described in  section  5.5.7,  an  information
    19             transfer  phase does not actually begin until the
    20             assertion of REQ by the target.


    21     After releasing BSY, the initiator shall wait a  minimum  of  400
    22     ns,  then  begin observing BSY for the target's response.  If the
    23     the initiator sees BSY asserted, it shall wait a  minimum  of  90
    24     ns,  then it shall release SEL and may release or change the data
    25     bus.   The  bus  is  entering  an  information  phase  after  the
    26     initiator  releases  SEL,  and the initiator should interpret bus
    27     signals as described in note 1 on page 5-23.   The  C/D  and  I/O
    28     signals control what the initiator should do with the data bus.

    29     If the initiator does not see BSY  asserted  within  a  Selection
    30     Timeout  interval from the time it released BSY, then a selection
    31     timeout has occurred.  The initiator shall release the  data  bus
    32     following  the  Selection Timeout interval, then wait a Selection
    33     Abort interval.  If the initiator sees BSY  asserted  during  the
    34     Selection  Abort  interval,  the  initiator  shall  treat it as a
    35     normal target response to selection.   If  BSY  is  not  asserted



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     1     before  the  end  of  the Selection Abort interval, the initiator
     2     shall release SEL and report a selection timeout error to  higher
     3     layers.   Note  that,  upon  releasing  SEL,  the  initiator  has
     4     released all bus signals.

     5     The minimum Selection Timeout  interval  shall  be  20  us.   The
     6     maximum  Selection  Timeout  interval shall be 30us or less.  The
     7     Selection Abort interval shall be 20us minimum and 30us maximum.

     8     An  implementation   conforms   with   this   selection   timeout
     9     requirement  if  it  initiates selection abort within the maximum
    10     timeout interval  for  at  least  95  percent  of  all  selection
    11     failures  that  occur  over a period of 10 minutes or more in any
    12     operational configuration.  In no case shall selection  abort  be
    13     initiated in less than the minimum selection timeout interval.

    14     "Operational configuration" means any configuration that does not
    15     contain  an  identifiable failure or some component that requires
    16     replacement.

    17                                   NOTE

    18             Certain  datalink  implementations,   listed   in
    19             appendix  H,  do  not  provide  a  mechanism  for
    20             detecting selection timeout.


    21     5.5.6.1  SELECTION Phase Transitions

    22     The  figure  below( figure  5-3 )  shows  the  transitions   that
    23     terminate the SELECTION phase.



















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     1                            +--------+                   
     2                            |BUS FREE|<-----------------+
     3                            +--------+                  |
     4                                .                       ^
     5                                .                       |
     6                        +----------------+     (2)(5)   |
     7                        |    SELECTION   |------------>-+
     8                        +----------------+              |
     9                         |      |(1)    |(3)            ^
    10                         |      |       V               |
    11                         |      | +-----------+         |
    12                         |      | |Unexpected |         |
    13                         |      | |Information|------->-+
    14                         |      | |Phase      |          
    15                         |(4)   | +-----------+          
    16                         |      V                        
    17                         |   +---------+                 
    18                         |   | Cmd Out |                 
    19                         |   +---------+                 
    20                         |        .                      
    21                         V        .                      
    22                       +-----------+                     
    23                       | Status In |                     
    24                       +-----------+                     
    25                             .                           
    26                             .                           

    27                 Figure 5-3:  SELECTION Phase Transitions


    28     All DSSI implementations shall detect the  following  events  and
    29     respond as described.

    30          1.  The target  has  detected  a  valid  selection  and  has
    31              responded  by  asserting BSY and driving the COMMAND OUT
    32              phase.

    33          2.  The initiator has failed to receive a selection response
    34              within  the  selection  timeout  period.   The initiator
    35              shall release all signals, enter the BUS FREE phase  and
    36              terminate  the  transmit request with a an error status.
    37              A status equivalent to CC_NORSP  shall  be  returned  to
    38              higher datalink layers.        

    39              Selection response failures may result from:





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     1              a.  An attempt to select a non-existent node, or

     2              b.  Detection of an invalid selection by the remote node
     3                  (see section 5.5.6 ).


     4          3.  The target has responded to selection by  asserting  BSY
     5              but  has  entered an invalid information phase ( a phase
     6              other that  STATUS IN  or  COMMAND OUT ).   See  section
     7              5.5.7.4.

     8          4.  The target has detected a valid  selection  but  has  no
     9              Packet  Receive  buffer  free.   The  target shall drive
    10              STATUS IN and return a value of NAK to the initiator.

    11              The initiator shall return a status of CC_NAK to  higher
    12              layers.

    13          5.  The initiator has detected Bus Reset while waiting for a
    14              target  response.   The  initiator  shall  terminate the
    15              transmit request and return an error  status  to  higher
    16              layers.   A  value  equivalent  to  CC_NORSP  should  be
    17              returned.


    18     5.5.7  Information Transfer Phases

    19     The COMMAND OUT, DATA OUT and STATUS IN phases  are  collectively
    20     referred  to  as the Information Transfer phases because they are
    21     all  used  to  transfer  data  or  control  information  via  the
    22     DATA BUS.

    23     The information phases are determined by the state of the C/D and
    24     I/O signals as shown in the following table.
















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     1       Signal                                                      
     2       ------                                                      
     3       C/D   I/O           Phase Name           Transfer Direction 
     4       ---   ---           ----------           ------------------ 

     5        0     0            DATA OUT             Initiator to target
     6        0     1              **                         **         
     7        1     0            COMMAND OUT          Initiator to target
     8        1     1            STATUS IN            Target to initiator

     9                  Key: 0 = False, 1 = True, ** = Reserved


    10                 Table 5-4:  Information Transfer Phases


    11     The target, by driving the C/D  and  I/O  signals,  controls  all
    12     changes from one phase to another.

    13     The  information  transfer  phases  use  one  or   more   REQ/ACK
    14     handshakes  to  control  the  information transfer.  Each REQ/ACK
    15     handshake allows the transfer of one byte of information.

    16     During the information  transfer  phases  the  BSY  signal  shall
    17     remain true and the SEL signal shall remain false.  Additionally,
    18     during  the  information  transfer  phases,  the   target   shall
    19     continuously  envelope  the REQ/ACK handshake(s) with the C/D and
    20     I/O signals in such a manner that these control signals are valid
    21     for  a  bus  settle  delay  [ 400ns ] before assertion of the REQ
    22     signal of the first handshake and remain valid  until  after  the
    23     negation  of  the  ACK  signal at the end of the handshake of the
    24     last transfer of the phase.

    25                                   NOTES


    26             1.  After the negation of the ACK signal  of  the
    27                 last  transfer  of  the phase, the target may
    28                 prepare for  a  new  phase  by  asserting  or
    29                 negating  the  C/D  and  I/O  signals.  These
    30                 signals   may   be   changed   together    or
    31                 individually.   They  may  be  changed in any
    32                 order and may be changed more than once.   It
    33                 is desirable that each line change only once.
    34                 A new information phase does not begin  until
    35                 the REQ signal is asserted for the first byte
    36                 of the new phase.



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     1             2.  An information phase  is  defined  as  ending
     2                 when  the C/D or I/O signals change after the
     3                 assertion  of  the  ACK  signal.   The   time
     4                 between  the end of a phase and the assertion
     5                 of the REQ signal beginning a  new  phase  is
     6                 undefined  ( except  for  the ultimate limits
     7                 imposed   by   the   initiator   and   target
     8                 timeouts ).    An  initiator  is  allowed  to
     9                 anticipate a new phase based on the  previous
    10                 phase,  the  expected  new  phase,  and early
    11                 information provided by changes  in  the  C/D
    12                 and  I/O  signals.   However, the anticipated
    13                 phase is not valid until the  REQ  signal  is
    14                 asserted at the beginning of the next phase.



    15     5.5.7.1  Asynchronous Information Transfer

    16     The target shall control the direction of transfer  by  means  of
    17     the  I/O  signal.  When the I/O signal is true, information shall
    18     be transferred from the target to the initiator.   When  the  I/O
    19     signal  is  false,  information  shall  be  transferred  from the
    20     initiator to the target.

    21     If the I/O signal is true  ( transfer  to  the  initiator ),  the
    22     target  shall  first  drive the DATA BUS signals to their desired
    23     values, delay at least one deskew delay  [ 45ns ]  plus  a  cable
    24     skew  delay  [ 10ns ],  then assert the REQ signal.  The DATA BUS
    25     signals shall remain valid until the ACK signal is  true  at  the
    26     target.   The initiator shall read the DATA BUS signals after the
    27     REQ signal is true then indicate its acceptance of  the  data  by
    28     asserting the ACK signal.

    29     When the ACK signal becomes true at the target,  the  target  may
    30     change  or  release the DATA BUS signals and shall negate the REQ
    31     signal.  After the REQ signal is false, the initiator shall  then
    32     negate the ACK signal.  After the ACK signal is false, the target
    33     may continue the transfer by driving  the  DATA<7:0>  and  PARITY
    34     signals and asserting the REQ signal as described above.

    35     If the I/O signal is false ( transfer to the target ) the  target
    36     shall  request  information  by  asserting  the  REQ signal.  The
    37     initiator shall drive the DATA<7:0 > and PARITY signals to  their
    38     desired  values,  delay at least one deskew delay [ 45ns ] plus a
    39     cable skew  delay  [ 10ns ]  and  assert  the  ACK  signal.   The
    40     initiator shall coninue to drive the DATA<7:0> and PARITY signals



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     1     until the REQ signal is false.

     2     When the ACK signal becomes true at the target, the target  shall
     3     read the DATA<7:0> and PARITY signals then negate the REQ signal.
     4     When the REQ signal becomes false at the initiator, the initiator
     5     may  change  or release the DATA BUS signals and shall negate the
     6     ACK signal.  The target may continue the  transfer  by  asserting
     7     the REQ signal as described above.

     8     5.5.7.2  Synchronous Data Transfer

     9     Support for Synchronous Data Transfers ( Synchronous Burst Mode )
    10     is mandatory for all implementations.

    11     Synchronous Data transfers require the use of  a  REQ/ACK  offset
    12     parameter  that  specifies  the maximum number of REQ pulses that
    13     can be sent by the target in advance of the number of ACK  pulses
    14     received  from  the  initiator.  As discussed in section 5.5.7.5,
    15     the target determines the maximum allowable offset  by  comparing
    16     the  REQ/ACK  offset sent by the initiator during the COMMAND OUT
    17     phase with the target's  value  for  this  parameter,  using  the
    18     smaller of the two.  For the DSSI, the only legal values for this
    19     parameter are three (3), seven (7) or  fifteen  (15).   All  DSSI
    20     nodes should implement the maximum value.

    21     If the number of REQ pulses exceeds the number of ACK  pulses  by
    22     the  REQ/ACK  offset,  the target shall not assert the REQ signal
    23     until after the leading edge of the next ACK pulse is received.

    24     The target shall assert the  REQ  signal  for  a  minimum  of  an
    25     assertion period [ 90ns ].The target shall then wait at least the
    26     transfer period [ 180ns ] from the last  transition  of  the  REQ
    27     signal to true before again asserting the REQ signal.

    28     The initiator shall send one pulse on the ACK signal for each REQ
    29     pulse  received.   The  ACK signal may be asserted as soon as the
    30     leading edge of the corresponding REQ pulse  has  been  received.
    31     The  initiator  shall  assert  the ACK signal for a minimum of an
    32     assertion period [ 90ns ].  The initiator shall wait at least the
    33     transfer  period  [ 180ns ]  from  the last transition of the ACK
    34     signal to true before again asserting the ACK signal.

    35     During the DATA OUT  phase  ( C/D  false  and  I/O  false ),  the
    36     initiator  shall  transfer  one byte for each REQ pulse received.
    37     After receiving the leading edge of a REQ  pulse,  the  initiator
    38     shall  first  drive the DATA BUS signals to their desired values,
    39     delay at least one deskew delay  [ 45ns ]  plus  one  cable  skew



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     1     delay  [ 10ns ]  then assert the ACK signal.  The initiator shall
     2     hold the DATA BUS signals valid for at  least  one  deskew  delay
     3     [ 45ns ]  plus  one  cable skew delay [ 10ns ] plus one hold time
     4     [ 45ns ] after the assertion of the ACK  signal.   The  initiator
     5     shall assert the ACK asignal for a minimum of an assertion period
     6     [ 90ns ].  The initiator may then negate the ACK signal  and  may
     7     change  or  release  the DATA BUS signals.  The target shall read
     8     the value of the DATA BUS signals within one hold  time  [ 45ns ]
     9     of the transition of the ACK signal to true.

    10     The target shall not assert a new information phase ( by changing
    11     C/D and I/O ) until its counts of REQ and ACK pulses are equal.

    12     A  target  shall  determine  that  a  synchronous  transfer   has
    13     completed successfully when:

    14          1.  The target's counts of REQ and ACK pulses are equal,

    15          2.  The number of  bytes  received  equals  the  byte  count
    16              parameter   supplied   by   the   initiator  during  the
    17              COMMAND OUT  phase  plus  one  byte  for  the   appended
    18              checksum.

    19          3.  No parity or checksum errors are detected.


    20     The  target  shall  detect  and  respond  to  errors   during   a
    21     synchronous transfer as follows:

    22           o  The target detects more REQs than  the  number  of  ACKs
    23              sent.   The  target shall abort the transfer by entering
    24              the BUS FREE phase.

    25           o  The target detects a  parity  or  checksum  error.   The
    26              target  shall  drive the STATUS IN phase ( observing the
    27              above constraints  regarding  the  assertion  of  a  new
    28              information  phase )  and  return  a value of NAK to the
    29              initiator.


    30     The target shall respond to all  other  errors  by  entering  the
    31     BUS FREE phase.








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           Bus Protocol                                        27 March 1990


     1     5.5.7.3  Signal Restrictions Between Information Phases

     2     When the DSSI bus is between two information transfer phases, the
     3     following restrictions shall apply to the DSSI bus signals:

     4          1.  The BSY, SEL, REQ and ACK signals shall not change.

     5          2.  The C/D, I/O, DATA and PARITY signals may change.   When
     6              switching  the  DATA BUS  direction from out ( initiator
     7              driving ) to in ( target  driving ),  the  target  shall
     8              delay  driving  the  DATA BUS by at least a data release
     9              delay [ 400ns ] plus a bus settle delay [ 400ns ]  after
    10              asserting  the  I/O  signal.  In addition, the initiator
    11              shall release the DATA BUS no later than a data  release
    12              delay  [ 400ns ]  after the transition of the I/O signal
    13              to true.  When switching the DATA BUS direction from  in
    14              ( target  driving )  to  out  ( initiator driving ), the
    15              target shall release the DATA BUS no later than a deskew
    16              delay [ 45ns ] after negating the I/O signal.

    17          3.  The RST signal may change at any time  as  described  in
    18              section 5.5.1.3.


    19     5.5.7.4  Information Phase Error Conditions

    20     The following error conditions  are  common  to  all  information
    21     transfer  phases and shall be handled as described below.  In all
    22     cases, the initiator shall terminate the transmit request with an
    23     error  status.   A  value  of CC_NAK should be returned to higher
    24     layers.

    25          1.  Target Timeout - The target shall  release  all  signals
    26              and return to the BUS FREE phase as described in section
    27              5.5.1.4.

    28          2.  Premature BUS FREE phase detected by  initiator  -  This
    29              condition    occurs    as    the   result   of   certain
    30              target-detected errors ( eg:  synchronous data  transfer
    31              errors ( see section 5.5.7.2) ).

    32          3.  Initiator Timeout  -  The  initiator  shall  generate  a
    33              Bus Reset  and abort the request as described in section
    34              5.5.1.3.






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           Bus Protocol                                        27 March 1990


     1                                        NOTE

     2                  Implementations listed in appendix H that do not
     3                  support   selection   timeout  shall  report  an
     4                  initiator   timeout   condition   with    status
     5                  CC_NORSP.


     6          4.  Invalid information transfer  phase  -  The  target  has
     7              asserted  an unexpected information transfer phase.  The
     8              initiator shall generate a Bus Reset.

     9          5.  "Third-party" Bus Reset -- A bus reset,  asserted  by  a
    10              node  other  than  the initiator, during any information
    11              transfer phase shall be handled as described in  section
    12              5.5.1.3.


    13     5.5.7.5  The COMMAND OUT Phase

    14     In the COMMAND OUT phase, the target solicits from the  initiator
    15     a 6-byte Command Descriptor block ( plus checksum ) that contains
    16     control information required by the target  during  the  DATA OUT
    17     phase.

    18     The target shall assert C/D and transfer  the  information  using
    19     the  rules  for  asynchronous  information  transfer described in
    20     section 5.5.7.1.

    21     The format and rules for validating the  Command  Descriptor  are
    22     given below.



















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     1         7     6     5     4     3     2      1     0             
     2       +-----+-----+-----+-----+-----+-----+-----+-----+           
     3       |        Data Link Operation Code ( E0h )       |  command+0
     4       +-----------------------+-----------------------+           
     5       |    REQ/ACK Offset     |   Protocol Identifier |  command+1
     6       +-----------------------+-----+-----------------+           
     7       |         Reserved            | Dest. Node I/D  |  command+2
     8       +-----------------------------+-----------------+           
     9       |         Reserved            | Source Node I/D |  command+3
    10       +-----------------------------+-----------------+           
    11       |            Data Block Length<7:0>             |  command+4
    12       +-----------------+-----------------------------+           
    13       |    Reserved     |    Data Block Length<12:8>  |  command+5
    14       +-----------------+-----------------------------+           
    15       |                  Checksum                     |  command+6
    16       +-----------------------------------------------+           

    17         Figure 5-4:  Format of DSSI Command Out Descriptor Block



    18     The fields of the  DSSI  Command  Out  descriptor  block  are  as
    19     follows:


    20          Command + 0 - Datalink Operation Code


    21               Defines the Target Data Link function to be  performed.
    22               Only  one  function  is  defined:  "Receive Data Block"
    23               having a value of E0h.  An illegal  value  shall  cause
    24               the Target to return NAK status.




    25          Command + 1 <3:0> - Protocol Identifier


    26               A nibble that identifies a protocol layer, serviced  by
    27               the Data Link, to receive the data block.  A value of 0
    28               specifies delivery to the CI  Port  Layer.   For  codes
    29               that  are  unsupported,  the  Target  Data  Link  shall
    30               process such errors as described in section 5.5.7.6.1.






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     1          Command + 1 <7:4> - REQ/ACK Offset


     2               A nibble that contains the initiator's maximum  REQ/ACK
     3               offset.  The only valid values for this field are three
     4               (3), seven (7), or fifteen (15).   An  illegal  REQ/ACK
     5               offset shall cause the Target to return NAK status.


     6          Command + 2 <2:0> - Destination node I/D


     7               The DSSI Bus ID of the node receiving  the  information
     8               (i.e., the Target).  The Target shall return NAK status
     9               if this value is not equal to the Target's node I/D.


    10          Command + 2 <7:3> - Reserved


    11               See section 5.5.7.6.1.


    12          Command + 3 <2:0> - Source node I/D


    13               The  DSSI  Bus  I/D  of  the  node   transmitting   the
    14               information  (i.e.,  the  initiator).  The target shall
    15               verify the initiator's Node I/D by comparing it against
    16               the  Node  I/D received during selection, returning NAK
    17               status if these values differ.


    18          Command + 3 <7:3> - Reserved


    19               See section 5.5.7.6.1.


    20          Command + 4 <7:0> - Data Block Length <7:0>


    21          Command + 5 <4:0> - Data Block Length <12:8>


    22               The Data Block Length parameter is a 13-bit value  that
    23               is  returned  in  two consecutive bytes as shown above.



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     1               This value specifies the length of the  data  block  in
     2               bytes ( excluding the checksum ).  See section 5.5.8.1.


     3          Command + 5 <7:5> - Reserved


     4               See section 5.5.7.6.1.


     5          Command + 6 - Checksum


     6               This  field  contains  the  vertical  checksum  of  the
     7               Command  Descriptor and shall be computed as the XOR of
     8               the first 6 bytes.  It is generated  by  the  initiator
     9               and  checked  by the target.  The checksum contents are
    10               calculated as:


    11               checksum = command + 0 XOR Command +1 XOR ...
    12                          XOR Command + 5


    13               Detection of an invalid checksum by  the  Target  shall
    14               cause the Target to return NAK status.



    15     5.5.7.6  Command Out Descriptor Validation Precedence

    16     Fields that result in NAK status when invalid  shall  be  checked
    17     before  all  other  fields.   Reports  of  NAK  status shall take
    18     precedence over all other validation error responses.

    19                                   NOTE

    20             A validation error that results in NAK status may
    21             be reported as soon as the erroneous parameter is
    22             received ( validation "on the fly" ) or  deferred
    23             until  after  the entire Command Descriptor block
    24             has been read in.








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           Bus Protocol                                        27 March 1990


     1     5.5.7.6.1  Reserved Field Validation

     2     A field designated as a reserved field shall be set to zero ( 0 )
     3     by the initiator.

     4     Targets should validate reserved fields.  An implementation  that
     5     performs such validation shall:

     6          1.  Complete the transaction with the  initiator,  including
     7              error  recovery retries, and return an ACK status to the
     8              initiator if the packet was received correctly.

     9          2.  Discard the packet if any reserved field in the  Command
    10              Descriptor block is non-zero.


    11     Higher protocol  layers  in  the  initiator  or  target  are  not
    12     notified  when such a packet is discarded.  A discarded packet is
    13     handled  through  provisions  in  higher  level   protocols   for
    14     detecting lost packets.

    15     5.5.7.6.2  COMMAND OUT Phase Transitions

    16     The following figure ( figure  5-5  shows  the  transitions  that
    17     terminate the COMMAND OUT phase.

























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           Bus Protocol                                        27 March 1990


     1                               +--------+              
     2                               |BUS FREE|<------------+
     3                               +--------+             |
     4                                   .                  ^
     5                                   .                  |
     6                           +----------------+  (2)    |
     7                           |  COMMAND OUT   |------->-+
     8                           +----------------+  (5)    |
     9                            |      |(1)    |(3)       ^
    10                            |      |       V          |
    11                            |      | +-----------+    |
    12                            |      | |Unexpected |-->-+
    13                            |      | |Information|     
    14                            |      | |Phase      |     
    15                            |(4)   | +-----------+     
    16                            |      V                   
    17                            |   +---------+            
    18                            |   | Data Out|            
    19                            |   +---------+            
    20                            V                          
    21                          +-----------+                
    22                          | Status In |                
    23                          +-----------+                

    24                Figure 5-5:  COMMAND OUT Phase Transitions

    25     All DSSI implementations shall detect the  following  events  and
    26     respond as described.

    27          1.  A valid Command Descriptor block has been  read  by  the
    28              target.  The target shall assert the DATA OUT phase.

    29          2.  An  initiator  or  target  timeout  has  occurred.   See
    30              section 5.5.7.4.

    31          3.  The initiator detects an  unexpected  information  phase
    32              ( a  phase  other  than  STATUS IN  or  DATA OUT).   See
    33              section 5.5.7.4.

    34          4.  The target has detected a parity or  checksum  error  in
    35              the  Command  Descriptor  block  or  has  discovered  an
    36              invalid command  parameter.   ( The  Command  Descriptor
    37              contents  and  validation rules are described in section
    38              5.5.7.5. ) The target shall enter  the  STATUS IN  phase
    39              and return a status of NAK to the initiator.

    40              The initiator shall terminate the transmit request  with



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           Bus Protocol                                        27 March 1990


     1              an  error  status.  A value of CC_NAK should be returned
     2              to higher layers.

     3          5.  A  Bus  Reset  condition  occurred.   This  conditon  is
     4              processed as described in section 5.5.7.4.


     5     5.5.8  The DATA OUT Phase

     6     The target enters the DATA OUT phase by deasserting C/D and  I/O.
     7     The  target  and initiator then interact to transfer a Data Block
     8     whose format  is  described  below.   The  data  block  shall  be
     9     transmitted   using  the  rules  for  synchronous  data  transfer
    10     described in section 5.5.7.2.

    11     As shown in figure 5-6, a DSSI data block consists of the  number
    12     of   bytes   (   n  )  specified  in  the  length  field  of  the
    13     Command Descriptor block plus one byte of vertical checksum.


    14           7     6     5     4     3     2     1     0
    15        +-----+-----+-----+-----+-----+-----+-----+-----+
    16        |              information byte 0               |  data text+0
    17        +-----------------------------------------------+
    18        |              information byte 1               |  data text+1
    19        +-----------------------------------------------+
    20                              ...
    21        +-----------------------------------------------+
    22        |              information byte n - 2           |  data text+(n-2)
    23        +-----------------------------------------------+
    24        |              information byte n - 1           |  data text+(n-1)
    25        +-----------------------------------------------+
    26        |                 Checksum                      |  data text+(n)
    27        +-----------------------------------------------+

    28                      Figure 5-6:  DSSI Data Format


    29     The checksum byte is computed as the XOR of  all  preceding  data
    30     bytes.   It  is  generated  by  the  initiator and checked by the
    31     target.  The checksum contents are calculated as:


    32     Checksum = data text+0 XOR data text+1 XOR data text+2 ...
    33                XOR data text+(n-2) XOR data text+(n-1).





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     1     5.5.8.1  Data Block Length

     2     The  minimum  data  block  size  transmitted  by  the  initiator,
     3     excluding  the  checksum,  shall  not  be less than 2 bytes.  The
     4     maximum shall not exceed the largest value allowed by the  higher
     5     level protocols serviced by the target's datalink layer.  For the
     6     CI  port  protocol,  the  maximum  value  is  specified  in   the
     7     MAX_BODY_LEN parameter transmitted in the ID packet.

     8     The target datalink should be able to receive and buffer  in  its
     9     Receive  Packet  Buffer  all  data blocks, up to the maximum size
    10     that can be specified  in  the  Command Descriptor  block  ( 8191
    11     bytes ).

    12     Any packet received by the datalink layer  that  is  outside  the
    13     upper  or lower limits accepted by higher layers should be passed
    14     to the higher layer.  If an error-free  data  block  is  received
    15     that  is  too  long,  ( greater than MAX_BODY_LEN for the CI port
    16     layer ), the  packet  should  be  truncated  and  delivered  with
    17     notification that an oversize data block was received.

    18                                   NOTE


    19             The  paragraphs  above  describe  the   preferred
    20             method  for  handling  oversize packets.  Certain
    21             DSSI datalink  implementations,  however,  cannot
    22             receive  such  packets without buffer overflow or
    23             other adverse side  effects.   To  prevent  these
    24             conditions,  such  an  implementation  may  abort
    25             packet  transmission  by  checking   the   length
    26             parameter  in  the  Command  Descriptor block and
    27             issuing a NAK status whenever an invalid value is
    28             detected.

    29             Appendix   D,   "Implementation    Functionality"
    30             describes   how   specific  DSSI  implementations
    31             handle such conditions.


    32     5.5.8.2  DATA OUT Phase Transitions

    33     The following transitions terminate the DATA OUT phase.







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           Bus Protocol                                        27 March 1990


     1                               +--------+              
     2                               |BUS FREE|<------------+
     3                               +--------+             |
     4                                   .                  ^
     5                                   .                  |
     6                           +----------------+  (4)(5) |
     7                           |   DATA OUT     |------->-+
     8                           +----------------+         |
     9                                   |(1)    |(3)       ^
    10                                   |(2)    V          |
    11                                   | +-----------+    |
    12                                   | |Unexpected |-->-+
    13                                   | |Information|     
    14                                   | |Phase      |     
    15                                   | +-----------+     
    16                                   V                   
    17                              +-----------+            
    18                              | STATUS IN |            
    19                              +-----------+            
                                                             

    20                 Figure 5-7:  DATA OUT Phase Transitions

    21     All DSSI implementations shall detect the  following  events  and
    22     respond as described.

    23          1.  The  DATA OUT  phase  has   completed   succesfully   as
    24              described in section 5.5.7.2.  The target shall return a
    25              status value of ACK.

    26          2.  The target detected a parity  or  checksum  error.   The
    27              target shall return a status of NAK.

    28              The initiator shall terminate the transfer with an error
    29              status.   A value of CC_NAK should be returned to higher
    30              layers.

    31          3.  The initiator has  detected  an  unexpected  information
    32              phase  ( a  phase  other  than STATUS IN ).  See section
    33              5.5.7.4.

    34          4.  The target detected one of the synchronous data transfer
    35              errors described in section 5.5.7.2.

    36          5.  An initiator timeout, target timeout  or  Bus Reset  has
    37              occurred.  See section 5.5.7.4.




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           Bus Protocol                                        27 March 1990


     1     5.5.8.3  The STATUS IN Phase

     2     The target asserts the STATUS IN phase by  setting  C/D  and  I/O
     3     true.   The  target then transfers a single byte of status to the
     4     initiator using the rules for asynchronous transfers described in
     5     section 5.5.7.1.

     6     Only two values are legal ACK ( 61h), indicating success, or  NAK
     7     (  1Eh  ),  indicating  failure.   The  associated  bit patterns,
     8     including parity, are shown below ( figure 5-8 ).

     9              P   7   6   5   4   3   2   1   0                
    10            +---+---+---+---+---+---+---+---+---+              
    11            | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | status text+0
    12            +---+---+---+---+---+---+---+---+---+              
    13                      ACK Status ( 61h )                       


    14              P   7   6   5   4   3   2   1   0                
    15            +---+---+---+---+---+---+---+---+---+              
    16            | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | status text+0
    17            +---+---+---+---+---+---+---+---+---+              
    18                      NAK Status ( 1Eh )                       



    19                 Figure 5-8:  DSSI STATUS IN Data Formats


    20     The above patterns are  selected  to  reduce  the  likelihood  of
    21     undetected  errors by maximizing the code distance, including the
    22     odd parity bit, between the specified legal values.

    23     5.5.8.4  STATUS IN Phase Transitions

    24     The following figure shows the  transitions  that  terminate  the
    25     STATUS IN phase.













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           Bus Protocol                                        27 March 1990


     1                             +----------+         
     2                             | BUS FREE |<-------+
     3                             +----------+        |
     4                                   .             |
     5                                   .             |
     6                            +------------+ (1)(2)|
     7                            |  STATUS IN |--->---+
     8                            +------------+ (3)   |
     9                                   | (4)         |
    10                                   v             |
    11                           +-----------------+   |
    12                           | Any Other Phase |->-+
    13                           +-----------------+    

    14                 Figure 5-9:  STATUS IN Phase Transitions

    15     All DSSI implementations shall detect the  following  events  and
    16     respond as described.

    17          1.  The   initiator   has   successfully    completed    the
    18              asynchronous  transfer  of  status  by asserting the ACK
    19              signal as described in section 5.5.7.1.

    20              The target shall enter the BUS FREE phase.   If,  during
    21              the  STATUS IN  phase  just  completed,  the  target has
    22              returned  a  value   of   ACK,   signifying   error-free
    23              completion  of  the  DATA OUT  phase,  the  target shall
    24              forward the received data packet to higher layers.   The
    25              initiator  shall  return  a  status  of CC_ACK to higher
    26              layers.

    27          2.  The STATUS IN value received by the initiator  contained
    28              a  parity  error or value other than ACK.  The initiator
    29              shall terminate the transfer  and  return  a  status  of
    30              CC_NAK ( or its equivalent ) to higher datalink layers.

    31          3.  An  initiator  or  target  timeout  has  occurred.   See
    32              section 5.5.7.4.

    33          4.  The initiator has detected a phase other than  BUS FREE.
    34              The  initiator  shall  reset the bus and should return a
    35              status of  CC_NAK  (  or  its  equivalent  )  to  higher
    36              datalink layers.







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           Performance And Diagnostic Counters                 27 March 1990


     1     5.6  Performance And Diagnostic Counters

     2     For purposes of monitoring performance and to aid diagnosis,  all
     3     DSSI nodes shall maintain the counters described in this section.
     4     These counters shall be 32 bits in length, operated  upon  as  an
     5     unsigned  integer,  and readable by higher layers such that their
     6     values may be collected via higher layer  protocols.   All  nodes
     7     should  maintain  at  least one set of these counters, and higher
     8     layer protocols may specify whether the  events  to  a  specified
     9     node or to all nodes should be counted.

    10     In addition to the counters described in  this  section,  a  DSSI
    11     node  may  implement additional counters and include their values
    12     in the response returned to higher layers.  The format and use of
    13     implementation-specific  counters  is  outside  the scope of this
    14     document.

    15     The counters should be updated by a node only if  a  previous  or
    16     current communication to the destination node is successful since
    17     the counters were last reset.  A counter value  of  FFFFFFFFh  is
    18     not valid and indicates an error or overflow condition.

    19     All nodes shall provide an appropriate mechanism for reading  and
    20     clearing  these  counters.   Nodes  that  implement a VAX CI Port
    21     interface to the host should use the CI Port Read  Count  command
    22     ( RDCNT ).

    23     5.6.1  Counter Descriptions

    24     The following list describes  the  events  to  be  counted.   The
    25     two-letter symbolic preface indicates the layer in which the data
    26     is collected ( ie:  PL = Port Layer, DL = Datalink layer).

    27          1.  DL_TIME:   Time  (in  10  msec  ticks)  since  all   the
    28              diagnostic and performance counters were last zeroed.

    29          2.  DL_ACKS_REC:  Total Number of frames transmitted by this
    30              node  successfully  ( ie:  total number of ACKs received
    31              ).

    32          3.  DL_ACKS_SENT:  Total number of frames received  by  this
    33              node successfully (i.e., ACKs sent ).

    34          4.  DL_BUS_EXCEPTIONS:  Number of transmission attempts from
    35              this node that terminated with error status due to:





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     1              1.  Premature target transition to BUS FREE.

     2              2.  Local node asserting Bus Reset ( eg:  upon detecting
     3                  an  initiator  timeout ).  ( Also included in DL_RST
     4                  parameter below.)

     5              3.  Local node detecting Selection Timeout.


     6          5.  DL_NAKSREC:  Number frames transmitted  from  this  node
     7              for which a NAK status was received during the STATUS IN
     8              phase

     9          6.  DL_ILLPHASE:  Number of  frames  transmitted  from  this
    10              node  that  resulted  in  the target entering an illegal
    11              phase.

    12          7.  DL_RST:  Number of DSSI  Bus  Resets  asserted  by  this
    13              node.

    14          8.  DL_RST_REC:  Number of DSSI bus RESETS detected but  not
    15              asserted by this node.

    16          9.  DL_CMDVAL_ERRS:  Number of command validation errors  in
    17              frames  received  by  this  node  ( ie:   errors  in the
    18              Command Descriptor block) ).  This count should  include
    19              errors due to bits set in reserved fields.

    20         10.  DL_DATA_ERRORS:   Number   of   frames   received   with
    21              redundancy   errors   ( checksum  or  horizontal  parity
    22              errors ) by this node.

    23         11.  DL_BYTES_SENT:  Total number  of  bytes  transmitted  by
    24              this node (sum of frame lengths)

    25         12.  DL_BYTES_REC:  Total number of bytes  received  by  this
    26              node (sum of frame lengths)

    27         13.  PL_DUP:  Total number of duplicate packets discarded  by
    28              this node's port layer.

    29         14.  PL_DG_DISCARD:  Total number of Datagrams discarded:  CI
    30              Datagrams discarded due to unavailable Datagram buffers.







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           Performance And Diagnostic Counters                 27 March 1990


     1     VAX CI Port implementations shall return the specified parameters
     2     in  the  CNTRD response packet fields indicated below.  All other
     3     counters in the fixed portion of the CNTRD packet shall be set to
     4     zero  ( 0 ).   The  specification of data returned in other CNTRD
     5     counter fields is outside the scope of this document.

     6          1.  PATH0_ACK:    DL_ACK   ( total    Number    of    frames
     7              transmitted ).

     8          2.  PATH0_NAK:  DL_NAK ( number of NAKs received ).

     9          3.  PATH0_NORSP:   DL_BUS_EXCEPTIONS  ( number   of   frames
    10              transmitted from this node for which the Channel Control
    11              layer detected an error other than CC_NAK ).

    12          4.  DG_DISC:    PL_DISC   ( total   number   of    Datagrsms
    13              discarded ).

































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           DSSI BUS ELECTRICAL AND PHYSICAL SPECIFICATION           Page 6-1
                                                               27 March 1990


     1                                 CHAPTER 6

     2              DSSI BUS ELECTRICAL AND PHYSICAL SPECIFICATION


     3     6.1  Introduction

     4     This chapter specifies the electrical and  physical  requirements
     5     for the DSSI bus.

     6     6.2  Electrical Description

     7     6.2.1  Required Signal Termination

     8     The configuration of devices and terminators on the bus shall  be
     9     as shown in figure 6-1.

    10     All assigned signals shall be terminated with 120 Ohms +/- 2%  to
    11     Vdd and 285 Ohms +/- 2% to ground at each end of the interconnect
    12     ( see figure 6-2 ).

    13              V                                            V   
    14               dd                                           dd 
    15              |                                            |   
    16              \                                            \   
    17           R1 /                                            / R1
    18              \                                            \   
    19              |                                            |   
    20              +----+-~~~~--+--------+--------+-------+-----+   
    21              |    |       |        |        |       |     |   
    22              \  +---+   +---+    +---+    +---+   +---+   \   
    23              /  |   |   |   |    |   |    |   |   |   |   /   
    24           R2 \  |   |   |   |    |   |    |   |   |   |   \ R2
    25              /  +---+   +---+    +---+    +---+   +---+   /   
    26              |  Device  Device   Device   Device  Device  |   
    27             GND   7       3        2        1       0    GND  

    28              Figure 6-1:  DSSI Bus Electrical Configuration












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           Electrical Description                              27 March 1990


     1             V                                     V          
     2              dd                                    dd        
     3             |                                     |          
     4             \                                     \          
     5             /  120 Ohms                           /  120 Ohms
     6             \                                     \          
     7             /                                     /          
     8             |---        Interconnect           ---|          
     9             |                                     |          
    10             \                                     \          
    11             /  285 Ohms                           /  285 Ohms
    12             \                                     \          
    13             /                                     /          
    14             |                                     |          
    15            GND                                   GND         

    16               Figure 6-2:  DSSI Bus Terminator Arrangement

    17     6.2.2  Terminator Package

    18     Acceptable terminator packages are listed in appendix \TBS\.  Any
    19     system  not  using these terminator packages for both ends of the
    20     bus shall use a terminator arrangement identical to that shown in
    21     figure  6-3.   This  means  that  the  decoupling  capacitors and
    22     resistor network shall be as shown on both ends of the  bus.   In
    23     addition, the tolerance on the resistors shall be +/- 2%.
























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           Electrical Description                              27 March 1990


     1                 +-------------------------------------------------+
     2                 |                                                 |
     3      TERMPWR ------+-------+------------+----------+------  ...   |
     4                 |  |       |            |          |              |
     5                 | ---     ---           \          \              |
     6                 | --- 1uF --- 0.047uF   / 120      /              |
     7                 |  |       |            \          \              |
     8                 | GND     GND           /          /              |
     9                 |                       +-----+    +-----+  ...   |
    10                 |                       |     |    |     |        |
    11                 |                       \     |    \     |        |
    12                 |                       / 285 |    /     |        |
    13                 |                       \     |    \     |        |
    14                 |                       /     |    /     |        |
    15                 |                       |     |    |     |        |
    16                 |                      GND    |   GND    |        |
    17                 +-----------------------------|----------|--------+
    18                                               |          |         

    19              Figure 6-3:  Terminator Package Configuration

    20     6.2.3  DSSI Driver

    21     The QDXX standard cell or its equivalent shall  be  used  as  the
    22     transciever  on  the  DSSI  bus.   For  futher information on the
    23     charactoristics of this cell and a list of approved  transceivers
    24     refer to appendix \TBS\

    25     6.2.4  Electrical Characteristics

    26     The electrical characteristics for the DSSI bus are described  in
    27     five   sections:    the   output   characteristics,   the   input
    28     characteristics,  the  terminator  power   characteristics,   the
    29     terminator power dissipation, and the noise margin.

    30     6.2.4.1  Output Characteristics

    31     The output characteristics are given in table 6-1.  They  specify
    32     the  requirements  which  shall  be  met  by any device driving a
    33     signal onto the DSSI bus.










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     1               +-------------+---------+---------+--------+
     2               |  Parameter  |   Min   |   Max   |  Units |
     3               +-------------+---------+---------+--------+
     4               |         Output Characteristics           |
     5               +-------------+---------+---------+--------+
     6               |  Signal     |   0.0   |   0.9   | Volts  |
     7               |  Assertion  |         |         |        |
     8               +-------------+---------+---------+--------+
     9               |  Signal     |   3.15  |  3.51   | Volts  |
    10               |  Deassertion|         |         |        |
    11               +-------------+---------+---------+--------+
    12               |  Driver     |         |   -87.5 |  mA    |
    13               |  Output     |         |(sinking)|        |
    14               |  Capability |         |         |        |
    15               +-------------+---------+---------+--------+
    16               |  Rise       |   10    |         |  nS    |
    17               |  Time       |         |         |        |
    18               +-------------+---------+---------+--------+
    19               |  Fall       |   10    |         |  nS    |
    20               |  Time       |         |         |        |
    21               +-------------+---------+---------+--------+

    22            Table 6-1:  DSSI Electrical Output Characteristics

    23     All signals shall be supplied  by  open  collector  or  tri-state
    24     drivers.   The  bus  is  pulled-up to the deasserted level by the
    25     terminators when the signal is in the high-impedance state.   The
    26     minimum deasserted voltage level occurs at the minimum TERMPWR of
    27     4.45V.  The  maximum  deasserted  voltage  level  occurs  at  the
    28     maximum TERMPWR of 5.25V.

    29     The output of drivers on the bus shall be trapezoidal  for  loads
    30     in the range 30pF to 300pF and 60 Ohms to 240 Ohms.

















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     1     6.2.4.2  Input Characteristics

     2     The input characteristics are given in table 6-2.   They  specify
     3     the  voltage  levels which shall be recognized by any receiver on
     4     the DSSI bus.

     5               +-------------+---------+---------+--------+
     6               |  Parameter  |   Min   |   Max   |  Units |
     7               +-------------+---------+---------+--------+
     8               |        Input Characteristics             |
     9               +-------------+---------+---------+--------+
    10               |  Signal     |         |   1.2   | Volts  |
    11               |  Asserted   |         |         |        |
    12               +-------------+---------+---------+--------+
    13               |  Signal     |   2.0   |         | Volts  |
    14               |  Deasserted |         |         |        |
    15               +-------------+---------+---------+--------+
    16               |  Input      |  -50    |   50    |  uA    |
    17               |  Leakage    | (per    | (per    |        |
    18               |  Current    | signal) | signal) |        |
    19               +-------------+---------+---------+--------+

    20            Table 6-2:  DSSI Electrical Input Characteristics

    21     6.2.5  Terminator Power Characteristics

    22     The terminator power characteristics  describe  the  requirements
    23     which  shall  be  met  by  the  device  supplying  power  to  the
    24     terminators.  They are given in table 6-3.

    25     The physical configuration  for  terminator  power  is  shown  in
    26     figure  6-4.   This  setup  shall be used by any device supplying
    27     power to the DSSI bus.  The decoupling capacitors C2 and  C3  are
    28     contained in the terminator package.

    29     Vdd shall be current limited to no more than 2 Amps.  This may be
    30     accomplished  using  either  a  fuse  or  active current limiting
    31     circuit.

    32     TERMPWR shall be between 4.45 Volts and 5.25 Volts.










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     1                         Device Supplying Power
     2                         +---------------------+
     3                         |       V             |
     4                         |        dd           |
     5                         |       |             |
     6                         |       |             |
     7                         |       |             |
     8                         |      ----           |
     9                         |      \  /           |
    10                         |       \/   D1       |
    11                         |      ----           |
    12                         |       |________     |
    13                         |       |       |     |
    14                         |       |      ---    |
    15                         |       |      --- C1 |
    16                         |       |       |     |
    17                         |       |      GND    |
    18                         +-------|-------------+
    19                                 |
    20                                 |
    21       Terminator Package        |             Terminator Package
    22       +-----------------+       |             +-----------------+
    23       |                 |       |   TERMPWR   |                 |
    24       |  +----------------------+----------------+--------+     |
    25       |  |        |     |                     |  |        |     |
    26       | ---      ---    |                     | ---      ---    |
    27       | --- C2   --- C3 |                     | --- C2   --- C3 |
    28       |  |        |     |                     |  |        |     |
    29       | GND      GND    |                     | GND      GND    | 
    30       |                 |                     |                 |
    31       +-----------------+                     +-----------------+
                                       
    32                  D1 - A diode or device to prevent the back flow of 
    33                       current from the bus to Vdd shall be used.

    34                  Decoupling Capacitors:
    35                    C1 - 0.47uF   
    36                    C2 - 1uF
    37                    C3 - 0.047uF

    38               Figure 6-4:  Terminator Power Configuration









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     1               +-------------+---------+---------+--------+
     2               |  Parameter  |   Min   |   Max   |  Units |
     3               +-------------+---------+---------+--------+
     4               |     Terminator Power Characteristics     |
     5               +-------------+---------+---------+--------+
     6               |  Supply     |  4.75   |  5.25   | Volts  |
     7               |  Voltage    |         |         |        |
     8               |  (Vdd)      |         |         |        |
     9               +-------------+---------+---------+--------+
    10               |  TERMPWR    |  4.45   |  5.25   | Volts  |
    11               +-------------+---------+---------+--------+
    12               |  Source     |   74.2  |  87.5   |   mA   |
    13               |  Current    |         |         |        |
    14               |  per signal |         |         |        |
    15               +-------------+---------+---------+--------+
    16               |  Sink       |         |  -50    |   uA   |
    17               |  Current    |         |         |        |
    18               |  per signal |         |         |        |
    19               +-------------+---------+---------+--------+

    20               Table 6-3:  Terminator Power Characteristics

    21     6.2.5.1  Terminator Power Dissipation

    22     This is the power dissipated in the terminators per signal.   The
    23     power dissipated per signal in the terminator package is given in
    24     table 6-4.  The total power dissipated in the terminator  package
    25     depends on the number of signals asserted and deasserted.






















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     1               +-------------+---------+---------+--------+
     2               |  Parameter  |   Min   |   Max   |  Units |
     3               +-------------+---------+---------+--------+
     4               |  Terminator Power Dissipation            |
     5               +-------------+---------+---------+--------+
     6               | Power       |         |   213   |   mW   |
     7               | per asserted|         |         |        |
     8               | signal      |         |         |        |
     9               +-------------+---------+---------+--------+
    10               | Power       |         |    68   |   mW   |
    11               | per         |         |         |        |
    12               | deasserted  |         |         |        |
    13               | signal      |         |         |        |
    14               +-------------+---------+---------+--------+

    15                 Table 6-4:  Terminator Power Dissipation

    16     The power per  asserted  signal  is  calculated  at  the  maximum
    17     current of -87.5 mA.

    18                     2                 2
    19            Power = V / R = (5.25 Volts) / 120 Ohms = 230 mW


    20     The power per deasserted signal is  calculated  for  the  maximum
    21     voltage of 5.25 volts across the terminators.

    22                     2                  2
    23            Power = V / R = (5.25 volts) / (405 Ohms) = 68 mW


    24     6.2.5.2  Noise Margin

    25     As illustrated in figure 6-5, the noise  margin  is  the  voltage
    26     difference  between the appropriate receiver threshold and output
    27     voltage level, under worst case  load  conditions,  after  taking
    28     transmission  line  effects  into account.  For the DSSI bus, the
    29     worst case noise margin is  defined  as  the  voltage  difference
    30     between  the  deasserted output voltage level and the high-to-low
    31     receiver threshold voltage as shown in the  figure.   Appendix  J
    32     discusses the factors that influence this parameter.

    33     The worst case noise margin for the DSSI bus, as measured at  the
    34     transceiver inputs under worst case loading conditions, shall not
    35     be less that the minimum value specified in table 6-5.





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     1                    |\  /\/^--------------.                      
     2             _______|_\/__                |                      
     3         Worst   ^  |                     |                      
     4         Case    |  |                     |                      
     5         Noise   |  |                     |                      
     6         Margin  v  |  High-to-low        |                      
     7            --------|---------------------|------------ 2.1 Volts
     8                    |  Receiver threshold |                      
     9                    |                     |                      
    10                    |                     |                      
    11                    |  Low-to-high        |                      
    12            --------|---------------------|------------- .5 Volts
    13                    |  Receiver threshold | ^ Noise              
    14                    |                     | | Margin             
    15                    |                     | v                    
    16                    |                     |--------              
    17               _____|                     |/\/^----------------- 
                                                             

    18                Figure 6-5:  DSSI Noise Margin Definition


    19               +-------------+---------+---------+--------+
    20               |  Parameter  |   Min   |   Max   |  Units |
    21               +-------------+---------+---------+--------+
    22               |  Noise margin                            |
    23               +-------------+---------+---------+--------+
    24               |  Noise      |   0.5   |  1.51   | Volts  |
    25               |  Margin     |         |         |        |
    26               +-------------+---------+---------+--------+

    27                      Table 6-5:  DSSI Noise Margins

    28     6.3  PHYSICAL CHARACTERISTICS

    29     This section defines the physical  characteristics  of  the  DSSI
    30     bus,  including  such  factors as bus length, connector and cable
    31     part numbers, configuration rules, design  rules  and  rules  for
    32     connecting and disconnecting nodes from an operating bus.

    33     6.3.1  Maximum Length

    34     The  maximum  length  of  the  DSSI  cable  from  terminator   to
    35     terminator shall not exceed 6 meters.






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     1     6.3.2  STUB LENGTH

     2     The module  etch  from  the  driver/receivers  to  the  DSSI  bus
     3     connector  is referred to as the stub.  The stub length shall not
     4     exceed 10 cm.

     5     6.3.3  STUB SEPARATION

     6     The stub separation is  the  mimimum  distance  between  any  two
     7     devices on the DSSI bus.  The mimimum stub separation is 6".

     8     6.3.4  MODULE ETCH REQUIREMENTS

     9     The stub should have a characteristic impedance of no  less  than
    10     70 ohms with capacitance per foot equal to 24pf +/- 10%.

    11     6.3.5  INTERNAL CONNECTOR REQUIREMENTS

    12     All internal connectors shall be  non-shielded.   The  unshielded
    13     connector pin assignments are listed in table 6-6.

    14     6.3.5.1  Device Connectors

    15     Device connectors shall be 50 pin, center keyed,  and  latchable.
    16     They  shall consist of two (2) rows of 25 male pins with adjacent
    17     pins  2.54mm   (.10in)   apart.    Refer   to   the   engineering
    18     specifications  for DEC PN 12-16832-03 (3 wall) or 12-21545-03 (4
    19     wall) for details.

    20     The 4  wall  connector  (12-21545-03)  shall  be  used  when  the
    21     connector  is  positioned  in adherence with DEC STD 030.  If the
    22     connector is positioned so that the  male  pins  extend  off  the
    23     module  edge then the 3 wall connector (12-16832-03) may be used.
    24     The device connectors shall be mounted on the component  side  of
    25     the module.

    26     6.3.5.1.1  Female Cable Connector

    27     The female cable connector shall have 50 pins, configured as 2x25
    28     female  contacts  2.54mm  (.10in)  apart.  The connector shall be
    29     center keyed and  strain  relieved.   Refer  to  the  engineering
    30     specification for DEC PN 12-23995-05 for details.








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     1     6.3.5.1.2  Male Cable Connector

     2     The male cable connector shall have 50 male  pins  2x25  contacts
     3     2.54mm (.10in) apart.  Refer to DEC PN (TBD) Engineering spec for
     4     details.

     5     6.3.6  INTERNAL CABLE REQUIREMENTS

     6     To minimize discontinuities and  signal  reflections,  cables  of
     7     different  impedances  shall  not  be  used on the same bus.  The
     8     internal cable can be round or flat but shall have the  following
     9     basic characteristics:

    10          1.  28 AWG

    11          2.  50 conductor (25 twisted pair for round cable)

    12          3.  Outside Diameter less than .3 inch for round cable

    13          4.  100 +/- 10% ohm characteristic impedance

    14          5.  .065 ohms per foot resistance


    15     For   cable   characteristics,   refer   to    the    engineering
    16     specifications for the following DEC part numbers:

    17          1.  Flat cable - 91-07738-02.

    18          2.  In-cabinet Round cable - 17-01901-01.


    19     6.3.7  EXTERNAL CONNECTOR REQUIREMENTS

    20     360  degree  shielded  connectors  shall  be  used  for  external
    21     applications   where   electromagnetic  compatibility  (EMC)  and
    22     electrostatic discharge (ESD) protection  are  required.Refer  to
    23     DEC PN (TBD) Engineering spec for details.

    24     6.3.8  EXTERNAL CABLE REQUIREMENTS

    25     The external cable shall be 25 twisted pair,  28  AWG,  shielded,
    26     with  a  characteristic  impedance  of  80  ohms.   Refer  to the
    27     engineeering specification for DEC PN 17-01901-01 for details.






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     1      Pin Number      Signal Name        Pin Number      Signal Name
     2      ----------      -----------        ----------      -----------
                                                                          
     3          1            DATA<0> L            26            TERMPWR   
     4          2            GND                  27            TERMPWR   
     5          3            DATA<1> L            28            TERMPWR   
     6          4            GND                  29            GND       
     7          5            DATA<2> L            30            Reserved  
     8          6            GND                  31            GND       
     9          7            DATA<3> L            32            Reserved  
    10          8            GND                  33            GND       
    11          9            DATA<4> L            34            Reserved  
    12         10            GND                  35            GND       
    13         11            DATA<5> L            36            BSY L     
    14         12            GND                  37            GND       
    15         13            DATA<6> L            38            ACK L     
    16         14            GND                  39            GND       
    17         15            DATA<7> L            40            RST L     
    18         16            GND                  41            GND       
    19         17            PARITY L             42            Reserved  
    20         18            GND                  43            GND       
    21         19            Reserved             44            SEL L     
    22         20            GND                  45            GND       
    23         21            Reserved             46            C/D L     
    24         22            GND                  47            GND       
    25         23            TERMPWR              48            REQ L     
    26         24            TERMPWR              49            GND       
    27         25            TERMPWR              50            I/O L     
                                                                           

    28                   Table 6-6:  DSSI Signal Assignments

    29     6.3.9  Connecting And Disconnecting A Device From The DSSI Bus

    30     The following  sections  describe  the  design  requirements  for
    31     connecting  and disconnecting a node to the bus without damage to
    32     components.

    33     6.3.9.1  Hot Swap Prohibited

    34     Hot-swap is the act of disconnecting or connecting a DSSI node to
    35     the  bus  while  node  power  is  on  and  the  DSSI system is in
    36     operation.  The ability to perform a hot-swap without harm to any
    37     component  in  a  running  system  is  not  supported by the DSSI
    38     architecture.  Hot-swap shall not be allowed on any DSSI system.





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     1     6.3.9.2  Power Supply Requirements

     2     The power supplies for DSSI devices shall present an impedance of
     3     1k Ohm or less during the power-down/power-up sequences and while
     4     powered off.

     5     6.3.9.3  Mechanical Requirements

     6     This section discusses the following mechanical requirements  for
     7     safely connecting and disconnecting a DSSI device:

     8          1.  Printed circuit board wiring and layout rules,

     9          2.  Grounding of multi-cabinet systems,

    10          3.  Proper  sequencing  of  DSSI  pins  when  connecting  or
    11              disconnectiong a device from the bus.


    12     6.3.9.3.1  Printed Circuit Board Wiring And Layout Rules

    13     All DSSI devices shall include a solid ground plane, which  shall
    14     be  directly  connected to the logic ground provided by the power
    15     supply.  All GROUND pins of the DSSI connector shall contact  the
    16     ground plane directly.

    17     When using the DXX transceivers ( see  engineering  specification
    18     \TBS\  )  The  VSS,  IOVSS,  QVSS1,  and  QVSS2 connections shall
    19     directly contact the ground plane.

    20     6.3.9.3.2  Ground Connection

    21     System configurations that use several power supplies within  one
    22     cabinet  or  in an expansion cabinet should include ground straps
    23     connecting the chassis ground of each power supply to the chassis
    24     ground of each cabinet.

    25     It is recognized that for systems that are far  apart,  grounding
    26     in  this  manner  could be impractical.  In this case, compliance
    27     with with the requirements of section 6.3.9.3.3 is essential.

    28     6.3.9.3.3  Pin Sequencing

    29     The design of cables, connnectors  and  other  related  hardware,
    30     when  supplemented with the appropriate user documentation, shall
    31     implement the following rules for connecting or disconnectiong  a
    32     device from the DSSI bus.



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     1     To connect a node to the bus,  node  power  shall  be  off.   The
     2     design  of  connectors  and  receptacles  shall  cause  DSSI  bus
     3     connections to be made in the following order:

     4          1.  The connector shield,

     5          2.  The DSSI GROUND pins,

     6          3.  DSSI signal-carrying pins.


     7     Upon applying power to the device, the device shall issue  a  bus
     8     RESET.

     9     To disconnect a node from the bus, node power shall be off.   The
    10     design of cables, connectors and receptacles shall cause DSSI bus
    11     connections to be terminated in  the  following  order  when  the
    12     connector is removed:

    13           o  DSSI signal-carrying pins,

    14           o  DSSI GROUND pins,

    15           o  The connector shield.


























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     1                                APPENDIX A

     2               FAIR ARBITRATION ALGORITHM TIMING PARAMETERS


     3     The basic concept used in the  "Fair  Arbitration"  algorithm  is
     4     that  DSSI nodes can be enabled or disabled.  An enabled node may
     5     participate in arbitration  if  it  has  a  message  to  send,  a
     6     disabled node may not.  The normal sequence of events starts with
     7     all nodes enabled.  Each node in turn wins arbitration,  sends  a
     8     message, and disables itself.  Eventually all nodes are disabled,
     9     resulting in the DSSI bus becoming idle.  All the nodes recognize
    10     that  the  bus  is idle (BSY and SEL both false for a long enough
    11     time) and re-enable themselves.

    12     In addition to the bus parameters specified in the fixed priority
    13     arbitration scheme ( section H.2.1), it is necessary to specify a
    14     maximum delay for DSSI nodes to assert BSY  and  their  DSSI  ID.
    15     This delay is necessary to make the fair arbitration scheme work.
    16     "Fair arbitration" basically means round-robin among those  nodes
    17     that are participating in arbitration.

    18     All nodes participating in arbitration must assert BSY and  their
    19     DSSI  ID  within a reasonable time period in order to ensure that
    20     they are visible to other nodes.

    21     In order to derive the fair arbitration  timings  and  show  that
    22     they  work,  some  assumptions  or requirements about some timing
    23     parameters  for  the  DSSI  bus  and  nodes  are  required.   The
    24     parameters needed and their assumed values are:


    25          1.  DSSI Cable Delay [200ns].   The  maximum  or  worst-case
    26              time for a signal to propagate from the driver output of
    27              one DSSI node to the receiver input of  any  other  DSSI
    28              node.

    29          2.  DSSI  Arbitration  Skew  Delay  [600ns].   The   maximum
    30              allowable  skew  for  a  DSSI node to assert BSY and its
    31              DSSI ID during arbitration.

    32          3.  DSSI Idle Delay [2200ns].  The minimum time a DSSI  node
    33              must  wait  before  concluding that no enabled nodes are
    34              arbitrating for the bus.






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     1          4.  The value for DSSI Bus Delay is based on  Pete  Mclean's
     2              SCSI  timing  analysis  dated  4-Dec-1984,  which gave a
     3              propagation delay for a DEC SCSI cable  of  1.75ns/foot.
     4              This  works out to a delay of 143.5ns for 25 meters, and
     5              rounding up to 200ns leaves a safety margin.

     6          5.  The value for DSSI  Arbitration  Skew  Delay  represents
     7              approximately  200ns  skew for synchronizing a signal to
     8              the node's internal clock, 200ns skew for logic  delays,
     9              and   200ns   for  logic  decision  time  to  arbitrate.
    10              Assuming a receiver delay of 65ns,  a  driver  delay  of
    11              70ns  (these values are quoted on a preliminary NCR data
    12              sheet for SCSI driver and receiver), and adding internal
    13              logic delays, gives somewhat less than 200ns total logic
    14              delays.   If  the  node  drives  its  arbitration  state
    15              machine  off  a  200ns clock, a bit more than 200ns skew
    16              will result from clock synchronization (200ns skew,  not
    17              total  synchronizer  delay).  Thus this figure should be
    18              attainable for any node that uses a 200ns clock for  its
    19              arbitration  state  machine, and trivial for a node that
    20              uses a faster clock.

    21          6.  DSSI Arbitration Skew Delay specifies the maximum  delay
    22              for an enabled node to assert BSY and its DSSI ID during
    23              arbitration.  This means that  Step  (3)  of  the  fixed
    24              priority  arbitration  algorithm  described  in  section
    25              H.2.1 gets replaced by the following:

    26        (3) Following the bus free  delay  [800ns]  in  Step  (2),  an
    27        enabled  DSSI device that wishes to arbitrate for the DSSI bus
    28        shall assert both BSY and  its  own  DSSI  ID  within  a  DSSI
    29        Arbitration  Skew  Delay  [600ns].   The DSSI device shall not
    30        arbitrate (i.e.  assert BSY and its DSSI ID) if  more  than  a
    31        bus  free  delay  [800ns]  plus  a DSSI Arbitration Skew Delay
    32        [600ns]  have  passed  since  the  BUS  FREE  phase  was  last
    33        observed.

    34     From the above information, the  DSSI  Idle  delay  needs  to  be
    35     calculated.   That  is,  if  the  DSSI bus is currently busy, and
    36     there is an enabled DSSI device that wishes to arbitrate for  the
    37     DSSI  bus, the maximum time that any other device on that bus may
    38     see BSY and SEL both false need to be calculated.  The worst case
    39     occurs  when the other device instantaneously sees BSY and/or SEL
    40     become false when they are  released  by  the  old  device.   The
    41     maximum  time for the other device to see BSY asserted by the new
    42     device is the sum of:




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     1          [ 200ns]  DSSI Cable Delay from old device to new device   
     2          [ 400ns]  Bus Settle Delay for new device to have BUS FREE 
     3          [ 800ns]  Bus Free Delay before new device may assert BSY  
     4          [ 600ns]  DSSI Arbitration Skew Delay before new device    
     5                    must assert busy                                 
     6          [ 200ns]  DSSI Cable Delay from new device to other device 
     7     or a total of 2200ns for DSSI Idle Delay.   It  should  be  noted
     8     that the DSSI Arbitration Skew Delay accounts for any skew in the
     9     new device recognizing BUS FREE.

    10     This means that a device may conclude the DSSI bus is idle if  it
    11     sees  both BSY and SEL false for a minimum of the DSSI Idle Delay
    12     [2200ns].  In order for all devices to conclude that the  bus  is
    13     idle,  BSY  and  SEL  must both remain false for a minimum of the
    14     DSSI Idle Delay [2200ns]  plus  a  DSSI  Arbitration  Skew  Delay
    15     [600ns].


































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           SII                                                      Page B-1
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     1                                APPENDIX B

     2                                    SII






















     3                       [ Deleted in version 1.0.0 ]
























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           DSSI PARAMETER VALUES                                    Page C-1
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     1                                APPENDIX C

     2                           DSSI PARAMETER VALUES


     3     This appendix is a  compilation  of  numeric  parameters  defined
     4     elsewhere in this document.


     5                   Table C-1:  DSSI General Parameters

     6       +--------------------+--------------------------------------+
     7       |       Value        |                                      |
     8       |------+------+------+           Description                |
     9       | Dec. | Oct. | Hex. |                                      |
    10       +------+------+------+--------------------------------------+
    11       | Allowed REQ/ACK Offset Values                             |
    12       |   3  |  03  |  03  | REQ/ACK offset (minimum)             |
    13       |   7  |  07  |  07  | REQ/ACK offset                       |
    14       |  15  |  17  |  0F  | REQ/ACK offset (maximum)             |
    15       |      |      |      |                                      |
    16       | DSSI Command Out Format                                   |
    17       | 224  | 340  |  E0  | Data Link Operation Code             |
    18       |      |      |      |                                      |
    19       | DSSI Status In Format                                     |
    20       |  97  | 141  |  61  | ACK                                  |
    21       |  30  | 036  |  1E  | NAK                                  |
    22       +------+------+------+--------------------------------------+

    23               Table C-2:  Selected DSSI Timing Parameters

    24       +-------------------------------------------+---------------+
    25       |             Description                   |   Value       |
    26       +-------------------------------------------+---------------+
    27       |  Initiator Timeout                        | 2800us        |
    28       |  Selection Abort Timeout ( minimum )      |   20us        |
    29       |  Selection Abort Timeout ( maximum        |   30us        |
    30       |  Selection Timeout ( minimum )            |   20us        |
    31       |  Selection Timeout ( maximum )            |   30us        |
    32       |  Target Timeout                           | 2400us        |
    33       +-------------------------------------------+---------------+









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           IMPLEMENTATION FUNCTIONALITY                             Page D-1
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     1                                APPENDIX D

     2                       IMPLEMENTATION FUNCTIONALITY


     3     This appendix lists parameter values and describes  the  behavior
     4     of  existing  DSSI  products  in  areas  where  the specification
     5     permits implementation-specific choices.

     6     The behavioral descriptions are for information only.   In  cases
     7     where  a  choice  is  allowed  and  the specification expresses a
     8     preference, new implementations shall comply with  the  preferred
     9     behavior   unless   precluded   from   doing   so  by  overriding
    10     considerations.

    11     D.1  Section 5.5.8.1 "Data Block Length"

    12     The referenced section specifies DSSI datalink  requirements  for
    13     receiving  and  buffering  packets  received  during the DATA OUT
    14     phase.

    15     As described in the referenced section, DSSI  targets  should  be
    16     able  to  safely  receive and buffer the maximum packet size that
    17     can be specified in the Command Descriptor block ( 8191 bytes  ).
    18     Packets  longer than the upper limited expected by a higher layer
    19     are to be truncated  and  forwarded  with  notification  that  an
    20     oversize packet was received.

    21     Due to implementation-specific constrains, DSSI products are  not
    22     able  to  conform  to this recommended behavior.  The behavior of
    23     existing implementations is described in the following sections.


    24     D.1.1  SWIFT And SII


    25     SWIFT and SII are low-cost, single-chip implementations  of  DSSI
    26     datalink Channel Control functions.  Both must be supplemented by
    27     an  attached  processor  and  memory  to  provide  full  CI  Port
    28     functionality.   SWIFT is a second generation replacement for SII
    29     that provides enhanced detection of memory  errors  and  CI  port
    30     layer assists to offload the processor.

    31     The hardware will receive datalink packets up to  8190  bytes  in
    32     length  directly  into hardware-managed buffer queues The maximum
    33     effective size, which determines the size of each queue entry, is
    34     negotiated  between  the  sender and receiver through the CI port



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     1     protocol and is less than the upper datalink limit.  The hardware
     2     has  no  way  to  prevent buffer overflow due to a packet that is
     3     longer  than  this  negotiated  size.   However,  SWIFT's   added
     4     capabilities   facilitate   the   detection   of   such  overflow
     5     occurrances.

     6     The  response  to  overflow  is  implementation-specific.    DSSI
     7     devices  may  invoke  crash  recovery  code when such an event is
     8     detected.  A DSSI host, on the other hand, may attempt a graceful
     9     recovery by terminating all virtual circuits serviced through the
    10     host adapter.

    11     D.1.2  SHAC And DASH

    12     As described in section 5.5.8.1, "Data Block  Length",  SHAC  and
    13     DASH check the length in the Command Descriptor block against the
    14     maximum allowed size of a CI port layer packet  body  ( specified
    15     in  the  MAX_BODY_LEN  field of a CI port layer ID packet ).  The
    16     transfer is terminated with a  NAK  STATUS IN  value  before  the
    17     start  of  the  DATA OUT  phase  if  the length exceeds the above
    18     limit.

    19     D.2  Table 5-2, "Summary Of Channel Control Layer Status Values"

    20     The status values, returned by  SHAC  and  DASH  Channel  Control
    21     layer  implementations  differ from the values summarized in this
    22     table.  SHAC and DASH return CC_NORSP For the  following  events,
    23     instead  of CC_NAK, as called out in the table, for the following
    24     cases:





















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           Table 5-2, "Summary Of Channel Control Layer St ... 27 March 1990


     1     Condition             Section/Page
     2     ---------             ------------

     3     Invalid information   Section 5.5.7.4,
     4     transer phase.        page 5-27,                        

     5     Inititiator           Section 5.5.7.4,
     6     Timeout.              5-27.

     7     "Third Party"         Section 5.5.7.4,
     8     bus reset.            page 5-27.

     9     Phase other than      Section 5.5.8.4,
    10     BUS FREE following    page 5-37.
    11     STATUS IN.

    12        Table D-1:  SHAC/DASH Differences in Channel Control  Layer
    13                    Status

    14     D.3  CI Port Maintenance I/D's

    15     The following is a tabulation of CI  Port  maintenance  I/Ds  for
    16     DSSI  products.  This list is provided for information only.  The
    17     assignment of official maintenance I/Ds  for  products  that  are
    18     compatible  with  the  CI  port  shall  be  done  through  the CI
    19     Architect.

    20                 Product                     Maintance I/D
    21                 -------                     -------------
    22                  KFQSA                          21h      
    23                  SHAC                           22h      
    24                  DASH                           24h      
    25                  RF71                           30h      
    26                  RF30                           31h      
    27                  RF31                           32h      
    28                  TF70                           40h      
    29                  TF85                           41h      
    30                  MF2                            20h      


    31                   Table D-2:  CI Port Maintenance I/Ds









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           USE OF CREDITS IN SCA/MSCP SPECIFICATIONS                Page E-1
                                                               27 March 1990


     1                                APPENDIX E

     2                 USE OF CREDITS IN SCA/MSCP SPECIFICATIONS


     3     This section is intended to clarify the use of  credits  in  SCA,
     4     CI, and MSCP architecture specifications.

     5     SCA provides credit  based  flow  control  for  each  connection.
     6     Whenever  a  connection  exists,  each side has some non-negative
     7     number  of  credits,  termed  a  credit  balance.   Credits   are
     8     initially  established  when  the  connection  is formed, and all
     9     credits disappear when a connection terminates.

    10     In any node or system, there will be a queue  of  things  waiting
    11     for credits and a queue of things that have credits waiting to be
    12     transmitted.  Depending on how the system is structured, the  two
    13     queues can be anywhere.

    14     About the only consistent rule is that the queue of  things  that
    15     have  credits  will  be at a lower layer than the queue of things
    16     waiting for credits.  In VMS the  queue  of  things  waiting  for
    17     credits  is  maintained  at  the interface between the MSCP/TMSCP
    18     server (SYSAP) layer and the SCS layer.  The important  thing  is
    19     that  items  in this queue are waiting for credits, not where the
    20     queue resides.  Plus, from the perspective of MSCP  or  TMSCP,  a
    21     command is completed when its end message is placed in this queue
    22     --- the server does not have to wait for a credit  to  arrive  to
    23     consider the command complete.

    24     In SII, the queue of things waiting at  the  SII  transmit  queue
    25     already have credits.  The SII transmit queue represents deferral
    26     queue at the data link layer.  However, deferral queues  used  to
    27     hold packets awaiting transmission retries, and port layer queues
    28     in the Port Queue Block are all equivalent.  The important  thing
    29     is  that  items  on  all  of  these  queues already have whatever
    30     credits they need, and are waiting for access to the transmission
    31     media.

    32     MSCP, TMSCP, and DUP class drivers (hosts) use  credits  to  send
    33     commands  to  servers.  This is described in the MSCP Spec and is
    34     not particularly unique or interesting in either SCA or DSSI.

    35     MSCP, TMSCP, and DUP servers require credits to:






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           USE OF CREDITS IN SCA/MSCP SPECIFICATIONS                Page E-2
                                                               27 March 1990


     1          1.  Send an end message.

     2          2.  Send an attention message.

     3          3.  Send a DATREQn packet.

     4          4.  Send a sequence of SNTDAT packets with a new transaction
     5              ID  (XCTID).   The  Last  Packet flag will be set in the
     6              last SNTDAT packet and will mark the  end  of  a  SNTDAT
     7              sequence  that  use  the same XCTID.  It should be noted
     8              that one credit is required for sending the first SNTDAT
     9              packet  with  a  new  XCTID.   All the subsequent SNTDAT
    10              packets  that  use  the  same  XCTID  do   not   require
    11              additional  credits.   A  credit  is  returned  when the
    12              server receives CNF packet from remote node.


    13     Servers may only send these messages when their credit balance is
    14     greater  than  zero.   The  act  of sending one of these messages
    15     decreases the server's credit balance by one.   In  this  context
    16     "send"  means  that  the message has been queued to the Data Link
    17     layer for transmission.  It does not mean that  the  message  has
    18     been  queued  to the Transport (Port) or Session (SCA) layer, and
    19     will be transmitted once sufficient credits arrive (it should  be
    20     noted  that "send" is used with this latter meaning in some parts
    21     of the MSCP Spec).

    22     MSCP, TMSCP, and DUP servers obtain credits by:

    23          1.  Receiving  a   Connect   request   and   accepting   the
    24              connection.

    25          2.  Receiving a Credit request.

    26          3.  Receiving an SCA Application Message.

    27          4.  Receiving a RETDAT packet with the Last Packet flag set.

    28          5.  Receiving a CNF packet.


    29     The first three of these contain a credit field,  which  contains
    30     the  number  of  credits  granted.  Strictly speaking, the server
    31     only obtains credits if it receives one of these messages with  a
    32     non-zero positive credit field.  The RETDAT and CNF packets grant
    33     exactly one credit.  The server  must  supply  a  transaction  ID
    34     field  in  DATREQn and SNTDAT packets that allows it to determine



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           USE OF CREDITS IN SCA/MSCP SPECIFICATIONS                Page E-3
                                                               27 March 1990


     1     the corresponding connection when it receives  a  RETDAT  or  CNF
     2     packet.

     3     The SCA Spec and the above description  are  written  as  if  the
     4     server  kept  a  single pool of credits for each connection.  All
     5     credits are the same, and the server checks (and decrements)  the
     6     credit balance immediately before sending each message or packet.
     7     Such an implementation maximizes flexibility, and is preferred in
     8     the absence of other criteria.  However, it is not the only valid
     9     implementation.

    10     VMS  implementation  follows  the  above  "full"  dynamic  credit
    11     management.    It   maintains   a  single  pool  of  credits  per
    12     connection, and will not allow  a  SYSAP  to  send  any  sequence
    13     message  packets  (SNDMSG,  REQDAT,  SNDDAT) if there are no send
    14     credits available.  Such messages will be held by  the  transport
    15     layer  (SCS  layer) until a send credit is available.  While such
    16     an implementation is preferable due to it's inherent flexibility,
    17     and  generality, there can be reasons for being less flexible and
    18     pre-allocating credits.  For example, if  the  cost  of  checking
    19     credits  at the time a packet is about to be sent is substantial,
    20     pre-allocating credits can eliminate the cost.  HSC uses such  an
    21     approach.

    22     MSCP, TMSCP, and DUP servers may maintain  independent  pools  of
    23     credits  for different purposes on a single connection.  That is,
    24     servers  may  pre-allocate  credits  to   a   specific   purpose,
    25     presumably to optimize performance.

    26     A good example is the HSC's use of credits.

    27     The HSC maintains four distinct, separate pools of  credits,  one
    28     for  each  class  of  messages.   A single credit is reserved for
    29     SNTDAT packets with the Last Packet flag.   Similarly,  a  single
    30     credit   is  reserved  for  each  outstanding  command  for  that
    31     command's end message.  A pool of DMA credits is used for DATREQn
    32     packets,  and  a  pool  of  excess  credits is used for attention
    33     messages.

    34     The HSC requires a minimum of three  initial  credits  with  each
    35     Connect  request.   One  is the SNTDAT credit, one is for the DMA
    36     credit  (DATREQn)  pool,  and  one  is  for  the  excess   credit
    37     (attention message) pool.  Additional initial credits are divided
    38     between the DMA and excess credit pools.






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           USE OF CREDITS IN SCA/MSCP SPECIFICATIONS                Page E-4
                                                               27 March 1990


     1     The HSC requires that each SCA Application Message (MSCP or TMSCP
     2     command)  grant  a  minimum  of  one  credit.  This is the credit
     3     reserved for the command's end message.  Any  additional  credits
     4     beyond  one  are  added  to  the excess credit pool for attention
     5     messages.  Similarly, any credits granted by Credit requests  are
     6     also added to the excess credit pool.

     7     In effect, the HSC only dynamically manages credits for attention
     8     messages.    All   other   uses  have  their  credits  statically
     9     pre-allocated.

    10     Now the HSC's example, while illustrative, may NOT be followed by
    11     DSSI devices.  It will, of course, work perfectly well with ports
    12     such as SHAC and Mayfair II that provide a  direct  interface  to
    13     the  host  class driver.  However, the HSC's scheme will not work
    14     with the KFQSA.

    15     The problem is that UQSSP does not require host class drivers  to
    16     explicitly  report  credits  to  the port, controller, or server.
    17     Thus the KFQSA cannot determine how many  credits  the  host  has
    18     granted  the  server.   In particular, the KFQSA cannot determine
    19     when the host grants excess credits for attention messages.  Thus
    20     DSSI  devices  may  statically  pre-allocate  the initial credits
    21     granted by the Connect request, in particular for  data  transfer
    22     operations,   but  must  dynamically  allocate  credits  for  end
    23     messages and attention messages.

    24     E.1  DSSI Device Credit Management

    25     The following  guidelines  describe  the  DSSI  devices'  use  of
    26     credits.   It  should  be  noted  that  these rules only apply to
    27     connections that use the MSCP and TMSCP protocols.

    28          1.  Class drivers shall  provide  a  minimum  of  3  initial
    29              credits  with  the  Connect  request  for MSCP and TMSCP
    30              connections.  Class drivers  should  specify  2  in  the
    31              min_credit field of the Connect request.

    32          2.  Servers shall set the min_credit  field  of  the  Accept
    33              request  to  the minimum number of credits needed by the
    34              server.

    35          3.  Servers shall use a  single  pool  of  credits  for  end
    36              messages  and  attention  messages.  DATREQn packets and
    37              SNTDAT packets may share  this  credit  pool  (for  full
    38              dynamic   credit  management),  share  a  separate  data
    39              transfer credit pool, or have separate credit pools  for



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           USE OF CREDITS IN SCA/MSCP SPECIFICATIONS                Page E-5
           DSSI Device Credit Management                       27 March 1990


     1              each type of data transfer.

     2          4.  Servers shall allocate at least one  initial  credit  to
     3              each  of  the  end/attention  message  pool, the DATREQn
     4              pool, and the SNTDAT pool.  If the server has fewer than
     5              three  pools,  due  to  sharing  one  pool  for  several
     6              purposes, then it shall allocate at  least  one  initial
     7              credit to each pool.  Additional initial credits, beyond
     8              the number of server credit pools, may be  allocated  in
     9              whatever manner the server desires.

    10          5.  Servers  shall  provide  full  functionality  with   the
    11              minimum  3  initial  credits.  However, they may require
    12              more credits to achieve full performance and in order to
    13              have multiple data transfer operations outstanding.

    14          6.  In general, DSSI servers should provide full performance
    15              with  5  initial  credits.   This is 3 credits for block
    16              data transfer operations, and 2  credits  for  messages.
    17              Any  DSSI  device  that  requires  more  that  5 initial
    18              credits to achieve full performance  should  prominently
    19              advertise  and  review  their  design  with  other  DSSI
    20              implementors and host operating systems.

    21          7.  DSSI servers  cannot  assume  that  class  drivers  will
    22              follow  the  rules  described  in  Chapter 3 of the MSCP
    23              specification.

    24              In particular, servers must operate normally  even  when
    25              they have fewer credits than outstanding commands.  This
    26              means that servers must check for  and  properly  handle
    27              the  case where a command completes, so they have an end
    28              message to send, but do not have a credit  available  to
    29              send the end message.  The server must queue the command
    30              and send it when the class  driver  provides  sufficient
    31              credits.    This  queue  effectively  lies  between  the
    32              MSCP/TMSCP server and SCS layers.  Queued messages  must
    33              be  sent  in  the  same order that they were queued.  In
    34              terms of "Command Categories and  Execution  Order",  an
    35              MSCP  or TMSCP command is completed when the end message
    36              is placed on this queue.

    37          8.  DSSI servers must ensure that attention messages do  not
    38              lockout end messages and data transfer operations.  That
    39              is, they must ensure  that  attention  message  are  not
    40              continuously   sent   while  end  messages  and/or  data
    41              transfer operations are waiting for credits.  One  means



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           USE OF CREDITS IN SCA/MSCP SPECIFICATIONS                Page E-6
           DSSI Device Credit Management                       27 March 1990


     1              of  achieving  this,  described  in the MSCP Spec, is to
     2              limit the rate at which attention messages are generated
     3              to  no  more  than  two  attention  messages per second,
     4              averaged over the controller timeout interval.   Another
     5              (preferable)   means   is  to  only  generate  attention
     6              messages when credits are available to immediately  send
     7              them.

     8          9.  When messages of various types are waiting for  credits,
     9              and  the  server receives some credits, the following is
    10              the recommended  order  in  which  the  new  credits  be
    11              utilized:

    12              1.  First, use the credits for any  messages  (primarily
    13                  end  messages)  queued  between  the  server and SCS
    14                  layers.

    15              2.  Next, use the credits to initiate any  pending  data
    16                  transfer   operations.    In  general,  give  SNTDAT
    17                  operations priority over REQDATn operations.

    18              3.  Finally, use the credits  to  generate  any  pending
    19                  attention messages.



    20     These are guidelines, not requirements  ---  they  will  tend  to
    21     maximize  performance.   Only servers that implement full dynamic
    22     credit management will be able to follow all of them.

    23     The guidelines for DUP connections  are  similar,  but  with  two
    24     differences.

    25     First, DUP does not  have  attention  messages,  so  the  initial
    26     credit  for  attention messages need not be provided.  Second, it
    27     is reasonable to use DUP without data transfer  operations.   So,
    28     if  the class driver knows that it will never issue a DUP command
    29     that contains a buffer descriptor, it  may  supply  zero  initial
    30     credits  in  the  Connect  request.   Otherwise, the class driver
    31     shall provide  at  least  two  initial  credits  in  the  Connect
    32     request.   If the class driver supplies zero initial credits, and
    33     subsequently issues a command that contains a buffer  descriptor,
    34     the  DUP  server  may  either honor the command (if it implements
    35     full dynamic credit management) or break the VC.






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           USE OF CREDITS IN SCA/MSCP SPECIFICATIONS                Page E-7
           DSSI Device Credit Management                       27 March 1990


     1     SCS$DIRECTORY uses neither attention messages nor  data  transfer
     2     operations,  and  thus  can  be  implemented  with  zero  initial
     3     credits.















































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                                                               27 March 1990


     1                                APPENDIX F

     2                        SCA AND MSCP CLARIFICATIONS


     3     F.1  SCA Additions And/or Clarifications

     4     This section attempts to clarify or amend sections of the various
     5     SCA documents.

     6     F.2  Format Of  Buffer  Descriptors  And  Use  In  SNTDAT/DATREQn
     7          Packets

     8     DSSI drives  must  support  both  the  CI  Port  and  SSP  buffer
     9     descriptor  formats.   The  reason  for  this  is  that  the data
    10     transfer commands received by a drive may be  from  an  SSP  type
    11     host  interface  (KFQSA),  or  CI Port type host interface( SHAC,
    12     MAYFAIR Port,  DASH)  etc.   Thus  the  buffer  descriptors  they
    13     receive  as part of the transfer commands may be in either of the
    14     following two formats.

    15          1.  SSP   Unmapped   Buffer   Descriptor   Format   -    SSP
    16              Specification,  Ref  [7].   Host  adapters with SSP type
    17              host  interface  (KFQSA)  must  ensure  that  the  third
    18              longword  of  the  buffer  descriptor  is either a valid
    19              Connection ID, or a zero.

    20          2.  CI  Port  Buffer  Descriptor  Format  -  VAX11-CI   Port
    21              Architecture Specification, Ref [6].


    22     F.3  Port And VC Concepts

    23     Similar to a CI node, a DSSI node may be in any of the six global
    24     states:   Uninitialized,  Disabled,  Enabled,  with  and  without
    25     maintenance functions enabled.

    26     The CI Specification (Pages 70-71, Ref [5]), describes the  above
    27     states  and their state transitions.  It should be noted that all
    28     the six states are not required to be implemented in a node.  The
    29     Uninitialized/Maintenance  state  must be implemented if the node
    30     RESET and START functions are supported.

    31     The other /Maintenance states are optional.






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     1     It should be remembered that the normal operational  state  of  a
     2     node  is  either  ENABLED  (if the node does not require external
     3     reset from another DSSI node) or ENABLED/MAINTENANCE (if the node
     4     supports  external  reset  from  another  DSSI node); the virtual
     5     circuit services (message,  datagram,  and  block  data  transfer
     6     services) are provided by a node only in these two states.

     7     F.3.1  Example Port State Diagram In DSSI Drives

     8     The state diagram of figure F-1 illustrates the minimum  required
     9     port states that must be supported by RFxx and TFxx products.  In
    10     addition, it is suggested that as many diagnostics as possible be
    11     run in response to a received RST.

    12                      `Power up'
    13                           |
    14                           V
    15                   .---------------.
    16          .--------| Uninitialized |
    17          |        `---------------'
    18          |diags      
    19          |passed  .------------------------.          .-------.
    20          |        |         STRT           |          |  RST  |
    21          V        V                        |          V       |
    22     .---------------.      RST      .---------------------.   |
    23     | Enabled/Maint |-------------->| Uninitialized/Maint |---'
    24     `---------------'               `---------------------'


    25          Figure F-1:  Minimum Port State Diagram in DSSI Drives

    26     F.3.1.1  Uninitialzed State

    27     In this state the node does not send/receive  any  packets.   The
    28     datalink  interface  will  either  return  failure status (NAK or
    29     NO_RSP), or will not respond to selections on the DSSI Bus.

    30     F.3.1.2  Uninitialized/Maint State

    31     In this state the datalink will acknowledge any received packets.
    32     ID  packets  will be returned in response to IDREQ packets.  This
    33     state is further explained in Sec 5.4, Page 72, DEC STD 161.








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           Port And VC Concepts                                27 March 1990


     1     F.3.1.3  Enabled/Maint State

     2     This  is  the  normal  operating  state  for  DSSI  drives,   and
     3     communication  services  for the higher layers are supported only
     4     in this state.

     5     F.4  Generation Of Unique Node Parameters

     6     Two parameters  types  need  to  be  differentiated  in  a  node;
     7     critical   parameters   and  non-critical  parameters.   All  the
     8     parameters required to communicate with a DSSI node,  even  in  a
     9     minimum  configuration, are critical parameters and the remaining
    10     parameters are non-critical.  Non-critical parameters  that  have
    11     to  be  saved  across  power  failures are stored in non-volatile
    12     memory and altered via a suitable diagnostic program (for example
    13     via  DUP  in  DSSI drives).  Critical parameters are set to their
    14     default values on powerup (or on node reset), and changes made to
    15     them after powerup are volatile.  The reason for this approach is
    16     that  many  DSSI  drives  do  not  have  a  management  interface
    17     (separate console interface), and a guaranteed communication path
    18     is required to change any parameters stored in  a  semi-permanent
    19     medium such as NVRAM.

    20     Critical parameters should not be  stored  in  NVRAM,  since  any
    21     inadvertent,  or  erroneous  changes  to  the  NVRAM  may prevent
    22     further  communication  with  the  drive.   While  most  of   the
    23     parameter  definitions  and their significance are node specific,
    24     the  parameters  described  in   this   section   are   mandatory
    25     requirements in every DSSI node.

    26     F.4.1  SCA And MSCP Parameters

    27     The SCA and MSCP architectures require that certain parameters be
    28     unique  across  a  shared  bus.  DSSI implementations that do not
    29     have a stand-alone maintenance interface ( e.g.; most DSSI device
    30     nodes  ),  shall  automatically generate default values for these
    31     parameters as described below.

    32     F.4.1.1  SCA System Name

    33     DSSI nodes that automatically  generate  a  default  System  Name
    34     shall use the following guidelines:

    35          1.  Ignore human readability






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     1          2.  Make the name as unique as  possible,  for  example,  by
     2              deriving the value from serial number.

     3          3.  The name should be of the form, 'ppdddd', where:

     4               o  pp:  is the product name, abridged to two characters
     5                  (eg.,R7)

     6               o  dddd:   is  a  base-36  string  of  characters  (the
     7                  consonants  in  the letters "A" -"Z" and the numbers
     8                  "0" - "9") formed by the most  unique  part  of  the
     9                  device's serial number taken six bits at a time, the
    10                  overflow (above 35) is carried to the next  six  bit
    11                  group.


    12          4.  The six characters in the name shall not include any  of
    13              the five vowels.

    14          5.  The name should be alterable by a diagnostic program.


    15                                   NOTE

    16             Rules 1,  3  and  4  do  not  apply  to  manually
    17             generated System Names.


    18     The KFQSA adapter should use a similar approach.  In nodes with a
    19     management  interface  this  parameter  is  an  alterable  system
    20     configuration parameter;  such  alterations  shall  be  preserved
    21     across power failures.

    22     F.4.1.2  SCS SYSTEMID

    23     This 48 bit  parameter  should  be  derived  from  the  following
    24     guidelines.

    25          1.  The default values for this parameter should be  derived
    26              from drive serial number (or Ethernet Address).

    27          2.  The parameter must be changeable, and  changes  must  be
    28              preserved across power failures.

    29          3.  It shall be unique across  the  domain  of  all  Digital
    30              products.




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     1     Every DSSI node polls all other DSSI nodes by attempting to  send
     2     IDREQ packets.  If the transmission succeeds (remote node exists,
     3     powered up, and not in uninitialized state),  the  receiver  will
     4     respond   with  ID  packet  indicating  the  Port  State.   After
     5     exchanging  IDREQ/ID  packets,  a  node  will  then  attempt   to
     6     establish  a  virtual circuit to this node if a VC is not already
     7     open.   A  VC  is  established   between   two   nodes   by   the
     8     START/STACK/ACK   handshake   described   in   Sec   9.2  of  SCA
     9     Specification, Ref [4].

    10     The default values for the polling interval, and  the  number  of
    11     nodes to be polled per polling interval are established in one of
    12     the following ways.

    13     In nodes that have a management interface, the default values are
    14     alterable  (for  example  through SYSGEN parameters in host nodes
    15     that do not use the KFQSA).

    16     In nodes that do not  have  a  management  interface  (eg.,  DSSI
    17     drives,  and KFQSA), the values are stored in a EEROM, and may be
    18     altered through a diagnostic program.

    19     F.5  SCA Packet Format Clarification

    20     The SCA Spec is somewhat confusing in its depiction of PPD packet
    21     formats.   Specifically,  the  LENGTH field shown just before the
    22     PPD_TYPE field is *not* part of  the  packet  body.   The  length
    23     field is derived from the frame length transmitted in the command
    24     out phase; it does not appear in the data out phase in any form.

    25     For example, the format of a PPD START datagram is illustrated in
    26     section 10.1.1 of the SCA spec as:

    27                     3               1                
    28                     1               5               0
    29                     +---------------+---------------+
    30                     |    PPD_TYPE   |    LENGTH     |
    31                     +---------------+---------------+
    32                     |                               |
    33                     =           START_DATA          =
    34                     |                               |
    35                     +-------------------------------+








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           SCA Packet Format Clarification                     27 March 1990


     1                Figure F-2:  Format of PPD START Datagram


     2     and illustrated in Appendix F of the SCA Spec  with  more  detail
     3     as:

     4                      3                              
     5                      1                             0
     6                     +-------------------------------+
     7                     |   PPD MTYPE   |   LENGTH      |
     8                     +-------------------------------+
     9                     |           SEND_SYS            |
    10                     +---------------+               |
    11                     | RSV   | PRTVRS|               |
    12                     +---------------+---------------+
    13                     |    MAX_MSG    |    MAX_DG     |
    14                     +---------------+---------------+
    15                     |            SW_TYPE            |
    16                     +-------------------------------+
    17                     |           SW_VERSION          |
    18                     +-------------------------------+
    19                     |         SW_INCARNATION        |
    20                     |                               |
    21                     +-------------------------------+
    22                     |            HW_TYPE            |
    23                     +-------------------------------+
    24                     |                               |
    25                     =           HW_VERSION          =
    26                     |                               |
    27                     +-------------------------------+
    28                     |           NODE_NAME           |
    29                     |                               |
    30                     +-------------------------------+
    31                     |            CUR_TIME           |
    32                     |                               |
    33                     +-------------------------------+

    34                Figure F-3:  Detail of PPD START Datagram


    35     What is actually sent during the DSSI data out phase for a  START
    36     datagram is the following:








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     1          31        24 23       16 15           8 7             0
     2         +-----------+-----------+--------------+---------------+
     3         | PPD_TYPE = START = 0  | CI flags = 0 | CI opcode = 1 |
     4         +-----------+-----------+--------------+---------------+
     5         |                   SEND_SYS                           |
     6         +-----------+-----------+                              +
     7         |    RSV    |   PRTVRS  |                              |
     8         +-----------+-----------+--------------+---------------+
     9         .                                                      .
    10         .                                                      .
    11         +-----------+-----------+--------------+---------------+
    12         |                                                      |
    13         +---                 CUR_TIME                       ---+
    14         |                                                      |
    15         +-----------+-----------+--------------+---------------+


    16                  Figure F-4:  PPD Start Datagram Packet


    17     and the frame length passed in the  DSSI  command  out  phase  is
    18     START_LEN+2 or 64 (decimal).

    19     The reason for this discrepancy is that the formats shown in  the
    20     SCA  Spec  are the formats passed to and from the VAX CI port ---
    21     not the format that appears on the wire.  The CI  port  interface
    22     has  the  packet  length  field  in the position shown in the SCA
    23     Spec.  The CI port adjusts the length field for the CI opcode and
    24     CI  flags  bytes, which is why the length that appears in the SCA
    25     Spec is 2 bytes less than the actual length on the wire.

    26     Another example  is  a  Disk  MSCP  transfer  command.   This  is
    27     somewhat  similar  to  Appendix  G  of the SCA Spec but with more
    28     detail.  What is actually sent during the DSSI data phase is  the
    29     following:















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     1           31       24 23      16 15       8 7        0         
     2           +----------+----------+----------+----------+<-------
     3           | PPD_TYPE =          |CI flags  | CI opcode| PPD Hdr
     4           |       SCS_MSG = 4   | = seqno  |     = 2  |        
     5           +-----------+---------+----------+----------+<-------
     6           |       CREDIT = 1    |  SCS_TYPE           |        
     7           |       ( usually )   |      = APPL_MSG = 10|        
     8           +-----------+---------+----------+----------+        
     9           |              REC_CONNECT_ID               | SCS Hdr
    10           +-----------+---------+----------+----------+        
    11           |              SEND_CONNECT_ID              |        
    12           +-----------+---------+----------+----------+<-------
    13           |        MSCP command reference number      |        
    14           +-----------+---------+----------+----------+        
    15           |       Reserved      |     Unit number     |        
    16           +-----------+---------+----------+----------+        
    17           |       Modifiers     |  Flags   |  MSCP    |        
    18           |                     |          |  Opcode  |        
    19           +-----------+---------+----------+----------+        
    20           |                 Byte Count                |        
    21           +-----------+---------+----------+----------+        
    22           |                                           | MSCP   
    23           +---                                     ---+ Cmd.   
    24           |             Buffer Descriptor             | Packet 
    25           +---                                     ---+        
    26           |                                           |        
    27           +-----------+---------+----------+----------+        
    28           |           Logical Block Number            |        
    29           +-----------+---------+----------+----------+        


    30         Figure F-5:  SCA Message Packet containing MSCP Command


    31     The frame length sent in the DSSI command out phase is:

    32             (MSCP command packet length) + AP_MSG_HDR_LEN + 2


    33             = 32 + 14 + 2 = 48

    34     AP_MSG_HDR_LEN is defined in SCA Appendix D.  The "+2" is for the
    35     CI opcode and flags, just as before.

    36     Packet formats defined in DEC STD 161 are sent exactly  as  shown
    37     in  that  document.   They include the CI opcode and flags fields
    38     but no other header information.  The actual packet  formats  are



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     1     described  in  section  4  of  DEC STD 161 and the CI opcodes are
     2     summarized in Appendix A.  These packet formats include:

     3              SNTDAT       Sent Data                        
     4              CNF          Confirm For Sent Data            
     5              DATREQ0/1/2  Data Request                     
     6              RETDAT       Returned Data                    
     7              IDREQ        ID Request                       
     8              RST          Reset                            
     9              SNTMDAT      Sent Maintenance Data            
    10              MDATREQ      Maintenance Data Request         
    11              STRT         Start                            
    12              ID           ID Information                   
    13              RETMDAT      Returned Maintenance Data        
    14              MCNF         Confirm For Sent Maintenance Data
    15              LB           Loopback                         


    16     The DG (datagram) and MSG (sequenced  message)  CI  opcodes  both
    17     imply  that  a  PPD  header  is present.  The PPD header, as sent
    18     across the wire, includes just the PPD_TYPE field.  The following
    19     values of PPD_TYPE means that the packet has the format described
    20     in chapter 10 of the SCA Spec:


    21                                 START    
    22                                 STACK    
    23                                 ACK      
    24                                 ERROR_LOG
    25                                 NODE_STOP

    26     If PPD_TYPE is SCS_DG or SCS_MSG, then an SCS header is  present.
    27     The  SCS  header  is the SCS_TYPE, CREDIT, REC_CONNECTION_ID, and
    28     SEND_CONNECTION_ID fields.

    29     It should be noted that some of these fields are reserved in some
    30     of  the  SCS  message  types,  as  dictated by the SCS_TYPE.  The
    31     following values of SCS_TYPE mean that the packet has the  format
    32     and interpretation described in chapter 8 of the SCA Spec:











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     1                                CONNECT_REQ
     2                                CONNECT_RSP
     3                                ACCEPT_REQ 
     4                                ACCEPT_RSP 
     5                                REJECT_REQ 
     6                                REJECT_RSP 
     7                                DISCON_REQ 
     8                                DISCON_RSP 
     9                                CREDIT_REQ 
    10                                CREDIT_RSP 

    11     It should be noted that chapter 8 shows  these  messages  without
    12     the PPD header and CI header.

    13     If SCS_TYPE is APPL_MSG or APPL_DG, it means that an MSCP, TMSCP,
    14     DUP,  or  some  other  application  protocol  message immediately
    15     follows the SEND_CONNECT_ID field.  This is  illustrated  in  SCA
    16     sections  8.3  and  8.4  and  in the previous paragraph.  The PPD
    17     header and CI header are of course present.

    18     The important point to remember is that the data structures  that
    19     appear  in the SCA document are completely oriented towards a VAX
    20     host system.  That is, they  are  the  data  structures  as  they
    21     appear  at the CI port interface, not as they appear on the wire.
    22     The format of a sequenced message at the CI port interface is the
    23     following  (see,  for  example,  section 7.2.1 of the VAX CI Port
    24     Spec) (diagram is 32 bits wide):























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     1                     31                             0 
     2                     +-------+-------+-------+-------+
     3                     |             FLINK             |
     4                     +-------+-------+-------+-------+
     5                     |             BLINK             |
     6                     +-------+-------+-------+-------+
     7                     |     Reserved for Software     |
     8                     +-------+-------+-------+-------+
     9                     | Flags |  OPC  |  MBZ  |  PORT |
    10                     +-------+-------+-------+-------+
    11                     |               |    MSG_LEN    |
    12                     +               +-------+-------+
    13                     |                               |
    14                     .                               .
    15                     .              MSG              .
    16                     .                               .
    17                     |                               |
    18                     +-------+-------+-------+-------+

    19                Figure F-6:  Format of VAX CI Port Packet


    20     where PORT is the destination node number, OPC  is  the  CI  port
    21     opcode  (*not*  the  CI  packet  opcode),  and Flags is the flags
    22     field, somewhat similar in both CI port and CI  packet.   MSG_LEN
    23     is  the  length  of  MSG,  which  is the message text.  This gets
    24     translated to the  following  CI  packet  format  "on  the  wire"
    25     (diagram is 8 bits wide):






















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     1                                     .
     2                             |    preamble   |
     3                             +---------------+
     4                             |               |
     5                             +-    length   -+
     6                             |               |
     7                             +---------------+
     8                             |      dest     |
     9                             +---------------+
    10                             |   dest compl  |
    11                             +---------------+
    12                             |     source    |
    13                             +---------------+
    14                             |  opcode = 2   |
    15                             +---------------+
    16                             | flags = seqno |
    17                             +---------------+
    18                             |               |
    19                             .               .
    20                             .      text     .
    21                             .               .
    22                             |               |
    23                             +---------------+
    24                             |      CRC      |
    25                                     .

    26                     Figure F-7:  Format of CI Packet


    27     where "dest" is the destination node ("PORT" above), "dest compl"
    28     is  its  ones complement, "source" is the source node.  "text" is
    29     the message text, copied  from  "MSG"  above.   "length"  is  the
    30     length from "length" through "text", which means it is MSG_LEN+7.

    31     The same packet appears on DSSI as the following:














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     1                              Command Phase:

     2                          7                    0 
     3                         +----------------------+
     4                         |  DSSI opcode  ( E0h) |
     5                         +----------------------+
     6                         |  REQ/ACK |           |
     7                         +----------------------+
     8                         |        Dest          |
     9                         +----------------------+
    10                         |       Source         |
    11                         +----------------------+
    12                         |       Frame          |
    13                         +-      Length        -+
    14                         |                      |
    15                         +----------------------+
    16                         |      Checksum        |
    17                         +----------------------+

    18                                Data Phase:

    19                          7                    0 
    20                         +----------------------+
    21                         |      Opcode = 2      |
    22                         +----------------------+
    23                         |    Flags = seqno     |
    24                         +----------------------+
    25                         |                      |
    26                         =        Text          =
    27                         |                      |
    28                         +----------------------+
    29                         |      Checksum        |
    30                         +----------------------+


    31                     Figure F-8:  DSSI Packet Format


    32     The "dest", "source", and "text" fields are the same  as  before.
    33     However, "frame length" is MSG_LEN+2.

    34     For how this relates to the message  formats  shown  in  the  SCA
    35     Spec,  the  Example  CI  Message  shown  in  Appendix G should be
    36     considered.






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     1     That example message is:

     2                     +-------+-------+-------+-------+
     3                     |             FLINK             |
     4                     +-------+-------+-------+-------+
     5                     |             BLINK             |
     6                     +-------+-------+-------+-------+
     7                     |SWFLAG | TYPE  |     SIZE      |
     8                     +-------+-------+-------+-------+
     9                     | Flags |  OPC  | STATUS|  PORT |
    10                     +=======+=======+=======+=======+
    11                     |   PPD MTYPE   |    LENGTH     |
    12                     +=======+=======+=======+=======+
    13                     |    CREDIT     |   SCS MTYPE   |
    14                     +-------+-------+-------+-------+
    15                     |    DESTINATION CONNECT ID     |
    16                     +-------+-------+-------+-------+
    17                     |      SOURCE CONNECT ID        |
    18                     +=======+=======+=======+=======+
    19                     |                               |
    20                     =   Application Message Text    =
    21                     |    (e.g., MSCP command)       |
    22                     +-------+-------+-------+-------+


    23        Figure F-9:  SCS Application Message in VAX CI Port Packet


    24     First, it should be  noted  that  the  "FLINK"  through  "LENGTH"
    25     fields  are  exactly  the  same  as  the  CI  port message format
    26     illustrated earlier.  The "reserved for software" field has  been
    27     interpreted, but everything else is the same.

    28     Second, the PPD message descriptions that appear in  SCA  Chapter
    29     10 start at the LENGTH and PPD MTYPE fields in this illustration;
    30     preceding fields are omitted from Chapter 10.

    31     Third, the SCS message descriptions that appear in SCA Chapter  8
    32     start  at  the  SCS MTYPE and CREDIT fields in this illustration;
    33     preceding fields are omitted from Chapter 8.

    34     Per the previous description,  this  message  translates  to  the
    35     following sequence of DSSI Data Phase bytes:







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     1                             +---------------+
     2                             |  Opcode = 2   |
     3                             +---------------+
     4                             | Flags = seqno |
     5                             +===============+
     6                             |               |
     7                             +-  PPD MTYPE  -+
     8                             |               |
     9                             +===============+
    10                             |               |
    11                             +-  SCS MTYPE  -+
    12                             |               |
    13                             +---------------+
    14                             |               |
    15                             +-   CREDIT    -+
    16                             |               |
    17                             +---------------+
    18                             |               |
    19                             +-             -+
    20                             |  DESTINATION  |
    21                             +-   CONNECT   -+
    22                             |      ID       |
    23                             +-             -+
    24                             |               |
    25                             +---------------+
    26                             |               |
    27                             +-             -+
    28                             |    SOURCE     |
    29                             +-   CONNECT   -+
    30                             |      ID       |
    31                             +-             -+
    32                             |               |
    33                             +===============+
    34                             |  Application  |
    35                             =    Message    =
    36                             |     Text      |
    37                             +---------------+
    38                             |    Checksum   |
    39                             +---------------+


    40         Figure F-10:  SCS Application Message in DSSI Data Block


    41     There is  no  length  field  anywhere  in  the  DSSI  Data  Phase
    42     transmission.   The  only length field is the one that appears in
    43     command phase.  The length field that appears in the PPD  message



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           Digital's Storage System Interconnect               Version 1.0.0
           SCA AND MSCP CLARIFICATIONS                             Page F-16
           SCA Packet Format Clarification                     27 March 1990


     1     descriptions  is  derived  from  the  command  phase frame length
     2     field.
















































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           Digital's Storage System Interconnect               Version 1.0.0
           REVISION HISTORY                                         Page G-1
                                                               27 March 1990


     1                                APPENDIX G

     2                             REVISION HISTORY


     3     This appendix  tracks  the  revision  history  of  the  document.
     4     Please  note  that  the  change bars present in the document only
     5     reflect changes from the previous version and are NOT cumulative.

     6     Version 1.0.0

     7     Date:  27 March 1990


     8     General:

     9         Version approved for ECO control.

































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           Digital's Storage System Interconnect               Version 1.0.0
           EXCEPTIONS                                               Page H-1
                                                               27 March 1990


     1                                APPENDIX H

     2                                EXCEPTIONS


     3     H.1  Policy

     4     An exception allows a product to differ from the specification in
     5     some way throughout the product's lifetime.

     6     The exceptions described in  the  following  sections  have  been
     7     granted   to   accomodate   products   in   existence   when  the
     8     specification  was  prepared.   The  decision   to   grant   such
     9     exceptions was made on the basis that the area of non-compliance,
    10     although resulting  in  less  than  optimum  behavior,  does  not
    11     seriously compromise the long-term architectural goals.

    12     All future exception requests shall be submitted as proposals for
    13     ECO's to this document.

    14     H.2  Exceptions For Products Using The SII Bus Interface Chip

    15     The SII chip is a first-generation bus interface chip  that  does
    16     not  support the architecural features described below.  Products
    17     that interface to the DSSI bus using this  chip  shall  therefore
    18     adhere to the following requirements:

    19     Section 5.5.6 SELECTION Phase -


    20         The SII chip has no selection  timeout  mechanism,  therefore
    21         such products shall detect a selection response failure using
    22         the initiator timeout mechanism defined in  section  5.5.1.4,
    23         Watchdog Timers.

    24         Note that these products shall,  nevertheless,  fully  comply
    25         with the selection response requirements of section 5.5.6.

    26     When such an initiator detects an initiator timeout or BUS RESET,
    27     it's  Channel  Control  layer  shall  report such conditions with
    28     status CC_NORSP.

    29     Section 5.5.5, Fair (Round-Robin) arbitration -


    30         The  SII  chip  does  not  support  round-robin  arbitration.
    31         Instead,  the fixed priority arbitration mechanism defined in



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           EXCEPTIONS                                               Page H-2
           Exceptions For Products Using The SII Bus Inter ... 27 March 1990


     1         section H.2.1 shall be used.

     2     The following is  a  list  of  products  that  use  the  SII  bus
     3     interface:



     4           o  The KFQSA 6-Channel SSP controller

     5           o  The RF30 150mb winchester disk drive

     6           o  The RF71 400mb winchester disk drive

     7           o  The Mayfair II DSSI I/O Adapter


     8     H.2.1  SII Fixed Priority Arbitration Scheme

     9     This section documents the fixed priority arbitration scheme used
    10     on  DSSI  products  implemented  with  the  SII.   This scheme is
    11     obsolete and shall not be implemented on any other DSSI products.

    12     The timing for fixed priority arbitration is detailed below:

    13          1.  A DSSI device that needs bus  access  (Initiator)  shall
    14              first wait for the BUS FREE phase to occur.

    15          2.  The device shall then wait 800  ns  before  driving  any
    16              signal.

    17          3.  Following this delay, devices may arbitrate by asserting
    18              both  BSY  and  their  own  DSSI ID.  However, no device
    19              shall attempt arbitration if  more  than  1400  ns  have
    20              passed  since  the BUS FREE phase was last detected.  As
    21              long as the bus remains free, there is no maximum  delay
    22              before arbitrating.

    23          4.  After waiting 2200 ns following assertion  of  BSY,  the
    24              device  shall  sample  the  bus.  If a higher DSSI ID is
    25              present on the bus or SEL is asserted,  the  device  has
    26              lost  arbitration  and  shall  release  its  signals and
    27              return to step 1.  If no higher DSSI ID is  present  and
    28              SEL  is not asserted, the device has won arbitration and
    29              signals this by asserting SEL.  All other  devices  must
    30              release  their  signals  within 800 ns after SEL becomes
    31              true.




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           EXCEPTIONS                                               Page H-3
           Exceptions For Products Using The SII Bus Inter ... 27 March 1990


     1          5.  The device that has won arbitration shall wait at  least
     2              1200 ns after asserting SEL before changing any signals.


     3     H.3  Exceptions For SHAC/DASH

     4     SHAC and DASH are products based on a single-chip  implementation
     5     of  the  VAX  CI  port layered on a DSSI datalink.  SHAC ( Single
     6     Host Adapter Chip ) interfaces a single DSSI bus  to  a  Microvax
     7     host  while  DASH  ( Dual  Adapter - Single Host ) interfaces two
     8     DSSI busses to an XMI-based host.

     9     H.3.1  Target Timeout Enforcement


    10     Section 5.5.6, SELECTION Phase, requires the target to begin  the
    11     Target  Timeout  interval  from  the  point  at  which the target
    12     detects  valid  selection.   As  a  side-effect   of   host   bus
    13     congestion,  SHAC/DASH implementations may delay the start of the
    14     target timeout interval.   In  extreme  cases  this  delay  might
    15     result  in an effective target timeout that exceeds the initiator
    16     timeout.

    17     The  arithmetic  average  of  such  delays,  measured  from   the
    18     assertion  of  BSY  by  the  target  to  the start of the timeout
    19     interval,  shall  not  exceed  200us  when  observed   over   any
    20     ten-minute interval.























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           Digital's Storage System Interconnect               Version 1.0.0
           TERMINATOR SELECTION                                     Page J-1
                                                               27 March 1990


     1                                APPENDIX J

     2                           TERMINATOR SELECTION


     3     In the selection of the terminator values, there were three  main
     4     areas  of  interest:   the signal integrity, particularly ringing
     5     and reflections due to impedance mismatches;  the  noise  margin;
     6     and the low level output current.

     7     The major factor in signal integrity on the interconnect  is  the
     8     relative  impedances of the different components.  The terminator
     9     values should be matched as closely as possible  to  the  overall
    10     impedance  of  the  interconnect.  Impedance mismatches result in
    11     overshoot and ringing on the bus.

    12     The effective impedance of the DSSI interconnect depends  on  the
    13     cable configuration and the number of devices present on the bus.
    14     Calculations show that the impedance can range from 65 to 86 Ohms
    15     over  the  variety of different cabling and device possibilities.
    16     As a result it was not possible to select  a  termination  scheme
    17     which  eliminated impedance mismatches.  The selected terminators
    18     have an equivalent impedance of 81.5 Ohms.  This value provides a
    19     good  impedance match for most of the possible configurations, as
    20     was verified with extensive simulation.

    21     The noise margin is the voltage difference between the high level
    22     output   voltage,   determined   by   the  terminators,  and  the
    23     high-to-low receiver threshold voltage.  This noise margin can be
    24     degraded  by  undershoot caused by ringing and reflections on the
    25     bus.  The problem of impedance mismatches between the terminators
    26     and  some  interconnect  configurations  does cause undershoot in
    27     some cases.  Therefore it was  necessary  to  select  terminators
    28     such  that  an  adequate noise margin was maintained even for the
    29     worst case cable and loading conditions.   A  value  of  Voh=3.15
    30     volts  at  a  worst  case  TERMPWR  of  4.45  volts was selected.
    31     Simulations of the worst case conditions (fully loaded system and
    32     attached  expansion  box)  show  that  this value gives a minimum
    33     noise margin of 0.5 volts.  This worst case occurs only for short
    34     periods  of  time (< 5nS) due to undershoot on the rising edge of
    35     the output waveform.









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           TERMINATOR SELECTION                                     Page J-2
                                                               27 March 1990


     1     The values for the terminator resistors were calculated from  the
     2     desired  values  for  the  impedance  and  the  high level output
     3     voltage.


     4                         R1*R2
     5                       ---------- = 81.5 Ohms
     6                        R1 + R2


     7                           R2
     8                       --------- * 4.45 Volts = 3.15 Volts
     9                        R1 + R2


    10             From these equations we get:  R1 = 115 Ohms
    11                                           R2 = 280 Ohms.


    12     These values provide good signal integrity, noise margin, and low
    13     level  output  current,  and  were therefore the values selected.
    14     Extensive simulation using these and other values confirmed  that
    15     this was the best choice.



























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