



                  










                                 Storage Systems Port

                             ECO Controlled Version 3.1.0

                                    9 November 1989





                     Send all inquiries and comments to SSAG::SSAG





               This  document  describes  the  Storage   Systems   Port
               interface between hosts and storage system controllers.









              DIGITAL EQUIPMENT CORPORATION CONFIDENTIAL AND PROPRIETARY

               This  document  is  an  unpublished  work  and  contains
               valuable   trade  secrets  which  are  confidential  and
               proprietary to Digital Equipment  Corporation,  and  may
               only be disclosed to individuals who have entered into a
               confidentiality agreement with Digital, and may  not  be
               copied or reproduced in whole or in part.

               Copyright (c) Digital Equipment Corporation  1989.   All
               Rights Reserved.




                 *** R E S T R I C T E D  D I S T R I B U T I O N ***
           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           CONTENTS                                                  Page ii
                                                             9 November 1989


                                           CONTENTS



           CHAPTER 1       INTRODUCTION

                   1.1     DSA Subsystem Overview . . . . . . . . . . .  1-1
                   1.2     Host/Controller Communications Overview  . .  1-3
                   1.3     Purpose  . . . . . . . . . . . . . . . . . .  1-5
                   1.4     Scope  . . . . . . . . . . . . . . . . . . .  1-5


           CHAPTER 2       STORAGE SYSTEMS PORT ARCHITECTURE

                   2.1     Overview . . . . . . . . . . . . . . . . . .  2-1
                   2.2     Physical Layer . . . . . . . . . . . . . . .  2-2
                   2.2.1     Characteristics  . . . . . . . . . . . . .  2-2
                   2.2.2     Requirements . . . . . . . . . . . . . . .  2-3
                   2.2.3     I/O Page Registers . . . . . . . . . . . .  2-3
                   2.3     Logical Layer  . . . . . . . . . . . . . . .  2-5
                   2.3.1     Host/Controller Communications Area  . . .  2-5
                   2.3.1.1     Controller Scratchpad Descriptor . . . .  2-7
                   2.3.1.2     Interrupt Indicators . . . . . . . . . .  2-7
                   2.3.1.3     Command And Response Queues  . . . . . .  2-8
                   2.3.2     Messages And Message Buffers . . . . . . . 2-10
                   2.3.3     Message Credits  . . . . . . . . . . . . . 2-13
                   2.3.4     Message Transmission . . . . . . . . . . . 2-14
                   2.3.4.1     Host To Controller   . . . . . . . . . . 2-14
                   2.3.4.2     Controller To Host . . . . . . . . . . . 2-14
                   2.3.5     Interrupts . . . . . . . . . . . . . . . . 2-15
                   2.3.6     Queue Access . . . . . . . . . . . . . . . 2-15
                   2.3.6.1     Command Queue  . . . . . . . . . . . . . 2-15
                   2.3.6.2     Response Queue . . . . . . . . . . . . . 2-17
                   2.3.6.3     Additional Requirements  . . . . . . . . 2-18
                   2.3.7     Data Transmission  . . . . . . . . . . . . 2-19
                   2.3.7.1     Unmapped Addressing Mode . . . . . . . . 2-20
                   2.3.7.2     Mapped Addressing Mode . . . . . . . . . 2-21
                   2.3.8     Transmission Errors  . . . . . . . . . . . 2-25
                   2.3.9     Self Detected Fatal Port/Controller Errors 2-26
                   2.3.10    Port Performance Considerations  . . . . . 2-27
                   2.3.11    Node Name Packets  . . . . . . . . . . . . 2-27


           CHAPTER 3       PORT/CONTROLLER INITIALIZATION

                   3.1     Initialization Overview  . . . . . . . . . .  3-1
                   3.2     Initialization Details . . . . . . . . . . .  3-2
                   3.2.1     Standard Initialization Step 1 . . . . . .  3-4
                   3.2.2     Standard Initialization Step 2 . . . . . .  3-7
                   3.2.3     Standard Initialization Step 3 . . . . . .  3-8


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           Storage Systems Port                                Version 3.1.0
           CONTENTS                                                 Page iii
                                                             9 November 1989


                   3.2.4     Standard Initialization Step 4 . . . . . . 3-10


           CHAPTER 4       VAXBI STORAGE SYSTEMS PORT

                   4.1     Overview . . . . . . . . . . . . . . . . . .  4-1
                   4.2     BI I/O Page Registers  . . . . . . . . . . .  4-1
                   4.3     Data Transmission  . . . . . . . . . . . . .  4-3
                   4.4     Controller Initialization  . . . . . . . . .  4-3
                   4.4.1     BI Register Usage  . . . . . . . . . . . .  4-3
                   4.4.2     Initialization Procedure . . . . . . . . .  4-4
                   4.4.2.1     BI Node Initialization . . . . . . . . .  4-5
                   4.4.2.2     Standard Initialization  . . . . . . . .  4-6


           CHAPTER 5       XMI STORAGE SYSTEMS PORT 

                   5.1     Overview . . . . . . . . . . . . . . . . . .  5-1
                   5.2     XMI Port Registers . . . . . . . . . . . . .  5-1
                   5.3     XMI-Specific Initialization  . . . . . . . .  5-4
                   5.3.1     Hard Initialization  . . . . . . . . . . .  5-4
                   5.3.2     Soft Initialization  . . . . . . . . . . .  5-4
                   5.3.3     Maintenance Initialization . . . . . . . .  5-5
                   5.3.4     Code Update Initialization . . . . . . . .  5-5
                   5.3.4.1     Code Update Registers  . . . . . . . . .  5-6
                   5.3.4.2     Code Update Operation; Examples  . . . .  5-9
                   5.3.4.2.1     Controller Host Synchronization  . . .  5-9
                   5.3.4.2.2     Setting A New Controller Address . . .  5-9
                   5.3.4.2.3     Write Controller Memory Operations . . 5-10
                   5.3.4.2.4     Read Controller Memory Operations  . . 5-11
                   5.3.4.2.5     Exiting The Update . . . . . . . . . . 5-12
                   5.3.4.3     Power Failure, Host Crashes, Etc.  . . . 5-12
                   5.3.5     SSP Initialization Differences . . . . . . 5-13
                   5.3.5.1     Step 1 Differences . . . . . . . . . . . 5-13
                   5.3.5.2     Step 4 Differences . . . . . . . . . . . 5-14
                   5.4     Bus-Specific Fields In Communications Area   5-14
                   5.5     Data Transmission  . . . . . . . . . . . . . 5-15
                   5.5.1     Unmapped Addressing  . . . . . . . . . . . 5-15
                   5.5.2     Mapped Addressing Mode . . . . . . . . . . 5-16
                   5.6     Address Restrictions . . . . . . . . . . . . 5-21
                   5.7     Write Ordering . . . . . . . . . . . . . . . 5-21
                   5.8     Error Reporting  . . . . . . . . . . . . . . 5-22


           CHAPTER 6       PORT/CONTROLLER DIAGNOSTIC AND MAINTENANCE 
                           FACILITIES

                   6.1     Diagnostic Wrap Mode . . . . . . . . . . . .  6-1
                   6.2     Purge And Poll Tests . . . . . . . . . . . .  6-1
                   6.3     Host Memory And Bus Tests  . . . . . . . . .  6-2


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           Storage Systems Port                                Version 3.1.0
           CONTENTS                                                  Page iv
                                                             9 November 1989


                   6.4     Last Fail Error Packets  . . . . . . . . . .  6-2
                   6.5     Special Function Mode  . . . . . . . . . . .  6-5
                   6.6     Maintenance Read And Maintenance Write 
                           Commands . . . . . . . . . . . . . . . . . .  6-6
                   6.6.1     Maintenance Read Command . . . . . . . . .  6-7
                   6.6.2     Maintenance Write Command  . . . . . . . .  6-9
                   6.6.3     Maintenance Read/Write Response Status 
                             Codes  . . . . . . . . . . . . . . . . . . 6-10


           APPENDIX A      CONNECTION ID, PORT TYPE, AND MODEL DEFINITIONS


           APPENDIX B      PORT FATAL ERROR CODE DEFINITIONS


           APPENDIX C      WAIVERS AND EXCEPTIONS


           APPENDIX D      REVISION HISTORY


           APPENDIX E      UNANNOUNCED PRODUCTS


           FIGURES

                   1-1     Example Storage Systems Port Based DSA 
                           Subsystem  . . . . . . . . . . . . . . . . .  1-3
                   2-1     Communications Area Layout . . . . . . . . .  2-6
                   2-2     Address Mapping Process  . . . . . . . . . . 2-24
                   3-1     Purge/Poll Test Sequence . . . . . . . . . .  3-9
                   5-1     XMI Address Mapping Process  . . . . . . . . 5-20


           TABLES

                   4-1     BI Register Usage  . . . . . . . . . . . . .  4-4
                   5-1     XMI I/O Registers  . . . . . . . . . . . . .  5-2
                   5-2     Host Command Opcodes . . . . . . . . . . . .  5-7
                   5-3     Controller Status Codes  . . . . . . . . . .  5-8
                   5-4     Code Update Error Codes  . . . . . . . . . .  5-8
                   A-1     Connection ID Values . . . . . . . . . . . .  A-1
                   A-2     Port Type Values . . . . . . . . . . . . . .  A-1
                   A-3     Controller Model Values  . . . . . . . . . .  A-2
                   B-1     Port Fatal Error Code Ranges . . . . . . . .  B-1
                   E-1     Controller Model Values  . . . . . . . . . .  E-1
                   E-2     Port Fatal Error Code Ranges . . . . . . . .  E-1




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           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           INTRODUCTION                                             Page 1-1
                                                             9 November 1989


     1                                 CHAPTER 1

     2                               INTRODUCTION


     3     1.1  DSA Subsystem Overview

     4     A Digital Storage Architecture  (DSA)  subsystem  consists  of  a
     5     host,  an  intelligent  mass storage controller, a communications
     6     mechanism, and related software entities.

     7     The controller contains  intelligence  to  perform  detailed  I/O
     8     handling tasks such as:  controlling the physical functions of an
     9     I/O device, transferring data to/from an I/O  device  or  to/from
    10     the  host,  buffering  the data as necessary, optimizing requests
    11     for maximum throughput, detecting and recovering from I/O errors,
    12     etc.  The host simply sends I/O requests to the controller and is
    13     notified when the controller has  performed  all  the  I/O  tasks
    14     necessary to fulfill the request to the fullest extent possible.

    15     The communication of  I/O  requests  and  completion  notices  is
    16     message  packet  oriented,  controlled by higher level protocols.
    17     Currently there are three higher level protocols  defined  within
    18     DSA:

    19           o  Disk -- for disk I/O device control; defined in  the
    20              Mass Storage Control Protocol (MSCP) specification

    21           o  Tape -- for tape I/O device control; defined in  the
    22              Tape   Mass   Storage   Control   Protocol   (TMSCP)
    23              specification

    24                  and,

    25           o  Diagnostics  and  Utilities  --  for  mass   storage
    26              controller  and  I/O  device  diagnostic and utility
    27              program control;  defined  in  the  Diagnostics  and
    28              Utilities Protocol (DUP) specification.

    29     The host and controller are physically connected  by  a  hardware
    30     communications  mechanism  through  a  port located in each.  The
    31     hardware communications mechanism permits the host and controller
    32     to  communicate  with each other using the higher level protocols
    33     and to transfer data between the two as well.  The port  provides
    34     the   software  to  hardware  interface  necessary  for  software
    35     processes, located in both the host and controller, to access the
    36     communications  mechanism  for  those  purposes.  The software to
    37     hardware interface is referred to as the port "access protocol." 




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           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           INTRODUCTION                                             Page 1-2
           DSA Subsystem Overview                            9 November 1989


     1     The host and controller  each  use  two  levels  of  software  to
     2     accomplish  their  tasks.   The  higher level software process is
     3     called a "class driver"  in  the  host  and  a  "server"  in  the
     4     controller.   The  class driver and server are concerned with the
     5     specifics of I/O device control and communicate with  each  other
     6     using   the   higher   level  protocol  messages  via  a  logical
     7     communications path known as a  "connection."   The  lower  level
     8     software  process in both the host and controller is known as the
     9     "port driver" and is concerned only with providing communications
    10     services for the higher level processes across the communications
    11     mechanism through the port.

    12     The host and controller typically provide multiple  higher  level
    13     software  processes  (i.e.,  class  drivers and servers), one for
    14     each higher level protocol they support.  Hosts provide a  single
    15     port  driver  for  each different communications mechanism (i.e.,
    16     port type) they support.  Controllers typically support only  one
    17     communications  mechanism  and  therefore  provide  only one port
    18     driver.

    19     The Storage Systems Port is an interface which enables use of the
    20     Unibus,  Q-Bus,  BI,  and XMI busses as communications mechanisms
    21     between a host and a  controller.   Figure  1-1  illustrates  the
    22     various  components  of a DSA storage subsystem that utilizes the
    23     Storage Systems Port.



























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           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           INTRODUCTION                                             Page 1-3
           DSA Subsystem Overview                            9 November 1989


     1                 Host                     Mass Storage Controller 
     2          + - - - - - - - - +                + - - - - - - - - +  
     3          |                 |  Higher Level  |                 |  
     4             +-----------+       Protocol       +-----------+     
     5          |  |   Class   |  |     (HLP)      |  |    HLP    |  |  
     6             |   Driver  | <------------------> |   Server  |     
     7          |  +-----------+  |   Connection   |  +-----------+  |  
     8                   A                                  A           
     9          |        |        |                |        |        |  
    10                   |                                  |           
    11          |        |        |                |        |        |  
    12                   V              SSP                 V           
    13          |  +-----------+  |    Access      |  +-----------+  |  
    14             |   SSP     |      Protocol        |   SSP     |     
    15          |  |   Port    | <------------------> |   Port    |  |  
    16             |   Driver  |                      |   Driver  |     
    17          |  +-----------+  |                |  +-----------+  |  
    18                   A                                  A           
    19          + - - - -|- - - - +                + - - - -|- - - - +  
    20                   |                                  |           
    21                   V                                  V           
    22               +------+----------------------------+------+       
    23               | Port |                            | Port |       
    24               + -  - +                            + -  - +       
    25               |        Unibus, Q-Bus, BI, or XMI         |       
    26               +------------------------------------------+       

    27        Figure 1-1:  Example  Storage  Systems   Port   Based   DSA
    28                     Subsystem

    29     1.2  Host/Controller Communications Overview

    30     As mentioned earlier, message communications  and  data  transfer
    31     take  place  between  processes  resident  in  the  host  and the
    32     controller over a logical  path  known  as  a  connection.   Each
    33     connection  supported  by  the  controller  allows communications
    34     between the host and a specific device or  service  class  (e.g.,
    35     disk or tape) supported by the controller.

                   

    36     Because  the  communications  mechanism  is  a  point  to   point
    37     interconnect and because the controller knows the class of device
    38     that it controls, the port is integral with the controller.  This
    39     allows  the  controller to enable its connections as a group when
    40     it is initialized.  The  host,  on  the  other  hand,  must  make
    41     provisions   for  the  necessary  connections  either  at  system
    42     generation or at system configuration time.




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           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           INTRODUCTION                                             Page 1-4
           Host/Controller Communications Overview           9 November 1989


     1     Connections are terminated when the controller enters  the  fatal
     2     error  state  or when the host reinitializes the controller.  The
     3     controller always terminates its connections as a group.

     4     When a connection is terminated, all  outstanding  communications
     5     on  that  connection  must  be  discarded;  that is, the receiver
     6     "throws away" all unacknowledged messages  and  the  sender  must
     7     "forget" that such messages have been sent.

     8     The following three types  of  service  are  available  across  a
     9     connection:

    10          1.  Sequential Message

    11          2.  Datagram

    12          3.  Block Data Transfer


    13     The Sequential Message service guarantees that messages  will  be
    14     received   in   the   order  they  were  sent,  without  loss  or
    15     duplication.  If the controller determines that these  guarantees
    16     cannot be met, or if it cannot deliver a message, it will enter a
    17     fatal error state and all connections will be terminated.

    18     The Datagram  service  allows  the  transmission  of  independent
    19     information  units  (datagrams) over a connection.  Delivery of a
    20     datagram occurs with high probability,  but  is  not  guaranteed.
    21     Also,  the  delivery  of  duplicate  datagrams  or  the  order of
    22     delivery of  a  series  of  datagrams  is  not  guaranteed.   The
    23     probability  of  such  occurrences  is required to be "very low,"
    24     however.  Because of the physical interconnect used, the  Storage
    25     Systems  Port  itself will never be the cause of such occurrences
    26     so that, if the processes do make such guarantees for  datagrams,
    27     the  Datagram  Service  of  the  port  would be equivalent to the
    28     Sequential Message service.

    29     The Block Data Transfer service moves data between a  named  host
    30     buffer and the controller.  The host buffer name presented to the
    31     controller is the starting host memory address (byte  0)  of  the
    32     buffer.   Because the host does not directly participate in Block
    33     Data transfers, the host is not  aware  of  any  controller  data
    34     buffers.

    35     Flow control is the method by which the  message  flow  from  the
    36     sender  to  the  receiver  is  controlled.   Information  flow is
    37     controlled by a credit based protocol that  inhibits  the  sender
    38     from  sending messages (and by implication, block data) until the
    39     receiver has provided a buffer to receive  the  information.   In
    40     the  Storage  Systems  Port,  flow  control is not applied to the


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           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           INTRODUCTION                                             Page 1-5
           Host/Controller Communications Overview           9 November 1989


     1     datagram service.  As a result, a datagram may be discarded if  a
     2     buffer  is  not  available  for the datagram.  The message credit
     3     protocol used by the Storage Systems Port is described in  detail
     4     in Section 2.3.3, "Message Credits." 

     5     1.3  Purpose

     6     The purpose of this document is to  provide  information  on  the
     7     port  access  protocol  of the Storage Systems Port to the detail
     8     necessary for writing a Storage Systems Port driver.

     9     1.4  Scope

    10     The scope of this document is  limited  to  the  details  of  the
    11     Storage  Systems  Port  itself.   It does not assume any specific
    12     type of host processor or operating system.  It does  not  assume
    13     any particular controller.



































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           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           STORAGE SYSTEMS PORT ARCHITECTURE                        Page 2-1
                                                             9 November 1989


     1                                 CHAPTER 2

     2                     STORAGE SYSTEMS PORT ARCHITECTURE


     3     2.1  Overview

     4     The   Storage   Systems   Port   has   the   following    general
     5     characteristics:

     6          1.  Provides,  at  initialization  time,   information   for
     7              verifying correct operation of the controller.

     8          2.  Allows  for  parallel  operation  of  multiple   devices
     9              attached  to  the  controller,  with  full  duplexing of
    10              operation initiation and completion signals, and of data
    11              transfers.

    12          3.  Minimizes host interrupts during peak I/O loads.

    13     The   Storage   Systems   Port   has   the   following   specific
    14     characteristics:

    15          1.  Communication is always between a host and a controller.

    16          2.  The controller is implemented such that it  assumes  all
    17              host data buffers are in host physical memory and that a
    18              data  buffer  occupies  contiguous  physical   locations
    19              within  the host's address space.  The controller may be
    20              designed with additional functionality that allows it to
    21              transfer  data  to  a  noncontiguous  host  buffer using
    22              virtual to physical address conversion as defined  later
    23              in this specification.

    24          3.  The  host  does  not  directly  initiate  a  block  data
    25              transfer.   Block data transfer requests are embedded in
    26              the higher level protocol messages sent from the host to
    27              the controller.

    28     The port consists of two layers:

    29          1.  The Physical Layer:  The physical layer is the mechanism
    30              that  transmits data and bus control signals between the
    31              host and the  controller.   This  layer  is  implemented
    32              using the Unibus, Q-Bus, BI, or XMI and the specific bus
    33              interface logic in both the host and the controller.

    34          2.  The Logical Layer:  The logical layer  consists  of  the
    35              port  protocol  and the shared port data structures that
    36              are located in a communications area within host memory.


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           STORAGE SYSTEMS PORT ARCHITECTURE                        Page 2-2
           Overview                                          9 November 1989


     1              The data structures are operated on by both the host and
     2              controller according to a set of formal rules which  are
     3              discussed later.

     4              The host is responsible for providing  a  logical  layer
     5              interface process (port driver) between the higher level
     6              protocol process (class driver) and  the  port  physical
     7              layer.

     8     The port  design  assumes  that  the  higher  level  protocol  is
     9     asynchronous and message packet-oriented.

    10     The host and the controller use a communications area located  in
    11     host  memory  to  exchange messages.  The controller examines the
    12     communications  area  for  commands;  the   host   examines   the
    13     communications area for responses and datagrams.  From the host's
    14     viewpoint, an operation begins when the host deposits  a  command
    15     packet  in  the  communications  area.  The operation is complete
    16     when a corresponding response packet is removed by the host  from
    17     the communications area.

    18     The host uses I/O page registers  for  physical  control  of  the
    19     controller.   The  transmission  of messages and data between the
    20     host and  the  controller  is  accomplished  via  DMA  operations
    21     initiated by the controller.

    22     Interrupts generated by the controller  signal  events  concerned
    23     with  the  operation  of  the  port and do not directly represent
    24     events of the I/O devices attached to the controller.

    25     The controller transfers  data  to  physical  locations  in  host
    26     memory.   As  mentioned  above, the controller may be designed to
    27     perform virtual to physical address translation, if  directed  by
    28     the  host,  for  data  transfers.   This  address mapping must be
    29     explicitly  enabled  for  each  data  transfer.   Access  to  the
    30     communications  area by the controller is always to physical host
    31     memory locations.  Access to the communications area includes the
    32     transfer of command and response packets.

    33     2.2  Physical Layer

    34     2.2.1  Characteristics

    35     The physical layer is  the  Unibus,  Q-Bus,  BI,or  XMI  and  any
    36     associated  host  based or controller based logic for adapting to
    37     the bus and has the following characteristics:

    38          1.  Conforms to DEC STANDARD 158 (Unibus specification), DEC
    39              STANDARD  160  (LSI-11  Bus Specification), DEC STANDARD
    40              057 (VAXBI Standard),  or  Calypso  Memory  Interconnect


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           STORAGE SYSTEMS PORT ARCHITECTURE                        Page 2-3
           Physical Layer                                    9 November 1989


     1              (XMI) Specification.

     2          2.  Allows   repeated   access   (reads,   writes   or   any
     3              combination) to the same host memory location.


     4     2.2.2  Requirements

     5     The host resident port interface software (port driver)  and  the
     6     controller  shall  provide  the  following physical layer control
     7     facilities:

     8          1.  Transmission of commands and responses.

     9          2.  Sequential delivery  of  commands:   Commands  shall  be
    10              fetched  by  the  controller  in the order in which they
    11              were queued to the transport mechanism.

    12          3.  Asynchronous communication:  Responses may be sent in an
    13              order different from that of the triggering commands.

    14          4.  Unsolicited  responses:    The   controller   may   send
    15              unsolicited  messages  at  any  time, assuming they have
    16              been enabled.  The enabling mechanism  and  the  message
    17              formats/semantics    depend    on    a    higher   level
    18              command/response protocol.

    19          5.  Full  duplex  communication:   A  command,  response  or
    20              unsolicited response may occur at any time.

    21          6.  Port failure recovery:  The host shall place a timer  on
    22              the  controller,  and  shall be able to reinitialize the
    23              controller in the event of a timeout.

    24     The controller shall enter a fatal error state if  a  command  or
    25     response  is  lost  and  it  cannot notify a higher level of host
    26     software.

    27     2.2.3  I/O Page Registers

    28     Two 16-bit registers in the I/O page are used for control of  the
    29     controller.   These  registers  are  always  written  and read as
    30     words.  The behavior of byte aligned transfers to  the  I/O  page
    31     registers  is  undefined.  The register pair begins on a longword
    32     boundary within the I/O page.  The register names, addresses  and
    33     functions are:

    34             IP  7xxxx0/4        initialization and "polling"
    35             SA  7xxxx2/6        status, address and purge   



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     1     The IP register has two functions:

     2          1.  When   written   with   any   value,   causes   a   hard
     3              initialization of the port and the controller to occur.

     4          2.  When read by the host and a connection between the  host
     5              and  controller exists, causes the controller to examine
     6              the  current  location  of  the  command  queue  in  the
     7              communications   area  for  commands,  as  discussed  in
     8              Section 2.3.4, "Message Transmission."   Note  that  the
     9              term "polling" is used in parts of this specification to
    10              describe the controller's access of the command queue.

    11              When read by the host and a connection between the  host
    12              and  controller  does  not  exist, the device controller
    13              shall ignore the IP register read.


    14     The SA register has four functions:

    15          1.  When read by the host during initialization, it contains
    16              data    and    error   information   relating   to   the
    17              initialization process.

    18          2.  When written  by  the  host  during  initialization,  it
    19              communicates host specific parameters to the controller.

    20          3.  When read  by  the  host  during  normal  operation,  it
    21              contains status information, such as controller detected
    22              fatal errors.  The host shall examine  the  controller's
    23              SA   register  regularly  to  verify  normal  controller
    24              operation.  A controller self detected  fatal  error  is
    25              reported  in  the  SA  register  as discussed in Section
    26              2.3.9, "Self Detected Fatal Port/Controller Errors." 

    27          4.  When   written   with   zeros   by   the   host   during
    28              initialization  step  3  and during normal operation, it
    29              signals that the host has successfully completed  a  bus
    30              adapter   purge  in  response  to  a  request  from  the
    31              controller.

                   

    32     The detailed use of the IP  and  SA  registers  is  discussed  in
    33     Section 3.2, "Initialization Details." 







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     1     2.3  Logical Layer

     2     2.3.1  Host/Controller Communications Area

     3     The communications area  resides  in  host  physical  memory  and
     4     consists of two sections:

     5          1.  A header section.  The header section contains interrupt
     6              indicators.  A portion of this section is used to signal
     7              the host that the controller requires repeated access to
     8              the  same  memory  location  when  the  host  has  a bus
     9              adapter.

    10          2.  A response and command queue  section.   Each  queue  is
    11              implemented  as a longword vector containing descriptors
    12              that reference  response  or  command  message  buffers.
    13              Both  the  command  and  response  queues  are  circular
    14              queues, accessed by both the host  and  the  controller.
    15              Strictly   speaking   these   queues  should  be  called
    16              "receive"  and   "send"   queues   because,   from   the
    17              controller's     viewpoint,     they     are    entirely
    18              general-purpose.   For  clarity,  however,   the   terms
    19              "response" and "command" are used.

    20     The communications area shall be aligned on a word boundary.  Its
    21     layout is shown in Figure 2-1.


























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     1             15             8 7             0                 
     2  |          +---------------+---------------+                
     3  |          |                               | -14            
     4  |          +---- Controller Scratchpad ----+                
     5  |          |                               | -12            
     6  |          +----       Descriptor      ----+                
     7  |          |                               | -10            
     8             +---------------+---------------+                
     9             |        bus dependent          | -8             
    10             +-------------------------------+                
    11             |        bus dependent          | -6             
    12             +---------------+---------------+                
    13             |  command interrupt indicator  | -4             
    14             +---------------+---------------+                
    15             | response interrupt indicator  | -2             
    16             +---------------+---------------+                
    17             |                               | base+0 <------+
    18             +--   response descriptor 1   --+               |
    19             |                               | +2            |
    20             +---------------+---------------+               |
    21             /                               / response      |
    22             /                               / descriptor ---+
    23             /                               / queue         |
    24             +---------------+---------------+               |
    25             |                               |               |
    26             +--   response descriptor n   --+               |
    27             |                               | <-------------+
    28             +---------------+---------------+                
    29             |                               | base+4n <-----+
    30             +--   command descriptor  1   --+               |
    31             |                               |               |
    32             +---------------+---------------+               |
    33             /                               / command       |
    34             /                               / descriptor ---+
    35             /                               / queue         |
    36             +---------------+---------------+               |
    37             |                               |               |
    38             +--   command descriptor  m   --+               |
    39             |                               | <-------------+
    40             +---------------+---------------+                

    41                       Note: n = response queue size
    42                             m = command  queue size

    43                 Figure 2-1:  Communications Area Layout







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     1  |  2.3.1.1  Controller Scratchpad Descriptor

     2  |  The words at offsets -14,-12, and  -10  define  a  host  provided
     3  |  scratchpad  region to be used exclusively by the controller.  The
     4  |  provision of this region  is  optional  and  host  implementation
     5  |  dependent.   If  the  host  supports such a region, then it shall
     6  |  indicate its support by setting the CS bit in the SA register  at
     7  |  the end of Step 4.  (See section 3.2.4 for complete details.)

     8  |  The three words comprising the controller  scratchpad  descriptor
     9  |  are defined as follows:

    10  |               base-14: Size of the scratchpad buffer (in bytes).

    11  |                  -12: Low-order 16 bits of the physical address of
    12  |                      the scratchpad buffer.

    13  |                  -10: High-order 16 bits of the  physical  address
    14  |                      of the scratchpad buffer.

    15  |                      If implemented, the scratchpad  buffer  shall
    16  |                      be  at  least  32  bytes  long (Hexaword) and
    17  |                      aligned on a Hexaword boundary (low four bits
    18  |                      of  the  address  are  zeros).  No controller
    19  |                      shall require more than 32  bytes.   However,
    20  |                      host  operating systems may choose to provide
    21  |                      a larger scratchpad.

    22  |                                          NOTE

    23  |                      Some controller implementations  require  the
    24  |                      presence  of  the optional scratchpad buffer.
    25  |                      Please consult the  controller  specification
    26  |                      for that requirement.

    27     2.3.1.2  Interrupt Indicators

    28     Words [base -8,-6,-4,-2] in the communications area are  used  as
    29     interrupt  indicators.   Words  [base  -8,-6]  have bus dependent
    30     meanings.  The controller loads an indicator with a nonzero value
    31     to   indicate   the  reason  for  the  interrupt.   The  host  is
    32     responsible  for  clearing  an  indicator  when   servicing   the
    33     interrupt associated with an indicator.

    34     The indicators are:

    35                 base-8: For Unibus,  Q-Bus,  and  VAXBI,  unused  and
    36                         reserved.   For  XMI,  PFN-mask  (page  frame
    37                         number mask; see Section 5.4 for details).



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     1                     -6: For VAXBI, unused and reserved.

     2                         For  Unibus  and  Q-bus,  bus  adapter  purge
     3                         request:

     4                             15             8 7             0    
     5                             +---------------+---------------+   
     6                             | adapter chan  |    reserved   | -6
     7                             +-------------------------------+   

     8                         The  nonzero  interrupt  indicator   is   the
     9                         adapter  channel  number  and is contained in
    10                         the  high  order  byte   of   the   interrupt
    11                         indicator;  the  lower  byte of the indicator
    12                         word is unused and is reserved.  The  adapter
    13                         channel number is copied from the data buffer
    14                         descriptor of the command which required  the
    15                         purge.   After  the  host  performs  the  bus
    16                         adapter purge, it signals purge completion by
    17                         writing   zeros   in   the   controller's  SA
    18                         register.

    19                         For XMI, page size indicator  and  bit  flags
    20                         (see Section 5.4 for details):

    21  |                          15             8 7     4 3 2 1 0    
    22  |                          +---------------+-------+-------+   
    23  |                          |    reserved   |  PSI  |U|U|E|H| -6
    24  |                          |               |       |N|N|T|W|   
    25  |                          +-----------------------+-------+   

    26                         where:

    27                             PSI -- Page Size Indicator
    28                             UN  -- Undefined
    29                             ET  -- Enable Transient Error Reporting
    30                             HW  -- Hexaword Write supported, if set

    31                     -4: Command queue made the transition  from  full
    32                         to not-full.

    33                     -2: Response queue made the transition from empty
    34                         to not-empty.

    35     2.3.1.3  Command And Response Queues

    36     The command and response queues are organized as separate vectors
    37     of  longword  message  buffer  descriptors  in the communications
    38     area.  Each message buffer descriptor shall contain, when used, a
    39     host  buffer  name  and  access  control  bits for the descriptor


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     1     entry.  Buffer names are host  physical  memory  addresses  which
     2     point  to  host  command or response message buffers.  Because of
     3     the  level  of  indirection  between  the  command  and  response
     4     descriptor  queues  and  the  data  buffers,  the host is free to
     5     assign buffers anywhere in its physical memory space.

     6     Commands are fetched by the controller in the  order  that  their
     7     descriptors  appear in the command queue.  Responses are returned
     8     to the host in the order that buffer descriptors  appear  in  the
     9     response queue.

    10     Both the host and  the  controller  maintain  pointers  into  the
    11     queues.   The  host  owns and maintains the Tail pointer for each
    12     queue and the controller owns and maintains the Head pointer  for
    13     each  queue.   After  each  queue entry is processed, the pointer
    14     used to access the  queue  is  incremented  by  its  owner.   The
    15     following procedure is used to increment a queue pointer.

    16               pointer := pointer + 1;
    17               pointer := (pointer) MOD (queue_size);

    18     The length of each queue is determined  by  the  relative  speeds
    19     with  which  the  host  and  the  controller generate and process
    20     messages  and  is  unrelated  to  the  controller  command  limit
    21     discussed in Section 2.3.3, "Message Credits."  The host sets the
    22     queue lengths at initialization time as discussed in Section 3.2,
    23     "Initialization Details." 

    24     Command or response message buffer descriptors have the following
    25     format:

    26          31   29                                             0 
    27          +-+-+----------------------------------------------+-+
    28          |o|f|   physical message buffer address (text+0)   |0|
    29          +-+-+----------------------------------------------+-+

    30     where:

    31                       o is the message buffer descriptor  "ownership"
    32                         bit  and  indicates whether the descriptor is
    33                         owned  by  the   host   (o=0)   or   by   the
    34                         controller(o=1).   The "o" bit is used by the
    35                         descriptor access protocol to  interlock  the
    36                         descriptor against premature access by either
    37                         the host or the controller.

    38                       f is the "flag" bit whose  meaning  depends  on
    39                         the  state  of the message buffer descriptor.
    40                         The use of the "f" bit is described below.



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     1                         1.  When the controller returns ownership  of
     2                             a  message buffer descriptor to the host,
     3                             it sets the "f"  bit  (f=1)  to  indicate
     4                             that  it  has  completed  action  on  the
     5                             descriptor.

     6                         2.  If the controller finds the "f"  bit  set
     7                             (f=1)  when  it  acquires  ownership of a
     8                             message buffer descriptor, it generates a
     9                             host  interrupt  if  its  action  on  the
    10                             descriptor causes a queue transition.  (A
    11                             queue  transition  is  either the command
    12                             queue changing from full to  not-full  or
    13                             the response queue changing from empty to
    14                             not-empty.)

    15                             If the controller finds the "f" bit clear
    16                             (f=0)  when  it  acquires  ownership of a
    17                             message buffer descriptor, it  shall  not
    18                             generate  a  host  interrupt, even if its
    19                             action on the descriptor causes  a  queue
    20                             transition.

    21                             The  controller  shall   generate   queue
    22                             transition  interrupts  only  if the host
    23                             enabled transition interrupts during port
    24                             initialization.

    25                   Bit 0 must be zero because the message buffer  base
    26                         must  be  word aligned.  The controller shall
    27                         always assume that bit 0 is zero.

    28     2.3.2  Messages And Message Buffers

    29     The command or response message buffer descriptor points  to  the
    30     message  buffer  base  address.   A Storage Systems Port specific
    31     envelope precedes the message text portion of the message  buffer
    32     and  is accessed by negative offsets from the message buffer base
    33     address, [text+0], as illustrated in the following diagram.   The
    34     message  text  and the port envelope are contiguous in the buffer
    35     provided by the host and form a packet which  is  transferred  to
    36     the  controller.   The buffer the host provides shall be at least
    37     as large as the packet.









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     1                 15             8 7     4 3     0        
     2                 +---------------+-------+-------+       
     3                 |   message length (in bytes)   | -4    
     4                 +---------------+-------+-------+       
     5                 | connection id | msgtyp|credits| -2    
     6                 +---------------+-------+-------+       
     7                 |     MB1       |     MB0       | text+0
     8                 +---------------+---------------+       
     9                 |     MB3       |     MB2       | +2    
    10                 +---------------+---------------+       
    11                 .                               .       
    12                 .                               .       
    13                 .                               .       
    14                 +---------------+---------------+       
    15                 |    MBn-1      |     MBn-2     | +(n-2)
    16                 +---------------+---------------+       

    17     The packet fields are defined below.

    18          message length gives the length  of  the  message  text,  in
    19                         bytes.

    20                         For  commands,  the  message   length   field
    21                         specifies   the  size  of  the  higher  level
    22                         protocol message, in  bytes,  beginning  with
    23                         [text+0].   The  message  length  for a given
    24                         message  is  dictated  by  the  higher  level
    25                         protocol.    The   message  length  field  is
    26                         included in the packet so that the controller
    27                         can  determine the message size without being
    28                         required to  have  knowledge  of  the  higher
    29                         level  protocol.   Using  the  message length
    30                         field, the controller may verify the presence
    31                         of  all  required parameters.  The controller
    32                         may assume that the message packet buffer  is
    33                         equal  to  the maximum message size specified
    34                         by the higher level protocol plus the size of
    35                         the packet envelope fields.

    36                         For responses, the host presets  the  message
    37                         length  field  with the length of the message
    38                         text portion of response buffer.  The minimum
    39                         response  buffer  size the host shall provide
    40                         is 64 bytes, which includes 4 bytes  for  the
    41                         message   envelope.   Before  transmitting  a
    42                         response message, the  controller  reads  the
    43                         message  length field in the response message
    44                         buffer.  If the response  message  is  larger
    45                         than the buffer, the controller truncates its
    46                         response.


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     1                         After the transfer of the  response  message,
     2                         the   controller   loads   the  size  of  the
     3                         transferred message into the  message  length
     4                         field.     The    host,    therefore,   shall
     5                         reinitialize the value of this field for each
     6                         proposed response.

     7                         If a controller's response messages are  less
     8                         than  or equal to 60 bytes, the controller is
     9                         not  required  to  check  the  size  of   the
    10                         response buffer.

    11           connection id identifies the connection serving  as  source
    12                         of,   or  destination  for,  the  message  in
    13                         question.   See  Table  A-1,  "Connection  ID
    14                         Values." 

    15                 credits gives the credit value  associated  with  the
    16                         message,   as  discussed  in  Section  2.3.3,
    17                         "Message Credits." 

    18                  msgtyp indicates the message type, as follows:

    19                            0 - Sequential Message:  The "credits" and
    20                                "message length" fields are valid.

    21                            1 - Datagram:  "Credits"  must  be   zero;
    22                                "message length" is valid.

    23                            2 - Credit   notification:  "Credits"   is
    24                                valid; "message length" must be zero.

    25                            3 - Node  Name  Packet:  This  packet   is
    26                                placed   in   the  response  queue  by
    27                                controllers  that  support  Node  Name
    28                                packets.  "Credits" must be zero.  The
    29                                "connection id" and  "message  length"
    30                                fields  are  valid and the contents of
    31                                the message text shall be as described
    32                                in Section 2.3.11.

    33                         4-14 - Reserved (unassigned)

    34                           15 - Maintenance:  "Credits" is unused  and
    35                                shall be ignored.


    36                      MB is a byte of message text.




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     1     There is no information protection provided for the text  of  the
     2     message   other  than  host  memory  parity,  which  may  not  be
     3     implemented by all host systems.

     4     Command and response buffers shall be contained entirely in  host
     5     physical  memory.  That is, for command buffers, [text-4] through
     6     [text+n] shall be valid host memory addresses ("n" is  determined
     7     by  the  higher  level protocol).  For response buffers, [text-4]
     8     through [text+59] shall all be valid host memory addresses.

     9     2.3.3  Message Credits

    10     The higher level protocol implements a credit based control  flow
    11     mechanism  for  each  connection.   The  "credits"  field  of the
    12     message envelope supports that mechanism as explained below.

    13          1.  In its first response for a  connection  the  controller
    14              shall  return,  in the credits field of that response, a
    15              number N.  This number is one more than the controller's
    16              limit  for  higher  level  protocol  non-Immediate  type
    17              commands.  The "extra" credit allows the host to  always
    18              issue  a  higher  level protocol Immediate type command.
    19              The host higher level protocol class driver is  to  save
    20              the  credit  number  delivered  by the controller in its
    21              "credit account." 

    22              Immediately following initialization of  the  port,  the
    23              host  may  assume that it has been granted one credit by
    24              the controller.  The single credit allows  the  host  to
    25              enter  into an exchange with the controller to determine
    26              the actual number of message credits available.

    27          2.  Each time the host higher level  protocol  class  driver
    28              queues  a  command,  it  subtracts  one  from the host's
    29              message credit total.

    30          3.  Each time the class driver receives a response, it  adds
    31              the  number  contained  in  the  "credits"  field of the
    32              response to its credit total.  For unsolicited  response
    33              messages,  the  "credits" field will be zero; for normal
    34              response messages the credits field will usually be  one
    35              (an exception is discussed below).

    36          4.  If the class driver's credit total has a value  of  one,
    37              the  class  driver  may  issue  only  an  Immediate type
    38              command.  If the credit total is zero, the class  driver
    39              may not issue any commands at all.

    40     Because of the size of  the  "credits"  field,  controllers  with
    41     credit  limits  greater  than  15  cannot return an entire credit


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     1     value in a single response message envelope.   These  controllers
     2     shall  use the "credits" field in as many additional responses as
     3     necessary to notify the host of the credits  available  for  this
     4     connection.

     5     For a well behaved class  driver,  enlarging  the  command  queue
     6     beyond  the  value  N+1 provides no performance benefits; in this
     7     situation command queue  transition  interrupts  will  not  occur
     8     because the class driver will never fill the queue.

     9     2.3.4  Message Transmission

    10     2.3.4.1  Host To Controller

    11     To send a packet to the controller, the host loads a buffer  with
    12     the  packet, places the packet's physical buffer address into the
    13     current command  descriptor,  sets  the  "o"  bit  (o=1)  in  the
    14     descriptor,  and  increments its command queue pointer.  When the
    15     host sets the  "o"  bit,  the  descriptor  is  available  to  the
    16     controller  and  the  host  no longer "owns" the descriptor.  The
    17     controller, in turn, reads the packet address  from  the  current
    18     descriptor,  clears the "o" bit (o=0), and increments its command
    19     queue pointer to the next queue location.  The "o" bit transition
    20     1  -->  0 means that the controller no longer owns the descriptor
    21     and the descriptor is available again for use by the host.

    22     To guarantee that the controller  sees  each  message,  the  host
    23     shall  read  the IP register whenever it inserts a message in the
    24     command queue.  The host's reading of the IP register forces  the
    25     controller  to  process  the command queue.  The controller shall
    26     look at the "o" bit of  the  descriptor  at  the  queue  location
    27     pointed  to  by  the  controller's command queue pointer.  If the
    28     controller finds that that descriptor is owned by the host (o=0),
    29     it  shall  treat  the  host  "command available" signal as a null
    30     signal; otherwise,  the  controller  shall  process  the  message
    31     pointed to by the address value in the descriptor.

    32     2.3.4.2  Controller To Host

    33     To accept a message from the controller,  the  host  allocates  a
    34     message  buffer,  places  the  buffer's physical address into the
    35     current response descriptor,  sets  the  "o"  bit  (o=1)  in  the
    36     descriptor,  and  increments  its  response  queue  pointer.  The
    37     controller, when it is ready to send  a  message,  transfers  the
    38     message  packet to the buffer whose address was obtained from the
    39     current descriptor, clears the "o" bit (o=0) in  the  descriptor,
    40     and  increments  its  response pointer to the next response queue
    41     location.  The "o" bit transition 1 --> 0  means  the  controller
    42     has  transferred  a  message  to  the  host and the controller no
    43     longer owns the descriptor.


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     1     Because of the  possibility  of  unsolicited  messages  from  the
     2     controller,  the  host shall maintain a pointer to the last queue
     3     position used for a message from  the  controller  and  scan  the
     4     queue  from  that  position  to  the  current  position for newly
     5     received messages.

     6     2.3.5  Interrupts

     7     The transmission of a message shall result in a host interrupt if
     8     and  only  if  interrupts were enabled during initialization (see
     9     Section 3.1, "Initialization Overview") and one of the  following
    10     conditions has been met:

    11          1.  The message was a command, its descriptor  "f"  bit  was
    12              set  (f=1),  and the controller's fetching it caused the
    13              command queue to transition from full to not full.  This
    14              interrupt  means that the host may place another command
    15              in the command queue.

    16          2.  The message was a response, its descriptor "f"  bit  was
    17              set (f=1), and the controller's depositing it caused the
    18              response queue to transition from empty  to  not  empty.
    19              This  interrupt  means  that there is a response for the
    20              host to process.

    21          3.  The controller is  connected  to  the  host  via  a  bus
    22              adapter  and  a  command  required  that  the controller
    23              reaccess a given location during  data  transfer.   This
    24              interrupt  means  that the controller is requesting that
    25              the host purge the indicated channel of the bus adapter.


    26     2.3.6  Queue Access

    27     2.3.6.1  Command Queue

    28     When the  host  has  a  command  ready  for  the  controller,  it
    29     performs, in general, the following sequence of operations:

    30          1.  Allocates a command packet buffer.

    31          2.  Loads the command packet into the buffer.

    32          3.  Loads the buffer pointer into the  command  queue  entry
    33              pointed at by its command queue pointer.

    34          4.  Sets the "o" bit (o=1) as required and  sets  or  clears
    35              the "f" bit as desired.




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     1          5.  Increments its command queue pointer using the following
     2              procedure:

     3                        pointer := pointer + 1;
     4                        pointer := pointer MOD (command_queue_size);

     5          6.  Signals the controller that a command (or  commands)  is
     6              available by reading the controller's IP register.

     7     When the host reads the controller's IP register, the  controller
     8     performs, in general, the following sequence of operations:

     9          1.  Reads the command descriptor pointed at by  its  command
    10              queue pointer.

    11          2.  If the command descriptor is owned by the host (o=0) the
    12              controller exits from this sequence of operations.

    13          3.  If the command descriptor is  owned  by  the  controller
    14              (o=1)  the  controller transfers the command packet from
    15              host memory.

    16          4.  The controller returns the command queue  entry  to  the
    17              host  by clearing the "o" bit (o=0) and sets the "f" bit
    18              (f=1).

    19          5.  If returning the command  descriptor  made  the  command
    20              queue  transition  from full to not full and the "f" bit
    21              for the command descriptor was set (f=1)  by  the  host,
    22              the   controller  loads  the  command  queue  transition
    23              indicator (base-4) with a nonzero value and, if enabled,
    24              interrupts  the  host.   Note  that  the  command  queue
    25              transition indicator is set nonzero even  if  interrupts
    26              are  disabled.   Also  note that the host is responsible
    27              for clearing  the  command  queue  transition  indicator
    28              before queuing another command.

    29          6.  Increments its command queue pointer using the following
    30              procedure:

    31                        pointer := pointer + 1;
    32                        pointer := pointer MOD (command_queue_size);

    33          7.  If the controller  has  an  internal  command  buffering
    34              capability,  it  scans the command queue until either no
    35              more commands are available or the controller's internal
    36              command  buffers  have  been  filled.   Controllers  may
    37              optionally report the  latter  condition  as  a  "Credit
    38              Limit  Exceeded"  fatal  port  error (see Section 2.3.9,
    39              "Self Detected Fatal Port/Controller Errors").


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     1     Having ceased scanning the command queue, the controller  resumes
     2     scanning  either  when  it delivers a response to the host or, if
     3     there are no more outstanding responses, when the host reads  the
     4     IP register.

     5     2.3.6.2  Response Queue

     6     When the host is ready to receive a  response  message  from  the
     7     controller, it performs the following sequence of operations:

     8          1.  Allocates a response message buffer.

     9          2.  Loads the buffer size into the "message length" field of
    10              the packet envelope.

    11          3.  Loads the buffer pointer into the response  queue  entry
    12              pointed to by its response queue pointer.

    13          4.  Sets the "o" bit (o=1) as required and  sets  or  clears
    14              the "f" bit as desired.

    15          5.  Increments  its  response  queue   pointer   using   the
    16              following procedure:

    17                        pointer := pointer + 1;
    18                        pointer := pointer MOD (response_queue_size);

    19     When the controller has a response message to send to  the  host,
    20     it performs the following general operations:

    21          1.  Reads the descriptor pointed at by  its  response  queue
    22              pointer.

    23          2.  If the response descriptor is owned by  the  host  (o=0)
    24              the controller exits from this sequence of operations.

    25          3.  If the response descriptor is owned  by  the  controller
    26              (o=1)  the  controller  transfers the response packet to
    27              the referenced response buffer.

    28          4.  The controller returns the response  descriptor  to  the
    29              host  by clearing the "o" bit (o=0) and sets the "f" bit
    30              (f=1).

    31          5.  If returning the response descriptor made response queue
    32              transition  from  empty to not empty and the "f" bit for
    33              the response descriptor was set (f=1) by the  host,  the
    34              controller loads the response queue transition indicator
    35              (base-2)  with  a  nonzero  value   and,   if   enabled,
    36              interrupts  the  host.   Note  that  the  response queue


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     1              transition indicator is set nonzero even  if  interrupts
     2              are  disabled.   Also  note that the host is responsible
     3              for clearing the  response  queue  transition  indicator
     4              before attempting to dequeue a response.

     5          6.  Increments  its  response  queue   pointer   using   the
     6              following procedure:

     7                        pointer := pointer + 1;
     8                        pointer := pointer MOD (response_queue_size);

     9     Response queue access continues until all response messages  have
    10     been  sent  to  the host or the controller does not find any more
    11     empty response descriptors.

    12     2.3.6.3  Additional Requirements

    13     The controller and host  shall  guarantee  that  all  outstanding
    14     writes  (write  buffering)  and  relevant cache invalidates for a
    15     given  command/response  descriptor  entry  are  written   before
    16     changing  the ownership bit of the entry in question.  The way in
    17     which this requirement is met is implementation specific.


    18     Because of the possibility of  unsolicited  responses,  the  host
    19     shall  continue  to scan the response queue after all outstanding
    20     commands  have  been  acknowledged.   An  accumulation  of   such
    21     unsolicited  messages would first saturate the response queue and
    22     then  any  controller  internal  message  buffers,  blocking  the
    23     controller and preventing it from processing additional commands.

    24     The host shall occasionally scan the response queue  even  though
    25     it  may  not  be expecting a response.  The best way to mechanize
    26     this requirement is through  the  use  of  the  queue  transition
    27     interrupt  facility  described  earlier,  supplemented  with  the
    28     advice that the host should remove from  the  response  queue  as
    29     many  responses  as it finds, ceasing scan activity only when the
    30     response queue is found to be empty.

                   

    31     Controller inactivity is a necessary (but insufficient) condition
    32     for  the  host  to  reallocate memory used for the communications
    33     area.  Additional conditions to be met are listed below.

    34          1.  Unsolicited response messages shall be disabled  (higher
    35              level protocol dependent).





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     1          2.  At least 100 milliseconds shall have elapsed  since  the
     2              host last read the IP register.

     3     The controller shall cease accessing the communications area when
     4     it receives a bus or controller initialization signal.

     5     2.3.7  Data Transmission

     6     To support such  higher  level  protocol  functions  as  transfer
     7     restarts,  compares,  etc., the host memory interface shall allow
     8     repeated access to a given host memory location  for  both  reads
     9     and writes.

    10     On systems with bus adapters,  the  repeated  access  requirement
    11     means  that  the  relevant adapter channel may have to be purged,
    12     requiring the active cooperation of  the  host.   The  controller
    13     signals  its  desire  for an adapter channel purge by loading the
    14     adapter  channel  number  into  the  bus  adapter  purge  request
    15     indicator   in   the   communications   area  (base-6)  and  then
    16     interrupting the host.  The host writes zeros to the SA  register
    17     to indicate purge completion.

    18     The port architecture allows the host to specify  the  length  of
    19     each  DMA  bus  access.   The bus access is specified in terms of
    20     longword "bursts" on the bus.  The burst size  varies  in  length
    21     from  1  longword  (4  bytes)  to  32 longwords (128 bytes).  The
    22     default DMA bus access burst is bus dependent and is a controller
    23     implementation characteristic.

    24     In the command queue, the command descriptor points to a  (higher
    25     level protocol) command packet.  Command packets that describe an
    26     operation that requires movement of data to or from  host  memory
    27     contain  a  buffer  descriptor field.  The contents of the buffer
    28     descriptor field point to the buffer in host memory which  is  to
    29     serve  as  the source of or destination for the data to be moved.
    30     The controller moves data to or from the  host  buffer  specified
    31     using the block data transfer (DMA) mechanism.

    32     The  Storage  Systems  Port  permits  two  different   modes   of
    33     addressing for data movement operations:  unmapped and mapped.

    34     In unmapped addressing the controller simply moves the data  into
    35     or out of contiguous physical locations of host memory.

    36     In mapped addressing the data movement is dictated by  a  virtual
    37     to  physical  address  mapping  table.   Before  moving  data the
    38     controller first accesses the mapping table and then computes the
    39     physical  address  of  the  data  source  or destination from the
    40     virtual address supplied.  The mapping table may contain multiple
    41     virtual  address entries each pointing to a different area of the


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     1     host's physical memory.  The resultant host buffer may  therefore
     2     contain   either  contiguous  or  noncontiguous  physical  memory
     3     locations, whichever is desired by the host.

     4     The host selects which addressing mode  the  controller  uses  by
     5     setting  or  clearing  the  "mapped data transfer flag" ("m" bit)
     6     contained in the buffer descriptor field of the  command  packet.
     7     The  "m"  bit  also  determines the size and format of the buffer
     8     descriptor field which varies according to  the  addressing  mode
     9     selected.

    10     Sections 2.3.7.1, "Unmapped Addressing Mode" and 2.3.7.2, "Mapped
    11     Addressing Mode" below describe the buffer descriptor formats and
    12     addressing modes in greater detail.

    13     Note that unmapped addressing mode shall be  implemented  by  all
    14     controllers.   Implementation  of  mapped  addressing  mode  is a
    15     controller dependent option.

    16     2.3.7.1  Unmapped Addressing Mode

    17     The buffer descriptor used for unmapped addressing  mode  is  one
    18     longword and has the following format:

    19          31 30       24 23                                   0 
    20          +-+-----------+--------------------------------------+
    21          |m| adptr chl |            buffer address            |
    22          +-+-----------+--------------------------------------+

    23     where:

    24                       m is the mapped data transfer  flag.   Unmapped
    25                         addressing  mode  is selected by clearing the
    26                         "m" bit (m=0).

    27               adptr chl is a  7  bit  field  that  contains  the  bus
    28                         adapter  channel  number  of the channel that
    29                         the host is  using  for  the  transfer.   The
    30                         adapter  channel  number  is  stored  by  the
    31                         controller and passed back to the  host  when
    32                         the  controller  determines that the transfer
    33                         requires  an  adapter  channel  purge.   This
    34                         field is unused and reserved on systems which
    35                         do not require bus adapter channel purging.

    36          buffer address is the 24 bit physical buffer address for the
    37                         transfer.   This  address  may be an odd byte
    38                         address  if  the  controller  is  capable  of
    39                         performing    odd    byte   transfers.    The
    40                         availability of the odd byte transfer feature


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     1                         is  signaled  to  the  host  during Step 1 of
     2                         initialization by "OD=1" in the SA  register.
     3                         Otherwise the buffer address shall specify an
     4                         even byte address.

     5     2.3.7.2  Mapped Addressing Mode

     6     The buffer descriptor used for  mapped  addressing  mode  is  two
     7     longwords and has the following format (see Section 5.5.2 for XMI
     8     mapped addressing):

     9          31 30                               9 8             0 
    10          +-+----------------------------------+---------------+
    11          |m|         map register index       |     offset    |
    12          +-+-+--------------------------------+---------------+
    13          |mbz|              map register base                 |
    14          +---+------------------------------------------------+
    15          31   29                                             0 

    16     where:

    17                       m is the mapped  data  transfer  flag.   Mapped
    18                         addressing  mode  is  selected by setting the
    19                         "m" bit (m=1).

    20      map register index is a 22 bit field  that  contains  the  index
    21                         into  the  map register table associated with
    22                         the transfer.  The  controller  converts  the
    23                         index  to a longword value by multiplying the
    24                         index by 4.  The  converted  index  value  is
    25                         added  to  the  map  register base address to
    26                         produce the address of the first map register
    27                         assigned to the transfer.

    28                         Each map register in the table maps  no  more
    29                         than  one  page's  data  --  512  bytes.  The
    30                         controller   increments   the   initial   map
    31                         register index value to access subsequent map
    32                         registers during the  transfer.   An  address
    33                         translation  is  required  when  the transfer
    34                         reaches a page boundary.  The incremented map
    35                         register  index  is  the  offset from the map
    36                         register table base to the map register entry
    37                         that  contains  the  page number for the next
    38                         page's transfer.

    39                  offset is the byte offset within the first  page  in
    40                         host memory to be accessed by the transfer.




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     1                         The physical address of the first page of the
     2                         transfer  is  calculated  by  adding the (map
     3                         register index)*4 value to the  map  register
     4                         base  address  and  extracting the Page Frame
     5                         Number from the map register.   The  "offset"
     6                         is  concatenated  to the Page Frame Number to
     7                         create the complete physical  address  to  be
     8                         used.

     9                         The physical address may resolve  to  an  odd
    10                         byte  address if the controller is capable of
    11                         performing   odd   byte    transfers.     The
    12                         availability  of  this feature is signaled to
    13                         the host during Step 1 of  initialization  by
    14                         "OD=1"  in  the  SA  register.  Otherwise the
    15                         buffer address shall  specify  an  even  byte
    16                         address.

    17                         The number of bytes transferred in the  first
    18                         page   is   (512-"offset").   For  subsequent
    19                         pages, the offset value is 0;  that  is,  the
    20                         transfer  begins  on  the  first  byte of the
    21                         page.  512  bytes  are  transferred  in  each
    22                         intermediate   page  of  the  transfer.   The
    23                         number of bytes transferred in the last  page
    24                         is  determined by the remaining transfer byte
    25                         count and may vary from some minimum value to
    26                         a  full  page (512 bytes).  The transfer byte
    27                         count is passed as part of the  higher  level
    28                         protocol.

    29                     mbz Bits 29 and 30 Must Be Zero.

    30       map register base is the 30 bit physical address of the base of
    31                         the  map  register  table associated with the
    32                         transfer.  The map register  table  shall  be
    33                         longword  aligned  and  the  controller shall
    34                         assume that the base address  supplied  is  a
    35                         longword address.

    36                         Figure   2-2,   "Address   Mapping   Process"
    37                         illustrates  the  address mapping process for
    38                         the first transfer.

    39     The format of the host map register is as follows:

    40                31 30            21 20                   0 
    41                +-+----------------+----------------------+
    42                |v|   undefined    |          PFN         |
    43                +-+----------------+----------------------+


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     1                     v=1 The map register contains valid information.

     2                         The  number  of   map   registers   used   is
     3                         determined  by  the  length  of the transfer.
     4                         Each map register maps up  to  512  bytes  of
     5                         host memory.

     6                         Because a mapped transfer requires  a  number
     7                         of  consecutive  map  registers to define the
     8                         transfer, the controller shall terminate  the
     9                         transfer  if  it finds "v=0" in an active map
    10                         register.  The controller  shall  return  the
    11                         appropriate  higher level protocol error code
    12                         in that event if it still has an  outstanding
    13                         transfer count.

    14                     PFN is the page  frame  number  for  the  current
    15                         transfer   fragment  identified  by  the  map
    16                         register.

    17     The  location  of  the  map  register  table  is  passed  to  the
    18     controller  in the second longword of the buffer descriptor.  The
    19     controller shall assume that the map register  table  is  a  host
    20     physical longword address.

    21     Each mapped transfer shall have its own uniquely  identified  map
    22     register  table.   The  map  register  table shall be in physical
    23     memory; that is, it may not be  itself  mapped.   The  controller
    24     shall use unmapped addressing to access the table.  Consequently,
    25     the map register table shall remain in  memory,  at  its  initial
    26     location,  for  the  duration  of  the  transfer.   A transfer is
    27     complete when the controller returns the response packet for  the
    28     command.

    29     The address mapping process in this specification may be used for
    30     all  Storage  Systems  Port  implementations.   It  is the host's
    31     responsibility to ensure that the mapping values that it provides
    32     to  the controller result in valid physical addresses.  It is the
    33     controller's responsibility to verify that any resultant  address
    34     is valid for the connecting bus.

    35     The address mapping process is illustrated in  Figure  2-2.   The
    36     diagram  shows  the  generation  of  the physical address for the
    37     initial page of the transfer.  The mapping process for subsequent
    38     pages  is  identical,  except  that  an  offset  value  of  0  is
    39     concatenated to the extracted  Page  Frame  Number  to  form  the
    40     physical address.





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     1      30                       9 8             0                      
     2     +--------------------------+---------------+  From the 1st buffer
     3     |    map register index    |     offset    |  descriptor longword
     4     +--------------------------+---------------+                     
     5      \____________v___________/ \______v______/                      
     6                   |                    |                             
     7               extracted                |                             
     8          21       |          0         |                             
     9         +---------v-----------+        |                             
    10         |  map register index |        |                             
    11         +---------v-----------+        |                             
    12                   |                    |                             
    13             multiplied by 4            |                             
    14        23         |          1 0       |                             
    15       +-----------v---------+-+-+      |                             
    16       |  map register index |0|0|      |                             
    17       +-----------v---------+-+-+      |                             
    18                   |                    |                             
    19                 plus                   |                             
    20      29           |            0       |                             
    21     +-------------v-------------+      |          From the 2nd buffer
    22     |     map register base     | <----|--------  descriptor longword
    23     +-------------v-------------+      |                             
    24                   |                    |                             
    25           yields address of            |                             
    26                   |                    |                             
    27     +-------------+                    |                             
    28     |    31  20         0              |                             
    29     |   +-+--+-----------+             |                             
    30     |   |                |             |                             
    31     |   +-+--+-----------+             |                             
    32     +-->|v|  |    PFN    |             |                             
    33         +-+--+-----o-----+             |                             
    34         |           \    |             o                             
    35         |            \   |              \                            
    36         +-+--+--------\--+               \                           
    37                        \                  \                          
    38              29         \            9 8   \     0                   
    39              +-----------o------------+-----o-----+  resultant       
    40              |          PFN           |   offset  |  physical        
    41              +------------------------+-----------+  address         

    42                   Figure 2-2:  Address Mapping Process






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     1     2.3.8  Transmission Errors

     2     Six classes of errors are considered in the Storage Systems  Port
     3     Architecture.  They are listed below.

     4          1.  Failure to become Bus Master:  This can  arise  whenever
     5              the  controller  attempts  to access host memory for any
     6              reason.

     7              To deal cleanly with this  condition  before  requesting
     8              the  bus,  the controller always sets up a corresponding
     9              "last fail" response  packet  (see  Section  6.4,  "Last
    10              Fail")   before   actually   requesting  the  bus.   The
    11              controller then requests the bus and waits "forever" for
    12              bus  grant.   Should  the  grant  fail to come, the host
    13              eventually  will   experience   a   timeout   and   will
    14              reinitialize   the   controller.    At   that  time  the
    15              controller shall report the Bus  Master  error  via  the
    16              previously  set up "last fail" response packet, assuming
    17              such packets were enabled during the reinitialization.

    18          2.  Failure to become  Interrupt  Master:   This  can  arise
    19              whenever  the  controller attempts to interrupt the host
    20              for any reason.

    21              The treatment and reporting of this error are  analogous
    22              to those of failure to become Bus Master.

    23          3.  Bus Data Timeout error:  Whether retries  are  performed
    24              is  controller  dependent.   If  they  are, a persistent
    25              error results in differing action depending  on  whether
    26              the offending operation was a control or data transfer.

    27              a.  If a control transfer, the controller  shall  set  a
    28                  failure  code into the SA register and terminate the
    29                  connection with the host.  The controller will  have
    30                  to be reinitialized.

    31              b.  If the controller is accessing  host  memory  during
    32                  the  calculation  of  a  mapped  data  address,  the
    33                  controller shall set a  failure  code  into  the  SA
    34                  register and terminate the connection with the host.
    35                  The controller will have to be reinitialized.

    36              c.  If a data transfer, the controller remains connected
    37                  to  the  host.   The failure is reported to the host
    38                  through the higher level protocol.





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     1          4.  Bus Parity error:  The action here is the  same  as  for
     2              Bus Data Timeout errors.

     3          5.  An Invalid Resultant Data Address:  If, during a  mapped
     4              data   transfer,   the  controller  detects  an  invalid
     5              resultant data address, the controller remains connected
     6              to  the  host  and  reports the error through the higher
     7              level protocol.

     8          6.  Host Memory Parity Error:  If the memory parity error is
     9              detected  during a data transfer, the controller remains
    10              connected to the host.  The parity error is reported  to
    11              the  host  through  the higher level protocol.  A memory
    12              parity error during a queue or  a  packet  access  shall
    13              cause  the  controller  to terminate its connection with
    14              the  host.   The  SA  register  shall  be  set  to   the
    15              appropriate error code.


    16     2.3.9  Self Detected Fatal Port/Controller Errors

    17     In the event of a controller detected fatal error, the controller
    18     posts the following bits in SA:

    19          1.  Bit 15 = 1  Fatal Error Indicator ("ER" bit).

    20          2.  Bits 10-0:  Fatal Error Code.

    21     Port-generic fatal error codes are binary numbers  occupying  the
    22     value range 1-099.  Currently assigned codes are:

    23         001 - Envelope/Packet Read (parity or timeout).
    24         002 - Envelope/Packet Write (parity or timeout).
    25         003 - Controller ROM and RAM parity.
    26         004 - Controller RAM parity.
    27         005 - Controller ROM parity.
    28         006 - Queue Read (parity or timeout).
    29         007 - Queue Write (parity or timeout).
    30         008 - Interrupt Master.
    31         009 - Host Access Timeout (higher level protocol dependent).
    32         010 - Credit Limit  Exceeded  (reporting  this  condition  is
    33               optional).
    34         011 - Bus Master Error.
    35         012 - Diagnostic Controller Fatal Error.
    36         013 - Instruction Loop Timeout.
    37         014 - Invalid Connection Identifier.
    38         015 - Interrupt Write Error.
    39         016 - MAINTENANCE READ/WRITE Invalid Region Identifier.
    40         017 - MAINTENANCE WRITE Load to nonloadable controller.
    41         018 - Controller RAM error (nonparity).


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     1         019 - INIT sequence error.
     2         020 - High level protocol incompatibility error.
     3         021 - Purge/poll hardware failure.
     4         022 - Mapping Register read error (parity or timeout).
     5         023 - Attempt to set data transfer mapping  when  option  not
     6               present.
     7          *  - 099 - Unassigned


     8     Prior to Version 2.1, codes were assigned to specific controllers
     9     in  groups  of  100.   Codes  are  now assigned to controllers in
    10     groups of 50, so that a given  controller  uses  the  code  range
    11     X00-X49  or  X50-X99.   Table B-1, "Port Fatal Error Code Ranges"
    12     contains the code ranges currently assigned.

    13     2.3.10  Port Performance Considerations

    14     As mentioned earlier,  queue  interrupts  are  generated  by  the
    15     controller  when  the  command queue makes the transition full to
    16     not full or when the response queue makes the transition empty to
    17     not empty.

    18     Because a  full  condition  in  either  queue  implies  that  the
    19     intelligence  responsible  for  filling  that queue is blocked in
    20     some way, queue sizes should be specified large  enough  to  keep
    21     the  incidence  of  full queue small.  For the command queue, the
    22     optimal size depends on the latency in the controller's  scanning
    23     of  the  command queue.  For the response queue, the optimal size
    24     depends on the latency in  invoking  the  host  software  process
    25     which  will empty the queue.  The message credit scheme generally
    26     ensures  that  resource  allocation  will  not   increase   these
    27     latencies.

    28     2.3.11  Node Name Packets


    29     This  packet  is  generated  by  controllers  that  support   SCA
    30     compatible  node  names  and  System IDs.  Such controllers shall
    31     report their ability to generate Node Name packets by setting the
    32     "CN"  bit  during  Step  1 of controller initialization and shall
    33     generate the Node Name packet only when the "NN" and "GO" bits of
    34     the  Step  4  response  have  been  set by the host system.  Host
    35     software may request the Node Name packet (i.e., set the "NN" bit
    36     in  Step  4)  only if the controller had indicated its support by
    37     setting the "CN" bit during Step 1.







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     1     Node Name packet format:

     2                       31                             0    
     3                       +-------+---+---+---------------+   
     4                       |conn ID|msg|crd|     length    | -4
     5                       +-------+---+---+-------+-------+   
     6                       |   Xport_addr  |  MBZ  |NN_VERS|  0
     7                       +---------------+-------+-------+   
     8                       |           SEND_SYS            |  4
     9                       +-------+-------+               |   
    10                       | rsvd  | PRTVRS|               |   
    11                       +-------+-------+---------------+   
    12                       |   MAX_MSG     |     MAX_DG    | 12
    13                       +---------------+---------------+   
    14                       |            SW_TYPE            | 16
    15                       +-------------------------------+   
    16                       |          SW_VERSION           | 20
    17                       +-------------------------------+   
    18                       |                               | 24
    19                       |        SW_INCARNATION         |   
    20                       |                               |   
    21                       +-------------------------------+   
    22                       |            HW_TYPE            | 32
    23                       +-------------------------------+   
    24                       |                               | 36
    25                       |                               |   
    26                       |          HW_VERSION           |   
    27                       |                               |   
    28                       |                               |   
    29                       +-------------------------------+   
    30                       |                               | 48
    31                       |           NODE_NAME           |   
    32                       |                               |   
    33                       +-------------------------------+   
    34                       |                               | 56
    35                       |           CUR_TIME            |   
    36                       |                               |   
    37                       +-------------------------------+   
    38                       |           MAINT_ID            | 64
    39                       +-------------------------------+   
    40                       |           CODE_REV            | 68
    41                       +-------------------------------+   
    42                       |           PORT_FCN            | 72
    43                       +-------------------------------+   
    44                       |           SYS_STATE           | 76
    45                       +-------------------------------+   
    46                       |                               | 80
    47                       |         PORT_FCN_EXT          |   
    48                       |                               |   
    49                       +-------------------------------+   


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     1     length

     2         The length of the Node Name packet in bytes.   Equal  to  88.
     3         As  described  in  Section  2.3.2 if the length of the buffer
     4         provided by the host is less than 92 bytes (message text plus
     5         envelope), the controller shall truncate its response.

     6     crd

     7         Zero.

     8     msg

     9         Three, indicating this is a Node Name packet.

    10     conn ID

    11         Zero if the controller supports only Disk MSCP.  One  if  the
    12         controller  supports  only  Tape  MSCP.   If  the  controller
    13         supports both Disk and Tape MSCP, either value (0 or  1)  may
    14         be used.

    15     NN_VERS

    16         Node Name Version Number.  Must be one.  Host software  shall
    17         ignore  the contents of the Node Name packet if this value is
    18         not one.

    19     MBZ

    20         Zero.

    21     Xport_addr

    22         Transport Address of the remote node.

    23     SEND_SYS

    24         48 bit system address of the remote node.

    25     PRTVRS

    26         SCA Protocol Version number.

    27     MAX_DG

    28         Maximum size in bytes of an application datagram supported at
    29         the remote node.

    30     MAX_MSG


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     1         Maximum size in bytes of an application message supported  at
     2         the remote node.

     3     SW_TYPE

     4         The type of software in the remote node.

     5     SW_VERSION

     6         The version number of the software in the system.

     7     SW_INCAR

     8         Incarnation number of the software  in  the  remote  node  (8
     9         bytes).

    10     HW_TYPE

    11         The type of hardware in the remote node.

    12     HW_VERS

    13         Hardware version number of the remote node (12 bytes).

    14     NODE_NAME

    15         The ASCII node name of the  remote  node  at  this  transport
    16         address (8 bytes).

    17     CUR_TIME

    18         Current time in the remote node (8 bytes).

    19     MAINT_ID

    20         Port Identification number of the remote node.

    21     CODE_REV

    22         Code revision number of the port firmware.

    23     PORT_FCN

    24         Supported Port Functionality.  The values are as  defined  in
    25         Appendix D of the CI Specification (DEC STD 161).

    26     SYS_STATE

    27         Miscellaneous port and controller state information.  Certain
    28         fields  are  defined  below.  The remainder is implementation


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     1         specific.

     2                              15         10 9 8 7            0    
     3                               +----------+---+-+--------------+   
     4                               | reserved |PS |M|   RST_PORT   | 76
     5                               +----------+---+-+--------------+   
     6                               |          reserved             | 78
     7                               +-------------------------------+   


     8     RST_PORT

     9         Transport Address of the port that last reset this node.

    10     M

    11         MNT:  Denotes if maintenance is enabled in this node.

    12     PS

    13         PT_ST:  Port State.  Current state of the port.

    14             PT_ST = 0 for Uninitialized

    15             PT_ST = 1 for Disabled

    16             PT_ST = 2 for Enabled

    17             PT_ST = 3 Reserved

    18     PORT_FCN_EXT

    19         Port Functionality Extension.  Certain fields are as  defined
    20         below.

    21                                1 1 1 1 1 1                        
    22                                5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0    
    23                               +-----+-------------------------+   
    24                               |rsvd |          MBL            | 80
    25                               +-----+-------------------------+   
    26                               |          reserved             | 82
    27                               +-+-+---------------------------+   
    28                               |R|F|        reserved           | 84
    29                               +-+-+---------------------------+   
    30                               |          reserved             | 86
    31                               +-------------------------------+   

    32     MBL

    33         Maximum Body Length.  This value defines the  maximum  number


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     1         of bytes in a packet body supported in the remote node.

     2     R

     3         Reserved.

     4     F

     5         FSN:  Full  Sequence  Number   supported.    Must   be   one,
     6         indicating  that  the  remote  node  supports  3 bit sequence
     7         numbers.

     8                                   NOTE

     9     Bytes "text+4" through "text+63" are copied  unaltered  from  the
    10     first  60  bytes of START/STACK data in a START or STACK datagram
    11     received from the remote node.  The format and meaning  of  these
    12     fields  is  defined in Section 9.1 of the SCA specification; they
    13     are shown here solely for reference purposes.  The  format  shown
    14     above  reflects  version  V7.0D  of  that  specification, dated 1
    15     February 1988, which is the latest revision of that  document  at
    16     the  time  of  writing.   Any changes to the SCA START/STACK data
    17     format will be reflected above as an editorial change without any
    18     formal ECO to this specification.

    19     Bytes "text+64 through "text+87" are copied unaltered from  bytes
    20     T+8  through  T+31  inclusive  of  an ID packet received from the
    21     remote node.  The format and meaning of these fields are  defined
    22     in  the CI Specification, DEC STD 161; they are shown here solely
    23     for reference purposes.  The format shown above reflects ECO 2 to
    24     Revision  A  of that specification; no up to date version of that
    25     document exists at the time of writing.  Any changes  to  the  ID
    26     packet  format  will  be  reflected  above as an editorial change
    27     without any formal ECO to this specification.


















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           PORT/CONTROLLER INITIALIZATION                           Page 3-1
                                                             9 November 1989


     1                                 CHAPTER 3

     2                      PORT/CONTROLLER INITIALIZATION


     3     3.1  Initialization Overview

     4     The initialization procedure serves the following purposes:

     5          1.  Identifies  the  parameters   of   the   host   resident
     6              communications area to the controller.

     7          2.  Provides  a  confidence   check   of   controller,   DMA
     8              mechanism, and communications area integrity.

     9          3.  Establishes a logical connection between  the  host  and
    10              the  controller  -- i.e., brings the controller "online"
    11              to the host.  Note that this action does not  bring  the
    12              devices online to the controller.

    13     The initialization procedure begins with  a  hard  initialization
    14     from  the  host:   writing  the IP register or issuing a Bus Init
    15     (see Sections 4.4.2.1 and 5.3.1 for details of BI  and  XMI  hard
    16     initialization).    Following   the   hard   initialization,  the
    17     controller runs preliminary diagnostics.   If  these  diagnostics
    18     fail,  the  host  is to retry initialization.  If the diagnostics
    19     succeed, the following  4  steps  are  performed,  using  the  SA
    20     register for all communications:

    21          1.  The controller signals the beginning  of  Step  1.   The
    22              host  reads  the  controller  characteristics  and  then
    23              writes the command and response queue lengths, indicates
    24              whether   interrupts   are   to   be   enabled  for  the
    25              initialization, and if so, the address of the  interrupt
    26              vector.   The  controller  then runs a complete internal
    27              integrity check and signals either success or failure.

    28          2.  The controller signals the transition to  Step  2.   The
    29              host  reads  the  port type and the echo of queue length
    30              information it  provided  in  Step  1.   The  host  then
    31              indicates  whether  it requires adapter purge interrupts
    32              and writes the low order portion of  the  communications
    33              area base address.

    34          3.  The controller signals the transition to  Step  3.   The
    35              host reads the echo of interrupt information it provided
    36              in Step 1.  The host then writes the high order  portion
    37              of  the  communications  area  base address as well as a
    38              signal that conditionally triggers an immediate test  of
    39              the  adapter  purge  and  queue  access functions of the


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     1              controller.

     2              The controller then tests the ability of the I/O bus  to
     3              perform  DMA transfers and performs a memory test of the
     4              communications area.  Following successful completion of
     5              the  test,  the  controller  clears  (zeros)  the entire
     6              communications area.

     7          4.  The controller signals the transition to  Step  4.   The
     8              host  reads  the  controller  model number and microcode
     9              version.  The host then writes the allowable burst  size
    10              and indicates whether the controller should send a "last
    11              fail"  response   packet.    The   host   provides   the
    12              appropriate  number  of  valid  response descriptors and
    13              then signals the  controller  that  is  ready  to  begin
    14              normal operations.

    15     At each step the controller informs the host  of  either  failure
    16     (requiring  a  restart of the initialization sequence) or success
    17     (and therefore willingness to progress to the next initialization
    18     step).   The  host  maintains  timeouts on the various controller
    19     responses.

                   

    20     3.2  Initialization Details

    21     During initialization, the detailed format and meaning of the  SA
    22     register  depends  on  the  initialization step and whether SA is
    23     being read or written.

    24     When being read, certain bits  of  the  SA  register  format  are
    25     constant  and  apply to all steps.  The layout of the SA register
    26     is:

    27                     15      11 10                  0 
    28                     +-+-+-+-+-+---------------------+
    29                     |E|S|S|S|S|    interpretation   |
    30                     |R|4|3|2|1|       varies        |
    31                     +-+-+-+-+-+---------------------+

    32     The data portion of the SA  register  (bits  10-0)  is  qualified
    33     either  by the "ER" bit (bit 15) or by one of the step bits (bits
    34     14-11).  The contents of the SA register  are  undefined  if  the
    35     "ER" bit is clear and a step bit is not set.

    36     The bits S1-S4 are set separately by the controller  to  indicate
    37     which step it is ready to perform.  If the host detects more than
    38     one S-bit set at any time, it should reinitialize the controller.
    39     If  this  happens  a second time, the host should assume that the


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     1     controller has failed.

     2     If ER=1, then either  a  controller  based  diagnostic  test  has
     3     failed  or  there  has  been a fatal error.  Bits 10-0 display an
     4     error  code  which  may  be  either  port-generic  or  controller
     5     dependent.     See    Section   2.3.9,   "Self   Detected   Fatal
     6     Port/Controller Errors."

     7     If ER=1 and a step bit is set, then a fatal  error  was  detected
     8     during initialization.  If ER=1 and all step bits are clear, then
     9     a fatal error was detected during normal operation.

    10     In the event of an initialization error, the host shall retry the
    11     sequence  at  least once.  If initialization fails a second time,
    12     the host should assume that the controller has failed.

    13     During both initialization and normal operation, port errors  are
    14     always posted in the SA register as described above.

    15     The host begins the initialization sequence either by  issuing  a
    16     bus INIT or by writing any value to the IP register (see Sections
    17     4.4.2.1 and 5.3.1 for BI and XMI  hard  initialization  details).
    18     The  controller  shall guarantee that the host will read zeros in
    19     the SA register on  the  next  bus  cycle.   Initialization  then
    20     sequences through Steps 1-4 as described on the following pages.

    21     At the beginning of Step n, the controller shall clear  bit  Sn-1
    22     before  setting bit Sn so that the host will never see bits Sn-1,
    23     Sn set simultaneously.

    24     From the host's viewpoint, Step n is defined to have  begun  when
    25     reading  the  SA  register  shows  the  transition  Sn 0-->1.  Of
    26     course, Step n ends when Step n+1 begins as just  defined.   This
    27     transition  from  Step  n  to  Step  n+1 may be accompanied by an
    28     interrupt, depending  on  whether  interrupts  are  enabled.   If
    29     interrupts  are  enabled,  the  controller  is  not  required  to
    30     synchronize its interrupts with the Sn 0-->1 transition.

    31     Steps 1-3 each are required to complete within  10  seconds.   If
    32     any  of  these  steps  fails to complete within that period, this
    33     shall be treated as a host detected fatal error.

    34     There is no explicit signal for the completion of  Step  4.   The
    35     host simply observes that controller operation has begun.

    36     Following an initialization interrupt, the host shall wait  until
    37     either the "ER" bit or a step bit is set by the controller before
    38     utilizing the contents of the SA register.  The controller  shall
    39     ensure  that one of the above bits is set within the bus-specific
    40     timeout period following  the  interrupt.   For  the  Unibus  and


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     1     Q-Bus,  that  period is 100 microseconds.  For the BI and XMI, it
     2     is 10 seconds.

     3     To eliminate the possibility  of  erroneous  decisions  that  can
     4     occur  if  the host reads the SA register simultaneously with the
     5     controller's updating it, the controller shall use the  following
     6     sequence for loading the SA register:

     7          1.  Load the SA register data bits.

     8          2.  Clear the current step bit.

     9          3.  Set either the "ER" bit or the next step bit.

    10     Assuming that  "ER"  continues  to  be  zero,  the  remainder  of
    11     initialization is as described in the following sections.

    12     3.2.1  Standard Initialization Step 1

    13     Step 1 begins when S1 makes the transition 0-->1.  At  that  time
    14     the following pattern is present in the SA register:

    15                             S1                       
    16                              |                       
    17  |                  15       v|10  8 7 6 5 4       0 
    18  |                  +-+-+-+-+-+-+-+-+-+-+-+-+-------+
    19  |                  |E|0|0|0|1|N|Q|D|O|M|S|C|  rsvd |
    20  |                  |R| | | | |V|B|I|D|P|M|N|       |
    21  |                  +-+-+-+-+-+-+-+-+-+-+-+-+-------+

    22     This pattern shall appear within the bus-specific timeout  period
    23     after the hard initialize (100 microseconds for Unibus and Q-Bus,
    24  |  10 seconds for BI and XMI).  Bits 10-4 are controller  dependent.
    25     Their interpretations are listed below.

    26                    NV=1 means that the controller does not support  a
    27                         host-settable interrupt vector address.

    28                    QB=1 means that the controller supports  a  22-bit
    29                         QBUS.

    30                    DI=1 means that the controller implements enhanced
    31                         diagnostics -- i.e., wraparound and purge and
    32                         poll tests.  See  Sections  6.1,  "Diagnostic
    33                         Wrap  Mode"  and 6.2, "Purge and Poll Tests,"
    34                         respectively.

    35                    OD=1 means that the  controller  allows  odd  host
    36                         addresses  to  be  specified  in  the  buffer
    37                         descriptor.


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     1                    MP=1 means that the  controller  supports  address
     2                         mapping.   The  host  supplies a virtual data
     3                         address in the  buffer  descriptor  which  is
     4                         mapped  to a resultant physical address using
     5                         mapping registers maintained in host  memory.
     6                         See   Section   2.3.7.2,  "Mapped  Addressing
     7                         Mode." 

     8                    SM=1 means that the  controller  supports  Special
     9                         Function  Mode.  That is, expanded controller
    10                         specific   functions   (e.g.,    loop-on-test
    11                         diagnostics)    are    available    on   this
    12                         controller.

    13  |                      Note that the host may, at its option,  enter
    14  |                      Special  Function  Mode  by writing a special
    15  |                      pattern into  the  SA  during  initialization
    16  |                      Step 4.  The standard initialization sequence
    17  |                      (Step 1 through the transition to Step 4)  is
    18  |                      followed  up to that point.  See Section 6.5,
    19  |                      "Special Function Mode" for complete details.

    20                    CN=1 means that the controller supports Node  Name
    21                         packets as described in Section 2.3.3.


    22     When the host recognizes the S1 bit's transition, it responds  by
    23     writing the following into the SA register:

    24                     15   13 11 10  8 7 6           0 
    25                     +-+-+-----+-----+-+-------------+
    26                     |1|W|c que|r que|I| int vector  |
    27                     | |R| lng | lng |E| (address/4) |
    28                     +-+-+-----+-----+-+-------------+

    29     Note that bit 15=1.  This is to  guarantee  that  the  controller
    30     does not interpret the pattern as a host "adapter purge complete"
    31     response (after a spontaneous reinitialize).
                   


    32     The remainder of the  host  generated  Step  1  SA  register  bit
    33     pattern has this interpretation:

    34                    WR=1 means  that  the  controller   should   enter
    35                         Diagnostic   Wrap   Mode.    (The  controller
    36                         ignores  WR  if  it  delivered  DI=0  at  the
    37                         beginning of Step 1.)

    38                         Note that entering Diagnostic Wrap Mode is  a


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     1                         deviation  from  the  standard initialization
     2                         sequence,  beginning  after  the  Step  1  SA
     3                         pattern  written  by  the  host.  See Section
     4                         6.1,  "Diagnostic  Wrap  Mode"  for  complete
     5                         details.

     6               c que lng is the number of descriptors (32  bits  each)
     7                         in the command queue, expressed as a power of
     8                         two.  Thus for a maximum  command  queue  the
     9                         host  would  set  this  field equal to seven,
    10                         indicating 2**7 (128) descriptors.

    11               r que lng is the number of response queue  descriptors,
    12                         again expressed as a power of two.

    13                    IE=1 means  that  the  host   is   requesting   an
    14                         interrupt  at the completion of each of Steps
    15                         1-3.

    16                         Note that no interrupt will be  generated  at
    17                         the completion of Step 4.

    18              int vector determines if interrupts will be generated by
    19                         the  controller.   If  this field is nonzero,
    20                         interrupts will be  generated  during  normal
    21                         operation     and,     if     IE=1,    during
    22                         initialization.  If this field is zero,  then
    23                         interrupts   will  not  be  generated  during
    24                         normal    operation    nor     initialization
    25                         (regardless  of  the  "IE"  bit state).  When
    26                         nonzero, those controllers  which  accept  an
    27                         interrupt  vector from the host use the value
    28                         in  the  field  as  the  address/4   of   the
    29                         interrupt vector.


    30     Upon receipt of the above data the controller begins running  its
    31     integrity  check  diagnostics.   When  finished,  the  controller
    32     conditionally  interrupts  the  host  as  described  above.    If
    33     enabled,  the  interrupt  will take place whether the diagnostics
    34     succeed or fail.

    35     Step 1 shall complete within 10 seconds after the host writes  to
    36     the  SA register.  The completion shall result in an interrupt if
    37     the IE bit had been set in Step 1.







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           Initialization Details                            9 November 1989


     1     3.2.2  Standard Initialization Step 2

     2     Step 2 begins when S2 makes the transition 0-->1.  At  that  time
     3     the following pattern is present in the SA register:

     4                           S2                         
     5                            |                         
     6                     15     V   10  8 7 6 5   3 2   0 
     7                     +-+-+-+-+-+-----+-+-+-----+-----+
     8                     |E|0|0|1|0|port |1|W|c que|r que|
     9                     |R| | | | |type | |R| lng | lng |
    10                     +-+-+-+-+-+-----+-+-+-----+-----+

    11     Bits 10-8 define the port type.  All  controllers  conforming  to
    12     this  port specification shall use the value assigned to "Storage
    13     Systems Port" (see Table A-2 for currently assigned port values).

    14     Bits 7-0 are echoes of the data written by the  host  to  the  SA
    15     register bits 15-8 during Step 1.

    16     The host responds to the  S2  bit's  transition  by  writing  the
    17     following into the SA register:

    18                     15                           1 0 
    19                     +-----------------------------+-+
    20                     |         commbase low        |P|
    21                     |           address           |I|
    22                     +-----------------------------+-+

    23     This pattern has the following interpretation:

    24            commbase low is the low  order  portion  of  the  physical
    25                         address  of  [base+0]  of  the communications
    26                         area.  This is a word address; the low  order
    27                         bit is zero implicitly.

    28                         The high order portion  of  this  address  is
    29                         written  into  the  SA  register  by the host
    30                         during Step 3.

    31                    PI=1 means that the  host  is  requesting  adapter
    32                         purge interrupts.


    33     Step 2 shall complete within 10 seconds from the  time  the  host
    34     writes  the  Step  2  data  into the SA register.  The completion
    35     shall result in a host interrupt if the IE bit had  been  set  in
    36     Step 1.




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     1     3.2.3  Standard Initialization Step 3

     2     Step 3 begins when S3 makes the transition 0-->1.  At  that  time
     3     the following pattern is present in the SA register:

     4                         S3                           
     5                          |                           
     6                     15   V     10  8 7 6           0 
     7                     +-+-+-+-+-+-----+-+-------------+
     8                     |E|0|1|0|0|rsvd |I| int vector  |
     9                     |R| | | | |     |E| (address/4) |
    10                     +-+-+-+-+-+-----+-+-------------+

    11     In this pattern, bits 7-0 are the echo of bits 7-0  of  the  data
    12     that were written into the SA register by the host during Step 1.

    13     The host responds by writing the following pattern  into  the  SA
    14     register:

    15                     15                             0 
    16                     +-+-----------------------------+
    17                     |P|        commbase hi          |
    18                     |P|          address            |
    19                     +-+-----------------------------+

    20     This pattern has the following interpretation:

    21                    PP=1 means that the host is  requesting  execution
    22                         of  "purge"  and  "poll"  tests  as described
    23                         below.

    24                         The  controller  shall  ignore   PP   if   it
    25                         responded  with DI=0 at the beginning of Step
    26                         1.

    27             commbase hi is the high order  portion  of  the  physical
    28                         address  of  [base+0]  of  the communications
    29                         area.

    30                         Note that  the  low  order  portion  of  this
    31                         address  will  have  been written into the SA
    32                         register by the host during Step 2.


    33     If PP has been set, then immediately upon writing the SA register
    34     the host shall wait for the SA register to be cleared (zeroed) by
    35     the controller.  The host shall then do the following:





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           Initialization Details                            9 November 1989


     1          1.  Write zeros into the  SA  register.   This  simulates  a
     2              "purge completed" host action.

     3          2.  Read (and disregard) the IP register.  This simulates an
     4              access command queue request from the host.

     5     The host shall complete this  sequence  within  100  milliseconds
     6     from the time the SA register was first written during Step 3.

     7     While the host is performing the  above  steps,  the  controller,
     8     having seen PP=1, does the following:

     9          1.  Loads zeros into the SA register.

    10          2.  Waits for the SA register to be written by the host.

    11          3.  Waits for IP to be read by the host.


    12     Figure 3-1 illustrates the Purge/Poll test sequence.

    13                HOST                        CONTROLLER          
    14               ACTION                         ACTION            
    15               ------                         ------            

    16          Set   the  'PP' ------------->  Recognize 'PP' = 1    
    17          bit  in  the SA                       |               
    18          Register                              |               
    19                                                |               
    20                                                v               
    21          Wait for SA = 0 <-------------  Load zeros in SA      
    22                 |                                              
    23                 |                                              
    24                 v                                              
    25          Write  zeros to ------------->  Wait for host to write
    26          SA                              SA                    
    27                 |                                              
    28                 |                                              
    29                 v                                              
    30          Read IP         ------------->  Wait  for host to read
    31                                          IP                    

    32                  Figure 3-1:  Purge/Poll Test Sequence

    33  |  As the final part of step  3,  the  controller  shall  perform  a
    34     memory  test  of  the communications area and test the ability of
    35     the  I/O  bus  to  perform   DMA   transfers.    The   controller
    36     accomplishes  this by writing test patterns, such as walking ones
    37     and zeros, in the communications area.  Following the  successful
    38     completion  of  the  test,  the controller shall clear (zero) the


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           Initialization Details                            9 November 1989


     1     communications area.

     2     Step 3 shall complete within 10 seconds.  When it does  complete,
     3     an  interrupt  shall  be  generated if the IE bit had been set in
     4     Step 1.

     5     3.2.4  Standard Initialization Step 4

     6     Step 4 begins when S4 makes the transition 0-->1.  At  that  time
     7     the following pattern is present in the SA register:

     8                      S4                              
     9                       |                              
    10                    15 V      10    9 8     4 3     0 
    11                    +-+-+-+-+-+------+-------+-------+
    12                    |E|1|0|0|0| rsvd | model |  vers |
    13                    |R| | | | |      |       |       |
    14                    +-+-+-+-+-+------+-------+-------+

    15                    vers is the MOD 16 value of the actual  controller
    16                         microcode version.

    17                   model is encoded  to  identify  the  controller  as
    18                         shown   in   Table   A-3,  "Controller  Model
    19                         Values."

    20     The host responds by writing the SA register with the following:

    21  |                  15        10 9 8 7           1 0 
    22  |                  +---------+-+-+-+-----------+-+-+
    23  |                  | reserved|C|N|S|   burst   |L|G|
    24  |                  |         |S|N|F|           |F|O|
    25  |                  +---------+-+-+-+-----------+-+-+

    26     This pattern is interpreted as follows:

    27                   burst is  one  less  than  the  maximum  number  of
    28                         longwords  the  host  is willing to allow per
    29                         DMA transfer.  If this  field  is  zero,  the
    30                         controller shall use its default burst value.
    31                         The  values  of  both  the  default  and  the
    32                         maximum burst size are controller dependent.

    33                    SF=1 indicates special function mode (SFM).   This
    34                         mode is described in detail in Section 6.5.

    35                    NN=1 means that the  controller  should  send  the
    36                         Node  Name  packet  after  initialization  is
    37                         complete.  If both the "NN" and "LF" bits are
    38                         set  and  if a Last Fail packet is available,


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           Initialization Details                            9 November 1989


     1                         the controller should  first  send  the  Node
     2                         Name packet and then the Last Fail packet.

     3  |                 CS=1 means   that   the    host    supports    the
     4  |                      implementation  of  a  controller  scratchpad
     5  |                      buffer.  If this bit is zero, the  controller
     6  |                      stratchpad    descriptor    field    in   the
     7  |                      communications area is undefined.

     8                    LF=1 means that the controller should send a "last
     9                         fail"  response  packet,  if  available, when
    10                         initialization is complete.  See Section 6.4,
    11                         "Last Fail" for more details.

    12                         The host is  responsible  for  ensuring  that
    13                         there  are enough valid buffer descriptors in
    14                         the response queue to handle  any  last  fail
    15                         packet(s).

    16                         Note that the state of LF has  no  effect  on
    17                         the    enabling/disabling    of   unsolicited
    18                         responses in the higher level protocol.

    19                    GO=1 means that the controller  should  enter  its
    20                         functional microcode.

    21                         The host's setting of the  "GO"  bit  signals
    22                         the   end  of  the  initialization  sequence.
    23                         Functions  (timers,  etc.)  dictated  by  the
    24                         higher  level  protocol are not enabled until
    25                         the host sets the "GO" bit.

    26                         If GO=0 the controller shall continue to read
    27                         the  SA register until the host forces the GO
    28                         bit  to  make  the  transition   0-->1.    In
    29                         addition,  the controller shall not recognize
    30  |                      the "burst,"  "LF,"  "NN,"  and  "CS"  values
    31                         unless  GO=1.   If and when the host sets the
    32                         GO bit at a later time, it  shall  write  the
    33  |                      "burst,"  "LF," "NN," and "CS" values desired
    34                         at that time also.


    35     There is no  explicit  interrupt  at  the  end  of  Step  4.   If
    36     interrupts  had  been  enabled,  the  next  interrupt will be due
    37     either to a queue transition or to an adapter purge request.






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           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           VAXBI STORAGE SYSTEMS PORT                               Page 4-1
                                                             9 November 1989


     1                                 CHAPTER 4

     2                        VAXBI STORAGE SYSTEMS PORT


     3     4.1  Overview

     4     This chapter discusses the BI specific  details  for  controllers
     5     that  conform  to DEC STD 057, the VAXBI Standard.  The following
     6     sections detail exceptions  to  standard  SSP  and  bus  specific
     7     constraints imposed on the port protocol by the VAXBI.

     8     From the view point of the host, a BI controller differs  from  a
     9     standard SSP controller in the following ways:

    10          1.  VAXBI  node  initialization  is  performed  before   the
    11              standard  SSP  controller/port  initialization  sequence
    12              starts.

    13          2.  The SA register is implemented as two registers, one for
    14              reads and one for writes.

    15          3.  The IP register is read only from the host.

    16          4.  The format of the unmapped addressing buffer  descriptor
    17              required  for  transmission of data to/from host buffers
    18              differs.

    19          5.  Adapter purges are unnecessary and therefore disabled.

    20          6.  The interrupt vector is set up prior to  the  start  of,
    21              instead   of   during,   the   standard  controller/port
    22              initialization sequence.


    23     4.2  BI I/O Page Registers

    24     Three registers in the BIIC GPR space are used to  implement  the
    25     IP   and  SA  registers.   The  register  names,  addresses,  and
    26     functions are:

    27                 IP bb+F2 polling (read only from the host)

    28                         When  read  by  the  host  and  a  connection
    29                         between  the  host and the controller exists,
    30                         causes the controller to examine the  current
    31                         location   of   the   command  queue  in  the
    32                         communications   area   for   commands,    as
    33                         discussed    in   Section   2.3.4,   "Message
    34                         Transmission." 


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           BI I/O Page Registers                             9 November 1989


     1                         When  read  by  the  host  and  a  connection
     2                         between  the  host  and  controller  does not
     3                         exist, the controller ignores the IP register
     4                         read.

     5                         Note that writing  the  IP  register  has  no
     6                         effect.   The host writes the NRST bit in the
     7                         BI Control and Status Register  (BI  CSR)  to
     8                         effect a hard initialization.

     9              R-SA bb+F4 initialization  data/status  and  operational
    10                         status (read only from host)

    11                         When read by the host during  initialization,
    12                         it   contains   data  and  error  information
    13                         relating to the initialization process.

    14                         When  read  by   the   host   during   normal
    15                         operation,  it  contains  status information,
    16                         such as controller detected fatal errors.

    17                         The data portion of the R-SA  register  (bits
    18                         0-10)  is  qualified  either  by the "ER" bit
    19                         (bit 15) or by one of  the  step  bits  (bits
    20                         11-14).   The contents of the data portion of
    21                         the SA register are undefined if the "ER" bit
    22                         is clear and a step bit is not set.

    23              W-SA bb+F6 initialization control and simulated  adapter
    24                         purge (write only from host)

    25                         When written  by  the  host  during  standard
    26                         initialization, it communicates host specific
    27                         parameters to the controller.  It may also be
    28                         used  to  simulate  "purge completion" by the
    29                         host during standard initialization Step 3 if
    30                         the controller supports enhanced diagnostics.
    31                         See Section 3.2.3 for complete details.

    32                         Note that writing the W-SA  register  has  no
    33                         effect  once initialization has completed and
    34                         normal operation has begun.   Adapter  purges
    35                         are  not  required  to reaccess memory on the
    36                         VAXBI bus.

    37     where:  "bb" is the VAXBI node address






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           Data Transmission                                 9 November 1989


     1     4.3  Data Transmission

     2     Buffer descriptors for  "unmapped  addressing"  as  described  in
     3     Sections   2.3.7,  "Data  Transmission"  and  2.3.7.1,  "Unmapped
     4     Addressing Mode"  have the following format:

     5           31 30 29                                          0 
     6           +-+-+----------------------------------------------+
     7           |0|0|               buffer address                 |
     8           +-+-+----------------------------------------------+

     9     where:

    10          buffer address is the 30 bit physical buffer address for the
    11                         transfer.

    12                         Bits 30-31 must  be  zero.   Any  attempt  to
    13                         perform a transfer to an address greater than
    14                         2**30-2 will result in higher level  protocol
    15                         (Disk  MSCP)  "Host  Buffer  Access  Error --
    16                         Nonexistent memory error" status.

    17     Buffer descriptors for "mapped addressing" are  as  described  in
    18     Section 2.3.7.2, "Mapped Addressing Mode."

    19     4.4  Controller Initialization

    20     4.4.1  BI Register Usage

    21     Table 4-1 shows the BI register usage.






















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           Controller Initialization                         9 November 1989


     1                      Table 4-1:  BI Register Usage

     2     +--------------------+-----------+-----------+------------------+
     3     |                    |           |           |                  |
     4     |    BI Register     |    Bit    |   Init    |     To value     |
     5     |                    |           |    by     |                  |
     6     +--------------------+-----------+-----------+------------------+
     7     | Device Register    |  <31:16>  |  Adapter  | Revision         |
     8     |                    |           |           |                  |
     9     |                    |  <15:0>   |  Adapter  | Type             |
    10     +--------------------+-----------+-----------+------------------+
    11     | BI Control and     | STS   <11>|  Adapter  | Set              |
    12     | Status Register    |           |           |                  |
    13     |                    | BROKE <12>|  Adapter  | Clear            |
    14     |                    |           |           |                  |
    15     |                    | NRST  <10>|  Adapter  | Clear            |
    16     |                    |           |           |                  |
    17     |                    | HEIE   <7>|   Host    | Set   to  enable |
    18     |                    |           |           | hard  and   soft |
    19     |                    | SEIE   <6>|   Host    | error interrupts |
    20     +--------------------+-----------+-----------+------------------+
    21     | Bus Error Register |     -     |  Adapter  | Clear            |
    22     +--------------------+-----------+-----------+------------------+
    23     | Error Interrupt    |  <13:2>   |   Host    | Error  Interrupt |
    24     | Control Register*  |           |           | vector address   |
    25     +--------------------+-----------+-----------+------------------+
    26     | Interrupt          |     -     |   Host    | Host   BI   node |
    27     | Destination        |           |           | address          |
    28     | Register*          |           |           |                  |
    29     +--------------------+-----------+-----------+------------------+
    30     | User Interface     |  <13:2>   |   Host    | Interrupt vector |
    31     | Interrupt Control  |           |           |                  |
    32     | Register*          |           |           |                  |
    33     +--------------------+-----------+-----------+------------------+
    34     | All others         |     -     |  Adapter  | Clear            |
    35     +--------------------+-----------+-----------+------------------+
    36     | An asterisk (*) beside the register name indicates that it is |
    37     | initialized  after  the  adapter  self-test is complete.  All |
    38     | other registers are initialized during the self-test.         |
    39     +--------------------+-----------+-----------+------------------+


    40     4.4.2  Initialization Procedure

    41     Initialization   consists   of   two   separate    initialization
    42     procedures:   node  initialization required by the VAXBI Standard
    43     and the standard SSP initialization Steps 1 through 4.   BI  node
    44     initialization   is   always   performed   before   standard  SSP
    45     initialization.



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           Controller Initialization                         9 November 1989


     1     4.4.2.1  BI Node Initialization


     2          1.  The  initialization  procedure  begins   with   a   hard
     3              initialization  from the host.  That is, the host writes
     4              the NRST bit in the BI Control and Status  Register  (BI
     5              CSR) or does a Bus Init.  When writing the NRST bit, the
     6              host shall clear the  HEIE  and  SEIE  bits  to  prevent
     7              interrupts from occurring during adapter self-test.

     8          2.  After the NRST bit has been written, the  host  waits  a
     9              minimum  of  10  seconds,  then  checks the state of the
    10              BROKE bit in the BI CSR.  If  the  BROKE  bit  is  clear
    11              (zero), the controller has passed self test and is ready
    12              for the standard port initialization sequence to proceed
    13              --  i.e., the transition to Step 1 pattern is present in
    14              the R-SA.  If the BROKE bit is set, the  controller  has
    15              failed  self  test.  The controller reports that failure
    16              by setting the ER bit in the R-SA register  and  placing
    17              an error code in the low 11 bits.

    18              Note that the contents of the R-SA register may  not  be
    19              considered  as valid until 10 seconds after the the NRST
    20              bit has been written, even if a transition in the  BROKE
    21              bit is detected prior to that time.

    22          3.  After adapter self-test and prior to writing the Step  1
    23              data, the host may enable interrupts as follows:

    24              i.  Write the interrupt vector to the BI User  Interface
    25                  Interrupt Control Register,

    26             ii.  Write  the  error  interrupt  vector  to  the  Error
    27                  Interrupt Control Register,

    28            iii.  Set the  bit  corresponding  to  the  host  BI  node
    29                  address in the Interrupt Destination Register,

    30             iv.  Set the HEIE and/or SEIE bits.

    31              The vector written to the Error Interrupt  register  may
    32              be  the  same  vector  as used in the User register or a
    33              different value  if  desired.   If  interrupts  are  not
    34              desired,  the  above  registers  and  bits shall be left
    35              cleared (the adapter zeros these  registers  during  its
    36              self test).






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           Controller Initialization                         9 November 1989


     1     4.4.2.2  Standard Initialization

     2     The standard four step initialization proceeds  as  described  in
     3     Chapter  3, "Port/Controller Initialization." Note, however, that
     4     interpretation of certain fields varies slightly:

     5          1.  The controller ignores the "int vector"  field  (bits  0
     6              through  6)  of  the  Step 1 W-SA pattern written by the
     7              host.  The interrupt vector address  is  initialized  as
     8              described in Section 4.4.2.1, "BI Node Initialization."

     9          2.  The controller ignores the setting of the  "PI"  bit  in
    10              the  Step  2  W-SA  pattern  written  by  the host since
    11              adapter purges are not required to  reaccess  memory  on
    12              the VAXBI bus.





































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           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           XMI STORAGE SYSTEMS PORT                                 Page 5-1
                                                             9 November 1989


     1                                 CHAPTER 5

     2                         XMI STORAGE SYSTEMS PORT


     3     5.1  Overview

     4     This chapter discusses the XMI specific details  for  controllers
     5     that   conform   to   the   Calypso   Memory  Interconnect  (XMI)
     6     specification.  The following sections detail any  exceptions  to
     7     standard  SSP  and  bus specific contstraints imposed on the port
     8     protocol by the XMI.

     9     5.2  XMI Port Registers

    10     The XMI I/O registers consist of the SA, IP, and PD registers and
    11     the XMI required registers.  The XMI required registers are:

    12          1.  Device Register (XDEV)

    13          2.  Bus Error Register (XBER)

    14          3.  Failing Address Register (XFADR)

    15          4.  Communications Register (XCOMM)

    16          5.  Failing Address Extension Register (XFAER)


    17     The required XMI register addresses, the SA, IP, and PD  register
    18     addresses and their sizes are given in Table 5-1.





















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     1                      Table 5-1:  XMI I/O Registers

     2              +-----------+-----------------+--------------+
     3              |   Name    |   Address       |  Size        |
     4              +-----------+-----------------+--------------+
     5              |  XDEV     |  bb +  0        |  32 bits     |
     6              +-----------+-----------------+--------------+
     7              |  XBER     |  bb +  4        |  32 bits     |
     8              +-----------+-----------------+--------------+
     9              |  XFADR    |  bb +  8        |  32 bits     |
    10              +-----------+-----------------+--------------+
    11              |  XCOMM    |  bb +  10       |  32 bits     |
    12              +-----------+-----------------+--------------+
    13              |  XFAER    |  bb +  2C       |  32 bits     |
    14              +-----------+-----------------+--------------+
    15              |  IP       |  bb +  40       |  16 bits     |
    16              +-----------+-----------------+--------------+
    17              |  SA       |  bb +  44       |  16 bits     |
    18              +-----------+-----------------+--------------+
    19              |  PD       |  bb +  48       |  32 bits     |
    20              +-----------+-----------------+--------------+


    21              where: "bb" is the node base address. 


    22     For the detailed definition of the  XMI  required  registers  and
    23     their use, see the XMI specification.

    24     For XMI controllers, the IP is similar  to  the  IP  register  as
    25     described  in  Section  2.2.3,  "I/O  Page  Registers,"  and  its
    26     definition is given below.  The SA register has  only  the  first
    27     three  functions described in Section 2.2.3, as shown here below.
    28     The PD register is an extra register above the  ones  defined  in
    29     Section   2.2.3   and   is  used  to  transfer  interrupt  vector
    30     information  from  the  host  to  the   controller   during   SSP
    31     initialization.   All SSP registers shall be written as an atomic
    32     operation.

    33     The IP register has four functions for XMI controllers:

    34          1.  When read or written by the host with any  value  and  a
    35              connection  between  the  host  and  controller  exists,
    36              causes the controller to examine the current location of
    37              the   command  queue  in  the  communications  area  for
    38              commands,  as  discussed  in  Section  2.3.4,   "Message
    39              Transmission."  Note the term "polling" is used in parts
    40              of  this  specification  to  describe  the  controller's
    41              access of the command queue.



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     1              Host processors with faster I/O register write  accesses
     2              would  use the faster write access of the IP register to
     3              facilitate controller examination of the  communications
     4              area for commands.

     5              When read by the host and a connection between the  host
     6              and  controller  does  not  exist, the device controller
     7              ignores the IP register read.

     8          2.  When written with a 1 by the host  followed  by  a  node
     9              HALT,   causes   the   controller   to  perform  a  soft
    10              initialization.

    11          3.  When written with a 2 by the host  followed  by  a  node
    12              HALT,  causes  the  controller  to perform a maintenance
    13              initialization.

    14          4.  

    15              When written with a -1 by the host followed  by  a  node
    16              HALT,  causes  the  controller to perform a code update.
    17              The details of how  the  code  update  is  performed  is
    18              discussed   in   Section   5.3.4   "XMI   Code  Update."
    19              Implementation of code update is optional.

    20          5.  Controller action is undefined in all other cases.


    21     The SA register has three functions for XMI controllers:

    22          1.  When read by the host during initialization, it contains
    23              data    and    error   information   relating   to   the
    24              initialization process.

    25          2.  When written  by  the  host  during  initialization,  it
    26              communicates host specific parameters to the controller.

    27          3.  When  read  by  the  host  during  normal  operation  it
    28              contains status information, such as controller detected
    29              fatal errors.


    30     The PD register has only one function for XMI controllers:

    31          1.  Written  with  an  interrupt  level  and  an   interrupt
    32              destination  mask by the host prior to the host response
    33              to SSP initialization Step 1.





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     1              Read by  the  controller  prior  to  SSP  initialization
     2              Step 2.

                   

     3     5.3  XMI-Specific Initialization

     4     Initialization   consists   of   two   separate    initialization
     5     procedures:     node   initialization   required   by   the   XMI
     6     specification  and  the  standard  SSP   initialization   Steps 1
     7     through 4.    XMI   initialization  is  always  performed  before
     8     standard SSP initialization.

     9     The XMI initialization procedure is started  upon  receipt  of  a
    10     power   up,  or  a  hard,  soft,  or  maintenance  initialization
    11     sequence.  On initialization, every XMI node shall perform a node
    12     self  test.   This  testing  includes  a  self  test  of  the XMI
    13     interface and a self test of the modules that comprise the  node.
    14     Refer   to   the  XMI  specification  for  complete  details  and
    15     requirements for XMI initialization.  XMI initialization and node
    16     self  test  shall  complete  within  10  seconds after receipt of
    17     either a node  reset  or  power  up.   After  completion  of  XMI
    18     initialization  and  node  self test, standard SSP initialization
    19     Step 1 is entered.

    20     5.3.1  Hard Initialization

    21     Hard initialization is a means by which  the  host  requests  the
    22     controller  to  do a complete reinitialization, including running
    23     its internal diagnostic  tests.   The  controller  performs  hard
    24     initialization  upon  receipt of either a power up or node reset.
    25     The port driver initiates node reset by setting the NRST  bit  in
    26     the XBER register.

    27     5.3.2  Soft Initialization

    28     Soft initialization is a means by which the host can request  the
    29     controller  to perform microcode context reinitialization without
    30     performing its internal diagnostic tests.

    31     Soft initialization is initiated by the port driver  writing  the
    32     IP  register with a "1" and then setting the HALT bit in the XBER
    33     register.  The host  shall  ensure  that  any  error  information
    34     written  by  the  controller  into  the SA register has been read
    35     prior to starting soft initialization.

    36     The controller, upon receiving the HALT, examines the IP register
    37     to   decide   if   soft   initialization  is  desired.   If  soft
    38     initialization is desired, the controller shall perform a  sanity
    39     check   on  its  microcode.   If  the  microcode  is  bad,  error


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     1     information  is  written  into  the  SA  register  and   a   hard
     2     initialization  of  the  controller  shall  take  place.   If the
     3     microcode is  good,  the  controller  starts  SSP  initialization
     4     Step 1.

     5     5.3.3  Maintenance Initialization

     6     Maintenance initialization is a  means  by  which  the  host  can
     7     request  the controller to enter maintenance mode upon completion
     8     of initialization.

     9     Maintenance  initialization  is  initiated  by  the  port  driver
    10     writing  a "2" into the IP register and then setting the HALT bit
    11     in the XBER register.  The  host  shall  ensure  that  any  error
    12     information  written  by  the controller into the SA register has
    13     been read prior to starting maintenance initialization.

    14     The controller, upon receiving the HALT, examines the IP register
    15     to   decide   if   maintenance  initialization  is  desired.   If
    16     maintenance initialization  is  desired,  the  controller  enters
    17     maintenance  mode at the completion of SSP initialization Step 4.
    18     The controller starts SSP initialization Step 1 on completion  of
    19     the required XMI node initialization.

    20     Maintenance mode allows the controller a means by  which  it  can
    21     dump  its  internal  memory  to  a  host.   Maintenance  mode  in
    22     conjunction with maintenance read and write commands are used  to
    23     examine  controller  memory in situations in which the controller
    24     bug checks or crashes for unknown reasons  or  for  reasons  that
    25     need closer examination.

    26     Writing the maintenance initialization code in  the  IP  register
    27     before  performing  a node HALT instructs the controller to enter
    28     maintenance mode after  Step 4  and  dump  its  internal  memory;
    29     therefore,  the  controller should not initialize the majority of
    30     its memory and lose its previous  software  context.   After  the
    31     memory  dump has been completed, a node reset should be issued by
    32     the host followed by the standard hard  initialization  procedure
    33     to get the controller into normal operating mode.

    34  |  5.3.4  Code Update Initialization

    35  |  The XMI  code  update  scheme  is  an  emulation  of  a  hardware
    36  |  read/write path to controller memory.  Very simple code is placed
    37  |  at a specific virtual location in static RAM.   This  code  reads
    38  |  and  writes controller memory as instructed by the Storage System
    39  |  Port (SSP) registers.  It is essentially an SSP  register  driven
    40  |  loader.   Note  that  throughout  this  section,  the term "host"
    41  |  refers to the code update procedure in the host.



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     1  |  By using read and write controller memory primitives the host can
     2  |  perform  and  verify  a  complete code update.  The update image,
     3  |  verification  process,  and  update  safety  procedures  are  all
     4  |  controller  dependent.   Only the basic read and write procedures
     5  |  are defined in this section.

     6  |  The Update Init instructs the controller  to  enter  code  update
     7  |  early  in its initialization process.  The controller's boot code
     8  |  recognizes that an Update Init has occurred and checks to see  if
     9  |  the  XMI  signal  UPDATE  EN  H  is  asserted.  If the bit is not
    10  |  asserted, the controller boot code  indicates  an  initialization
    11  |  error  and does not allow the code update initialization sequence
    12  |  to proceed.  If  the  bit  is  asserted,  the  controller  passes
    13  |  control to the code update procedure.

    14  |                                NOTE

    15  |  Since minimal system checking is performed for an Update Init, it
    16  |  is  required that the host do a Hard Init to the controller prior
    17  |  to the Update Init.


    18  |  5.3.4.1  Code Update Registers

    19  |  Once the controller is  in  code  update  mode,  simple  register
    20  |  handshaking   mechanisms   are   used  to  synchronize  host  and
    21  |  controller.  Two of the three SSP  port  registers  are  used  to
    22  |  transfer data, addresses, and commands.  The first port register,
    23  |  the Status, Address and Purge register (SA), is used to  transfer
    24  |  commands and return action status as follows:
    25  |      15  14        11 10      8 7                          0  
    26  |      +---+------------+---------+----------------------------+
    27  |      | E |     MBZ    |  Error  |    Host Command Opcode/    |
    28  |      | R |            |  Code   |     Controller Status      |
    29  |      +---+------------+---------+----------------------------+
    30  |               Error Byte        |     Command/Status Byte     

    31  |  where:

    32  |   Command Opcode/
    33  |   Controller Status  is used to  both  transfer  commands  and  to
    34  |                      return   action  status.   The  Host  Command
    35  |                      Opcode  values  and  the  Controller   Status
    36  |                      values  are  mutually  exclusive  to  prevent
    37  |                      command/status confusion.  See Table 5-2  for
    38  |                      the  host command opcode values and Table 5-3
    39  |                      for the controller status values.

    40  |          Error Code  describes the type of error or  failure  that
    41  |                      occurred on the most recent command.


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     1  |                 MBZ  must be zero.  This field corresponds to  the
     2  |                      S-bits  in the port/controller initialization
     3  |                      sequence.   The  host  and  controller  shall
     4  |                      assume  an error has occurred if any of these
     5  |                      bits are ever set.

     6  |                  ER  is set by the controller if an error occurred
     7  |                      on the most recent command given by the host.
     8  |                      It is clear otherwise.

     9  |  The second port register, the Port Data register (PD), is used to
    10  |  communicate  data  and the virtual controller memory addresses to
    11  |  use.

    12  |  The maximum time allowed  for  all  controller  operations  is  4
    13  |  seconds.


    14  |                  Table 5-2:  Host Command Opcodes

    15  |  +--------+---------+-------------------------------------------+
    16  |  | Opcode |   Name  |               Description                 |
    17  |  |  (hex) |         |                                           |
    18  |  +--------+---------+-------------------------------------------+
    19  |  |        |         | Use the address in the PD register as the |
    20  |  |   11   | SET NEW | "current address" for READ DATA and WRITE |
    21  |  |        | ADDRESS | DATA operations.  This address  shall  be |
    22  |  |        |         | longword aligned.                         |
    23  |  +--------+---------+-------------------------------------------+
    24  |  |        |         | Write  the longword in the PD register to |
    25  |  |   22   |  WRITE  | the current address.  If no error occurs, |
    26  |  |        |  DATA   | update  the  current  address to point to |
    27  |  |        |         | the next longword in controller memory.   |
    28  |  +--------+---------+-------------------------------------------+
    29  |  |        |         | Write the longword of data at the current |
    30  |  |        |  READ   | address to the PD register.  If no  error |
    31  |  |   44   |  DATA   | occurs,  update  the  current  address to |
    32  |  |        |         | point to the next longword in  controller |
    33  |  |        |         | memory.                                   |
    34  |  +--------+---------+-------------------------------------------+
    35  |  |        |         | Code  update  is complete; the controller |
    36  |  |   88   |  DONE   | should loop waiting for  Hard  Init,  the |
    37  |  |        |         | only way in which the host can return the |
    38  |  |        |         | controller to normal operation.           |
    39  |  +--------+---------+-------------------------------------------+







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     1  |                Table 5-3:  Controller Status Codes

     2  |  +----------+------+----+---------------------------------------+
     3  |  |  Status  | Code | ER |            Description                |
     4  |  |          | (hex)|    |                                       |
     5  |  +----------+------+----+---------------------------------------+
     6  |  |          |      |    | The   controller   has   successfully |
     7  |  | SUCCESS  |  00  |  0 | completed the command and is ready to |
     8  |  |          |      |    | accept the next command.              |
     9  |  +----------+------+----+---------------------------------------+
    10  |  |          |      |    | The  controller  detected an error in |
    11  |  | FAILURE  |  00  |  1 | performing the command.  The  command |
    12  |  |          |      |    | should   be  retried  or  the  update |
    13  |  |          |      |    | restarted.                            |
    14  |  +----------+------+----+---------------------------------------+
    15  |  |  START   |      |    | The controller has completed its code |
    16  |  | TRANSFER |  A5  |  0 | update initialization and is ready to |
    17  |  |          |      |    | perform code update commands.         |
    18  |  +----------+------+----+---------------------------------------+



    19  |                Table 5-4:  Code Update Error Codes

    20  |   +------+---------+-------------------------------------------+
    21  |   | Code |  Name   |               Description                 |
    22  |   | (hex)|         |                                           |
    23  |   +------+---------+-------------------------------------------+
    24  |   |      |         | The   command   from  the  host  was  not |
    25  |   |   1  | ILLEGAL | recognized.  Internal controller  address |
    26  |   |      | COMMAND | does  NOT need to be reset with a SET NEW |
    27  |   |      |         | ADDRESS command.                          |
    28  |   +------+---------+-------------------------------------------+
    29  |   |      |   NO    | The host tried to do a READ DATA or WRITE |
    30  |   |   2  | ADDRESS | DATA  without  first  setting an address. |
    31  |   |      |SPECIFIED| The internal controller address needs  to |
    32  |   |      |         | be set with a SET NEW ADDRESS command.    |
    33  |   +------+---------+-------------------------------------------+
    34  |   |      |         | The  controller had a parity error on the |
    35  |   |      | PARITY  | most  recent  READ  DATA  or  WRITE  DATA |
    36  |   |   3  | ERROR   | command.  The internal controller address |
    37  |   |      |         | needs to be set with a  SET  NEW  ADDRESS |
    38  |   |      |         | command.                                  |
    39  |   +------+---------+-------------------------------------------+
    40  |   |      | ILLEGAL | The  address used was an illegal address. |
    41  |   |   4  | ADDRESS | The internal controller address needs  to |
    42  |   |      |         | be set with a SET NEW ADDRESS command.    |
    43  |   +------+---------+-------------------------------------------+




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     1  |             Table 5-4: Code Update Error Codes (cont.)

     2  |   +------+---------+-------------------------------------------+
     3  |   | Code |  Name   |               Description                 |
     4  |   | (hex)|         |                                           |
     5  |   +------+---------+-------------------------------------------+
     6  |   |      |OPERATION| The  read or write operation failed.  The |
     7  |   |   5  | FAILED  | internal controller address needs  to  be |
     8  |   |      |         | set with a SET NEW ADDRESS command.       |
     9  |   +------+---------+-------------------------------------------+


    10  |  5.3.4.2  Code Update Operation; Examples

    11  |  Note that in the following examples the writes to the SA register
    12  |  shall  be  done  as  atomic  operations  by both the host and the
    13  |  controller.   The  maximum  time  allowed  for   all   controller
    14  |  operations is 4 seconds.

    15  |  5.3.4.2.1  Controller Host Synchronization

    16  |  The host performs the following steps to enter  update  mode  and
    17  |  synchronize with the controller:

    18  |       1.  The host performs a HARD INIT of the controller.

    19  |       2.  The host then writes  a  (-1)  into  the  controller  IP
    20  |           register  and then sets the node halt bit (20000000 hex)
    21  |           in the controller XBE register  to  initiate  an  Update
    22  |           Init.

    23  |       3.  The host then loops on the SA register waiting  for  the
    24  |           Start  Transfer  status  (00A5 hex) from the controller.
    25  |           An error occurs if the host times out the controller.

    26  |       4.  After the Start Transfer status has been read, the  host
    27  |           may proceed with any of the update operations.


    28  |  5.3.4.2.2  Setting A New Controller Address

    29  |  The host sets a new controller memory address as follows:

    30  |       1.  The host writes the starting longword aligned controller
    31  |           memory address into the controller PD register.  It then
    32  |           clears the error byte and writes  the  SET  NEW  ADDRESS
    33  |           command  into the SA register (0011 hex).  The host then
    34  |           loops on the SA register waiting for the status  of  the
    35  |           operation.   An  error  occurs if the host times out the


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     1  |           controller.

     2  |       2.  The controller, upon reading the SET NEW ADDRESS command
     3  |           in the command/status byte of the SA register, reads the
     4  |           address in the PD register and stores it internally.  If
     5  |           the  address  is  a valid controller memory address, the
     6  |           controller clears the host command and writes Success in
     7  |           the  command/status  byte of the SA register (0000 hex).
     8  |           If the address is invalid, the contoller clears the host
     9  |           command  and  writes  Failure in the command/status byte
    10  |           and Illegal Address error in the error byte  of  the  SA
    11  |           register  (8400 hex).  The controller then loops reading
    12  |           the SA register waiting for the next command,  which  is
    13  |           indicated  by a nonzero value in the Host Command Opcode
    14  |           field.

    15  |       3.  After the host reads the controller status  and  if  the
    16  |           operation  was  successful, it may then proceed to issue
    17  |           READ DATA and WRITE DATA commands.  NOTE:  The read  and
    18  |           write  operations may occur back to back without setting
    19  |           a new controller memory address.


    20  |  5.3.4.2.3  Write Controller Memory Operations

    21  |  The host writes controller memory as follows:

    22  |       1.  The host sets the controller memory address to write  to
    23  |           by  using  the  SET  NEW ADDRESS command as shown in the
    24  |           previous example.  If the  controller  already  has  the
    25  |           desired  address,  the  SET  NEW  ADDRESS command may be
    26  |           skipped.

    27  |       2.  The host then writes a longword of controller data  into
    28  |           the  PD  register.   It  then  clears the error byte and
    29  |           writes the WRITE DATA command  into  the  command/status
    30  |           byte of the SA register (0044 hex).  The host then loops
    31  |           on the  SA  register  waiting  for  the  status  of  the
    32  |           operation.An  error  occurs  if  the  host times out the
    33  |           controller.

    34  |       3.  The controller, upon reading  the  WRITE  DATA  command,
    35  |           reads the data from the PD register and writes it to the
    36  |           internal controller memory address.  Upon  a  successful
    37  |           write  to  its own memory, the controller writes Success
    38  |           and clears the host command in  the  SA  register  (0000
    39  |           hex).   The  controller  indicates  a failure by writing
    40  |           8x00 hex to the SA register, where 'x'  is  the  failure
    41  |           reason (see Table 5-4 for update error code values).  If
    42  |           the operation was successful,  the  internal  controller


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     1  |           memory  address is incremented by a longword so that the
     2  |           next read or write operation will use the next  longword
     3  |           address.

     4  |       4.  When the host reads Success in the SA register,  it  may
     5  |           then  proceed  to  the next command.  NOTE:  If the host
     6  |           wishes to write any controller memory address other  the
     7  |           next longword, it needs to issue another SET NEW ADDRESS
     8  |           command before proceeding.


     9  |  5.3.4.2.4  Read Controller Memory Operations

    10  |  The host reads a controller memory address as follows:

    11  |       1.  The host sets the memory address it wishes to read  with
    12  |           the SET NEW ADDRESS command as in the previous examples.
    13  |           If the controller already has the desired  address,  the
    14  |           SET NEW ADDRESS command may be skipped.

    15  |       2.  The host then  writes  the  READ  DATA  command  in  the
    16  |           command  byte  and  clears error byte in the SA register
    17  |           (0022 hex).  It then loops on the  SA  register  waiting
    18  |           for the status of the operation.  An error occurs if the
    19  |           host times out the controller.

    20  |       3.  The controller, upon  reading  the  READ  DATA  command,
    21  |           reads the longword of data from controller memory at the
    22  |           internal controller memory address and writes  the  data
    23  |           into the PD register.  Upon a successful read of its own
    24  |           memory, the controller writes  Success  and  clears  the
    25  |           host  command  in  the  SA  register  (0000  hex).   The
    26  |           controller indicates a failure by writing  8x00  hex  to
    27  |           the  SA  register,  where 'x' is the failure reason (see
    28  |           Table  5-4  for  update  error  code  values).   If  the
    29  |           operation  was successful, the controller increments the
    30  |           internal address by a longword so that the next read  or
    31  |           write operation will use the next longword address.

    32  |       4.  When the host reads Success in the SA register, it  then
    33  |           reads  the  longword  of  data  in  the  PD register and
    34  |           proceeds to the next command.  NOTE:  If the host wishes
    35  |           to  read  any  controller  memory address other the next
    36  |           longword, it needs to  issue  another  SET  NEW  ADDRESS
    37  |           command before proceeding.







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     1  |  5.3.4.2.5  Exiting The Update

     2  |  The host exits update mode as follows:

     3  |       1.  The host writes the DONE command  in  the  host  command
     4  |           byte  and  clears  the command status and error bytes in
     5  |           the SA register (0088 hex).

     6  |       2.  The host then loops on the SA register waiting  for  the
     7  |           status  of  the  operation.  An error occurs if the host
     8  |           times out the controller.

     9  |       3.  The controller, upon reading the  DONE  command  in  the
    10  |           host command byte, writes Success and clears the command
    11  |           byte in the SA register (0000 hex).

    12  |       4.  The controller then loops forever  waiting  for  a  Hard
    13  |           Init to reset the controller.

    14  |       5.  After reading Success in the SA register, the host  does
    15  |           a  Hard  Init  to  the controller to reset it for normal
    16  |           operation.


    17  |  5.3.4.3  Power Failure, Host Crashes, Etc.

    18  |  The controller and cooperating host are responsible for  handling
    19  |  the  update sequence in the face of host crashes, power failures,
    20  |  etc.  The mechanisms used are implementation specific.   However,
    21  |  ways in which these could be handled are:

    22  |       1.  Place the critical code that performs  the  code  update
    23  |           functions in a protected area of memory, thus protecting
    24  |           them against being overwritten and always  allowing  you
    25  |           to  perform  the  code  update function.  Note that this
    26  |           requires the critical code to be bug-free.

    27  |       2.  Perform your code update in two parts.  Place a copy  of
    28  |           your  critical code into the memory that will be updated
    29  |           in the second part of the update  sequence.   Using  the
    30  |           copy that is now contained in the second part of memory,
    31  |           update the first part.  Once completed,  using  the  new
    32  |           copy  of  the critical code that now is contained in the
    33  |           first part of memory, update the second part.








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     1     5.3.5  SSP Initialization Differences

     2     Standard SSP  initialization  follows  XMI  node  initialization.
     3     Interpretation  of  certain  fields  varies,  as described in the
     4     following sections.

     5     5.3.5.1  Step 1 Differences

     6     After completion  of  XMI  initialization  and  node  self  test,
     7     standard  SSP  initialization Step 1 is entered.  The timeout for
     8     entering SSP initialization Step 1 is 10 seconds.   Standard  SSP
     9     initialization  is  performed as described in section 3.2.1, with
    10     the following variations:

    11     The PD register shall be written prior to writing the SA register
    12     in initialization Step 1, host response.  The PD register has the
    13     bit representations:

    14         31                20 19   16 15                       0 
    15         +-------------------+-------+--------------------------+
    16         |     Undefined     |  IL   |       Intr Dest          |
    17         |                   |       |         Mask             |
    18         +-------------------+-------+--------------------------+


    19         Intr Dest Mask  Interrupt Destination Mask.   Corresponds  to
    20                         the  node destination mask defined by the XMI
    21                         specification during an INTR transaction.

    22                     IL  Interrupt Level.   Corresponds  to  the  four
    23                         interrupt   levels   defined   by   the   XMI
    24                         specification during an INTR transaction.

    25     The SA register host response in initialization  Step 1  has  the
    26     following bit representations:

    27                     15   13 11 10  8 7 6           0 
    28                     +-+-+-----+-----+-+-------------+
    29                     |I|W|c que|r que|I| int vector  |
    30                     |V|R| lng | lng |E| (address/4) |
    31                     +-+-+-----+-----+-+-------------+


    32     This pattern is interpreted as described in  Section  3.2.1  with
    33     the exception of bit 15, the IV bit, and bit 7, the IE bit.

    34                     IV  is the upper  bit  of  the  interrupt  vector
    35                         address.   Addition  of  an upper bit for the
    36                         interrupt  vector  address  allows   an   XMI
    37                         controller to use any of 256 interrupt vector


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     1                         addresses.

     2                     IE  means  that  the  host   is   requesting   an
     3                         interrupt  at  the start of Steps 2, 3, and 4
     4                         (rather than at the completion of Steps 1, 2,
     5                         and 3).

     6     5.3.5.2  Step 4 Differences

     7     The burst size reported in the SA register,  host  response,  has
     8     the following definition:

     9                  burst  is the optimal number of  longwords  for  DMA
    10                         transactions.   The  optimal value depends on
    11                         the memory adapter in question.  For example,
    12                         an  adapter  with a 64 byte buffer for memory
    13                         accesses would use a value of 16.

    14     If  maintenance  mode  was  requested  at   initialization,   the
    15     controller   will  enter  maintenance  mode  upon  completion  of
    16     initialization step 4.

    17     5.4  Bus-Specific Fields In Communications Area

    18     As discussed in Section  2.3.1,  "Host/Controller  Communications
    19     Area,"  there  are  two  words  of  the  header  section  of  the
    20     communications area that communicate bus  dependent  information.
    21     There are five bus-specific fields in those two words for the XMI
    22     bus.  Those words are:

    23                 15             8 7     4 3 2 1 0         
    24                 +-------------------------------+        
    25                 |           PFN Mask            | base -8
    26                 |                               |        
    27  |              +---------------+-------+-+-+-+-+        
    28  |              |    reserved   |  PSI  |U|U|E|H| base -6
    29  |              |               |       |N|N|T|W|        
    30  |              +---------------+-------+-+-+-+-+        

    31     where:

    32                     HW  is the Hexaword Write indicator.  If set,  it
    33                         indicates  that Hexaword writes are supported
    34                         for this XMI implementation  and  will  allow
    35                         controllers   the  ability  to  use  Hexaword
    36                         writes.

    37                     ET  is the Transient Error  Reporting  indicator.
    38                         If  set,  it  indicates that transient errors
    39                         should be reported using the datagram service


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     1                         as described in Section 1.2, "Host/Controller
     2                         Communications Overview."

     3                     UN  is undefined.

     4                    PSI  is the Page Size Indicator field.  This 4 bit
     5                         field  gives  the host the flexibility to use
     6                         differing  page   sizes.    The   page   size
     7                         indicator  is used in the following manner to
     8                         find the page size:

     9                         (2**PSI) * 512 = page size

    10                         thus for PSI = 0, => page size = 512
    11                                  PSI = 1, => page size = 1024
    12                                  PSI = 2, => page size = 2048
    13                                  PSI = 3, => page size = 4096
    14                                  PSI = 4, => page size = 8192
    15                                     ....                     
    16                                     ....                     
    17                                     ....                     

    18               PFN Mask  is the 16  bit  PFN-mask,  which  allows  for
    19                         address expansion of up to 40 bits.  The mask
    20                         corresponds to the most significant  16  bits
    21                         of  the  physical  address (the lower 16 bits
    22                         are always  significant).   The  PFN-mask  is
    23                         left  shifted  16  bits, with 1's entering at
    24                         the right for each shift, and is  then  ANDed
    25                         with the host map register to get the PFN.

    26     5.5  Data Transmission

    27     5.5.1  Unmapped Addressing

    28     Buffer descriptors for  "unmapped  addressing"  as  described  in
    29     Sections   2.3.7,  "Data  Transmission"  and  2.3.7.1,  "Unmapped
    30     Addressing Mode"  have the following format:

    31           31 30 29                                          0 
    32           +-+-+----------------------------------------------+
    33           |0|0|               buffer address                 |
    34           +-+-+----------------------------------------------+

    35     where:

    36          buffer address is the 30 bit physical buffer address for the
    37                         transfer.

    38                         Bits 30-31 must  be  zero.   Any  attempt  to


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           Data Transmission                                 9 November 1989


     1                         perform a transfer to an address greater than
     2                         2**30-2 will result in higher level  protocol
     3                         (Disk  MSCP)  "Host  Buffer  Access  Error --
     4                         Nonexistent memory error" status.

     5     5.5.2  Mapped Addressing Mode

     6     The buffer descriptor used for  mapped  addressing  mode  is  two
     7     longwords and has the following format:

     8          31 30                               x y             0 
     9          +-+----------------------------------+---------------+
    10          |m|         map register index       |     offset    |
    11          +-+-+--------------------------------+---------------+
    12          |mbz|              map register base                 |
    13          +---+------------------------------------------------+
    14          31   29                                             0 

    15     where:

    16                       m is the mapped  data  transfer  flag.   Mapped
    17                         addressing  mode  is  selected by setting the
    18                         "m" bit (m=1).

    19      map register index contains the  index  into  the  map  register
    20                         table associated with the transfer.  The size
    21                         of the map register index field is:

    22                         22 - PSI (Page Size Indicator)

    23                         Thus, for systems with 512  byte  pages,  PSI
    24                         would  be 0 and would yield a field length of
    25                         22 bits for the map register  index  (x=9  in
    26                         the  figure  above).   For  systems with 8192
    27                         byte pages, PSI would be 4 and would yield  a
    28                         map  register  index field length of 18 (x=13
    29                         in the figure above).

    30                         The  controller  converts  the  index  to   a
    31                         longword value by multiplying the index by 4.
    32                         The converted index value is added to the map
    33                         register  base address to produce the address
    34                         of the first map  register  assigned  to  the
    35                         transfer.

    36                         Each map register in the table maps  no  more
    37                         than   one   page's   data.   The  controller
    38                         increments the  initial  map  register  index
    39                         value  to  access  subsequent  map  registers
    40                         during the transfer.  An address  translation


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           Data Transmission                                 9 November 1989


     1                         is  required when the transfer reaches a page
     2                         boundary.  The incremented map register index
     3                         is  the  offset  from  the map register table
     4                         base to the map register entry that  contains
     5                         the page number for the next page's transfer.

     6                  offset is the byte offset within the first  page  in
     7                         host  memory  to be accessed by the transfer.
     8                         The size of the offset field is:

     9                         PSI (Page Size Indicator) + 9

    10                         Thus, for systems with 512  byte  pages,  PSI
    11                         would  be  0  and would yield an offset field
    12                         length of 9 bits (y=8 in the  figure  above).
    13                         For  systems  with 8192 byte pages, PSI would
    14                         be 4 and would yield an offset  field  length
    15                         of 13 bits (y=12 in the figure above).

    16                         The physical address of the first page of the
    17                         transfer  is  calculated  by  adding the (map
    18                         register index)*4 value to the  map  register
    19                         base  address  and  extracting the Page Frame
    20                         Number from the map register.   The  "offset"
    21                         is  concatenated  to the Page Frame Number to
    22                         create the complete physical  address  to  be
    23                         used.

    24                         The physical address may resolve  to  an  odd
    25                         byte  address if the controller is capable of
    26                         performing   odd   byte    transfers.     The
    27                         availability  of  this feature is signaled to
    28                         the host during Step 1 of  initialization  by
    29                         "OD=1"  in  the  SA  register.  Otherwise the
    30                         buffer address shall  specify  an  even  byte
    31                         address.

    32                         The number of bytes transferred in the  first
    33                         page   is  ("Page  size"  -  "offset").   For
    34                         subsequent pages, the offset value is 0; that
    35                         is,  the transfer begins on the first byte of
    36                         the page.  "Page size" bytes are  transferred
    37                         in  each  intermediate  page of the transfer.
    38                         The number of bytes transferred in  the  last
    39                         page  is determined by the remaining transfer
    40                         byte count and may  vary  from  some  minimum
    41                         value  to  a  full  page.   The transfer byte
    42                         count is passed as part of the  higher  level
    43                         protocol.



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     1                     mbz Bits 29 and 30 Must Be Zero.

     2       map register base is the 30 bit physical address of the base of
     3                         the  map  register  table associated with the
     4                         transfer.  The map register  table  shall  be
     5                         longword  aligned  and  the  controller shall
     6                         assume that the base address  supplied  is  a
     7                         longword address.

     8                         Figure 5-1,  "XMI  Address  Mapping  Process"
     9                         illustrates  the  address mapping process for
    10                         the first transfer.

    11     The format of the host map register is as follows:

    12                31                                       0 
    13                +-+---------------------------------------+
    14                |v|                PFN                    |
    15                +-+---------------------------------------+

    16                     v=1 The map register contains valid information.

    17                         The  number  of   map   registers   used   is
    18                         determined  by  the  length  of the transfer.
    19                         Each map register maps up to one page of host
    20                         memory.

    21                         Because a mapped transfer requires  a  number
    22                         of  consecutive  map  registers to define the
    23                         transfer, the controller shall terminate  the
    24                         transfer  if  it finds "v=0" in an active map
    25                         register.  The controller  shall  return  the
    26                         appropriate  higher level protocol error code
    27                         in that event if it still has an  outstanding
    28                         transfer count.

    29                     PFN is the page  frame  number  for  the  current
    30                         transfer   fragment  identified  by  the  map
    31                         register.

    32     The  location  of  the  map  register  table  is  passed  to  the
    33     controller  in the second longword of the buffer descriptor.  The
    34     controller shall assume that the map register  table  is  a  host
    35     physical longword address.

    36     Each mapped transfer shall have its own uniquely  identified  map
    37     register  table.   The  map  register  table shall be in physical
    38     memory; that is, it may not be  itself  mapped.   The  controller
    39     shall use unmapped addressing to access the table.  Consequently,
    40     the map register table shall remain in  memory,  at  its  initial


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     1     location,  for  the  duration  of  the  transfer.   A transfer is
     2     complete when the controller returns the response packet for  the
     3     command.

     4     It is the host's responsibility to ensure that the mapping values
     5     that  it  provides  to  the  controller  result in valid physical
     6     addresses.  It is the controller's responsibility to verify  that
     7     any resultant address is valid for the connecting bus.

     8     The address mapping process is illustrated in  Figure  5-1.   The
     9     diagram  shows  the  generation  of  the physical address for the
    10     initial page of the transfer.  The mapping process for subsequent
    11     pages  is  identical,  except  that  an  offset  value  of  0  is
    12     concatenated to the extracted, masked Page Frame Number  to  form
    13     the physical address.





































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     1      30                       x y             0                      
     2     +--------------------------+---------------+  From the 1st buffer
     3     |    map register index    |     offset    |  descriptor longword
     4     +--------------------------+---------------+                     
     5      \____________v___________/ \______v______/                      
     6                   |                    |                             
     7               extracted                |                             
     8          z        |          0         |                             
     9         +---------v-----------+        |                             
    10         |  map register index |        |                             
    11         +---------v-----------+        |                             
    12                   |                    |                             
    13             multiplied by 4            |                             
    14        z'         |          1 0       |                             
    15       +-----------v---------+-+-+      |                             
    16       |  map register index |0|0|      |                             
    17       +-----------v---------+-+-+      |                             
    18                   |                    |                             
    19                 plus                   |                             
    20      29           |            0       |                             
    21     +-------------v-------------+      |          From the 2nd buffer
    22     |     map register base     | <----|--------  descriptor longword
    23     +-------------v-------------+      |                             
    24                   |                    |                             
    25           yields address of            |                             
    26                   |                    |                             
    27     +-------------+                    |                             
    28     |    31             0              |                             
    29     |   +-+--------------+             |                             
    30     |   |                |             |                             
    31     |   +-+--------------+             |                             
    32     +-->|v|     PFN      |             |                             
    33         +-+------o-------+             |                             
    34         |        |       |             |                             
    35         +-+------|-------+             |                             
    36                  |                     |                             
    37                 AND                    |                             
    38         31       |        0            |                             
    39         +--------v--------+            |                             
    40         |    PFN-mask     |            |                             
    41         +--------o--------+            o                             
    42                   \                     \                            
    43             z''    \                x y  \      0                    
    44             +-------o----------------+----o------+  resultant        
    45             |          PFN           |   offset  |  physical         
    46             +------------------------+-----------+  address          

    47                 Figure 5-1:  XMI Address Mapping Process



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     1     Values of variables in Figure 5-1 are:

     2              PSI = log (pagesize / 512)                 
     3                       2                                  

     4              x   = 9 + PSI

     5              y   = x - 1

     6              z   = 30 - x

     7              z'  = z + 2

     8              z'' = y + 32


     9     5.6  Address Restrictions

    10     The communications area,  mapping  lists,  command  entries,  and
    11     response  entries shall lie within the low-order two gigabytes of
    12     physical memory address space.  This allows  the  use  of  31-bit
    13     physical addresses for addressing these items.

    14     Additionally, the communications area shall start on  a  quadword
    15     boundary,  and  the  message  buffers  shall  start on a longword
    16     boundary.

    17     5.7  Write Ordering

    18     The following rules apply to the shared-memory  accesses  between
    19     an  I/O  controller  and  a  host  CPU.   The  rules  impose some
    20     access-ordering   relationships   on   caches,   write   buffers,
    21     invalidate queues, busses, adapters, and memories on the read and
    22     write data paths between a controller and a host CPU.

    23           o  The host CPU completes all  outstanding  write  accesses
    24              before   completing   any   write  access  that  changes
    25              ring-entry ownership.

    26           o  The controller completes all outstanding write  accesses
    27              before   completing   any   write  access  that  changes
    28              ring-entry ownership.

    29           o  The host CPU completes any read access  for  determining
    30              ring-entry  ownership  before  completing any other read
    31              accesses.

    32           o  The controller completes any read access for determining
    33              ring-entry  ownership  before  completing any other read
    34              accesses.


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     1     Definitions of "complete" for the above rules:  A  "write  access
     2     completes" with respect to another controller or CPU at the state
     3     transition after which the other controller or  CPU  is  able  to
     4     access  the newly written data.  A "read access completes" at the
     5     state transition after which no other controller or CPU  is  able
     6     to affect the data read.

     7     Implementation note:  If an error occurs anywhere along the  data
     8     path  for  a  read  or  write  transaction,  the  error  recovery
     9     procedure (if any) shall ensure that the ordering rules  continue
    10     to  be  followed.  If a hardware error can result in the ordering
    11     rules not being  followed,  then  the  ring-entry  ownership  may
    12     change  before  the  corresponding  data  has  been written.  The
    13     result could be the receiver accessing stale data.

    14     5.8  Error Reporting

    15     Error reporting is  performed  as  described  in  Section  2.3.8,
    16     "Transmission  Errors."   However,  XMI controllers should do the
    17     following additional error reporting:

    18              Transient XMI Errors are recoverable errors which  occur
    19              across   the  XMI  interface.   When  these  errors  are
    20              detected by the controller, it should:

    21              1.  Keep a running total of  all  transient  XMI  errors
    22                  which   have  occurred  since  the  last  controller
    23                  reinitialization

    24              2.  Keep a copy of the XBER register for the most recent
    25                  transient error which occurred

    26              3.  Report these values  in  the  the  Last  Fail  Error
    27                  Packet on controller reinitialization

    28              4.  If Transient  Error  reporting  is  enabled,  report
    29                  these values through the datagram service


    30              Fatal XMI Errors are unrecoverable errors which occur on
    31              a  transaction  essential to port integrity.  When these
    32              errors are detected by the controller, it should:

    33              1.  Keep a copy of the XBER register at the time of  the
    34                  fatal XMI error

    35              2.  Keep a copy of the XMI failing addresses registers





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     1              3.  Report these values  in  the  the  Last  Fail  Error
     2                  Packet on controller reinitialization

     3              4.  Write  the  SA  register  with   the   bit   pattern
     4                  representing  a  Fatal XMI Error and wait for a hard
     5                  initialization














































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           PORT/CONTROLLER DIAGNOSTIC AND MAINTENANCE FACILITIES    Page 6-1
                                                             9 November 1989


     1                                 CHAPTER 6

     2           PORT/CONTROLLER DIAGNOSTIC AND MAINTENANCE FACILITIES


     3     6.1  Diagnostic Wrap Mode

     4     Diagnostic Wrap Mode (DWM) provides host based diagnostics with a
     5     means   of   verifying   the  lowest  levels  of  host/controller
     6     communication.

     7     In DWM, the controller attempts to echo in the  SA  register  any
     8     data  written into the SA register by the host.  DWM is a special
     9     path through initialization Step 1; Steps 2-4 are suppressed  and
    10     the controller remains disconnected from the host.

    11     DWM is initiated by the setting of the 'WR'  bit  in  the  host's
    12     Step 1 response (see Section 3.2.1, "Standard Initialization Step
    13     1") and takes effect  immediately,  causing  the  host's  Step  1
    14     response to be echoed in the SA register.

    15     DWM is terminated by the  host's  reissuing  a  hard  initialize.
    16     Assuming  the  host  found the results of DWM to be satisfactory,
    17     the host would then bypass DWM during the  second  initialization
    18     sequence.

    19     It is recommended that a diagnostic program which  uses  DWM  not
    20     enable  interrupts  at Step 1.  A controller failure could result
    21     in interrupts to unintended host addresses.

    22     For each  datum  to  be  echoed,  the  host  does  the  following
    23     functions:

    24          1.  Writes any bit pattern into the SA register.

    25          2.  Waits for the SA register to  match  the  data  written.
    26              (This  must  happen  within 10 seconds or the host is to
    27              assume that the controller has failed.)

    28          3.  Loops back to 1 above for another pass.

    29     The sequence is terminated by reinitializing the controller.

    30     6.2  Purge And Poll Tests

    31     These  tests  are   described   in   Section   3.2.3,   "Standard
    32     Initialization Step 3." 





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           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           PORT/CONTROLLER DIAGNOSTIC AND MAINTENANCE FACILITIES    Page 6-2
           Host Memory And Bus Tests                         9 November 1989


     1     6.3  Host Memory And Bus Tests

     2     These  tests  are   described   in   Section   3.2.3,   "Standard
     3     Initialization Step 3." 

     4     6.4  Last Fail Error Packets

     5     Most errors detected by a UQSSP port or associated controller are
     6     reported  with  either a Port Fatal Error Code in the SA register
     7     or with a higher level protocol response packet.   However,  some
     8     errors cannot be reported through such means, since they indicate
     9     that the error reporting communication path or connection  itself
    10     is  not  available.   Last  Fail  Error  Packets  are  a means of
    11     reporting such errors after the communication path or  connection
    12     is restored.

    13     The following types of errors are reported  in  Last  Fail  Error
    14     Packets:

    15          1.  The port or controller  hangs,  resulting  in  the  host
    16              timing  out  and reinitializing the port and controller.
    17              Upon being reinitialized, the port or  controller  notes
    18              the  cause  of  the  hang and reports it in a subsequent
    19              Last Fail Error Packet.

    20          2.  The controller detects that its  communication  path  to
    21              the  port  has failed.  The controller notes the failure
    22              and reports it to the port when the  communication  path
    23              is  subsequently restored.  The port in turn reports the
    24              failure to the host with a Last Fail Error Packet.  Note
    25              that this type of error only occurs in systems where the
    26              port and controller are distinct entities.

    27     Hosts request that a Last Fail Error Packet be reported  to  them
    28     by  setting the LF bit during initialization Step 4.  This has no
    29     effect if the port does not have a last failure  to  report.   If
    30     the  port  does  have a last failure to report, and the host sets
    31     the LF bit, then the port normally returns exactly one Last  Fail
    32     Error  Packet  in  the  first response buffer that the host makes
    33     available.  However, in exceptional circumstances  the  port  may
    34     return  multiple  Last Fail Error Packets, and it may return them
    35     at any  time  so  long  as  the  host-port-controller  connection
    36     persists.

    37     If the host does not set the LF bit, then the port may not report
    38     a  Last  Fail  Error  Packet.  The port should save any Last Fail
    39     Error  Packet  in  case  the  host  sets  LF  in   a   subsequent
    40     initialization, allowing the packet to be reported.  Ports should
    41     attempt to save Last Fail Error Packets until they are  reported,
    42     until  another  failure  occurs,  or until a power fluctuation or


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           PORT/CONTROLLER DIAGNOSTIC AND MAINTENANCE FACILITIES    Page 6-3
           Last Fail Error Packets                           9 November 1989


     1     similar event.  Under normal circumstances each failure should be
     2     reported   only   once,  immediately  following  the  first  port
     3     initialization with LF set after the failure.

     4     Last Fail Error Packets are  formatted  identically  to  MSCP  or
     5     TMSCP  error  log  messages.   The connection ID in the Last Fail
     6     Error Packet message envelope shall be the same as the connection
     7     ID  used  in  normal  operation by the controller attached to the
     8     port.  That is, it shall be 0 (Disk MSCP) if the port is attached
     9     to  a  Disk  MSCP  controller  or  1  (Tape  MSCP) if the port is
    10     attached to a Tape MSCP controller.  If the  controller  supports
    11     both  Disk  and Tape MSCP, then either connection ID may be used.
    12     If the controller supports neither Disk nor  Tape  MSCP,  or  the
    13     port  cannot  determine  which  it supports, then Last Fail Error
    14     Packets may not be reported.

    15     The detailed format of a Last Fail Error Packet is  shown  below.
    16     The  first  longword  is  the  port envelope described in Section
    17     2.3.2,  "Messages  and  Message  Buffers."   Offsets  are   shown
    18     relative  to  the  message  buffer  base,  which  is  the address
    19     contained in the response queue message buffer descriptor.

    20                   31                             0    
    21                   +-------+---+---+---------------+   
    22                   |conn ID|msg|crd|     length    | -4
    23                   +-------+---+---+---------------+   
    24                   |   command reference number    |  0
    25                   +---------------+---------------+   
    26                   |sequence number|    reserved   |  4
    27                   +---------------+-------+-------+   
    28                   |  event code   | flags | format|  8
    29                   +---------------+-------+-------+   
    30                   |                               | 12
    31                   +---  controller identifier  ---+   
    32                   |                               | 16
    33                   +---------------+-------+-------+   
    34                   |port error code| chvrsn! csvrsn| 20
    35                   +---------------+-------+-------+   
    36                   |                               | 24
    37                   /      controller or port       /  .
    38                   /     dependent information     /  .
    39                   |                               |  .
    40                   +-------------------------------+   

    41         length

    42             The length of the Last Fail Error Packet text  in  bytes.
    43             Equal  to  24  plus  the length of the controller or port
    44             dependent information.



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           Storage Systems Port                                Version 3.1.0
           PORT/CONTROLLER DIAGNOSTIC AND MAINTENANCE FACILITIES    Page 6-4
           Last Fail Error Packets                           9 November 1989


     1         crd

     2             Zero.

     3         msg

     4             The value 1, indicating this is a datagram.

     5         conn ID

     6             Either 0 or 1, depending on the  controller  attached  to
     7             the port.  See description above.

     8         command reference number
     9         reserved
    10         sequence number

    11             Zero.

    12         format

    13             Zero, indicating this is  an  MSCP  or  TMSCP  CONTROLLER
    14             ERROR format error log message.

    15         flags

    16             The value 1,  indicating  the  MSCP  or  TMSCP  "Sequence
    17             Number Reset" error log flag is set.

    18         event code

    19             Any event code defined in the MSCP or TMSCP specification
    20             that  is  appropriate for the failure being reported.  In
    21             practice, this should always be a Controller Error  event
    22             code.   If  the  failure  was  a hung port or controller,
    23             resulting in the host timing out and  reinitializing  the
    24             port  or  controller,  then this event code should be the
    25             value 10 (decimal).  That value  indicates  a  controller
    26             timeout.

    27         controller identifier

    28             The MSCP or TMSCP controller identifier, or zero if it is
    29             not available.

    30         csvrsn

    31             The MSCP  or  TMSCP  controller  software,  firmware,  or
    32             microcode   revision   number,  or  zero  if  it  is  not
    33             available.


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           PORT/CONTROLLER DIAGNOSTIC AND MAINTENANCE FACILITIES    Page 6-5
           Last Fail Error Packets                           9 November 1989


     1         chvrsn

     2             The MSCP or TMSCP hardware revision number, or zero if it
     3             is not available.

     4         port error code

     5             Any value listed in Section 2.3.9, "Self  Detected  Fatal
     6             Port/Controller  Errors,"  that  is  appropriate  for the
     7             failure being reported.

     8         controller or port dependent information

     9             Zero  to  36  bytes  of  controller  or  port   dependent
    10             information.

    11     6.5  Special Function Mode

    12     Special Function Mode (SFM) is a method for  controller  specific
    13     functions  to  be implemented.  As an example, this mode could be
    14     used to set a controller's microdiagnostics  to  loop-on-test  in
    15     order  to  assist  module  repair  in  debug  and  testing of the
    16     controller.

    17     SFM support is a controller dependent option.   As  described  in
    18     Section  3.2.1,  "Standard  Initialization  Step 1," a controller
    19     signifies  that  it  supports  SFM  by  returning  SM=1  in   the
    20     transition  to Step 1 SA pattern.  Also mentioned in that section
    21     is that the standard initialization  sequence,  as  described  in
    22     Sections  3.2.1  through 3.2.4, is followed precisely from Step 1
    23     through the transition to Step 4.  However, for controllers  that
    24     provide  SFM support the interpretation of the SA pattern written
    25     by the host in response to the transition to Step 4 differs  from
    26     what is described in Section 3.2.4 as shown below.

    27                     15           9 8 7             0 
    28                     +-------------+-+-------------+-+
    29                     |  reserved   |S|  undefined  |G|
    30                     |             |F|             |O|
    31                     +-------------+-+-------------+-+

    32           SF=1 and GO=1 means that the controller should  enter  SFM,
    33                         if  and  only if the controller returned SM=1
    34                         in the transition to Step 1 SA pattern.

    35                         Note that the controller ignores the value of
    36                         Bits 1 through 7 when SF=1 and GO=1.

    37                         The controller shall  signify  that  SFM  has
    38                         been entered by setting all bits in the SA to


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           Storage Systems Port                                Version 3.1.0
           PORT/CONTROLLER DIAGNOSTIC AND MAINTENANCE FACILITIES    Page 6-6
           Special Function Mode                             9 November 1989


     1                         one (i.e.,  177777  octal)  within  1  second
     2                         after  receipt  of  the SFM enabling pattern.
     3                         If that value is  not  presented  within  the
     4                         specified  time,  the  host is to assume that
     5                         the  controller  has  failed.   Once  SFM  is
     6                         entered  the  operation  of the controller is
     7                         totally   implementation   dependent.     The
     8                         specifics of SFM operation shall be described
     9                         in the controller's Functional Specification.

    10                         SFM is terminated by the host's  reissuing  a
    11                         hard initialize.

    12           SF=0 and GO=1 means that the controller  should  enter  its
    13                         functional  microcode as described in Section
    14                         3.2.4 (if the  controller  returned  SM=1  in
    15                         Step 1 SA data).

    16                    GO=0 the controller  ignores  the  values  of  all
    17                         other  fields  in  the  pattern.  See Section
    18                         3.2.4 for other details in this regard.


    19     Controllers that do not provide SFM support (i.e.,  SM=0  in  the
    20     transition  to Step 1 SA pattern) shall ignore the setting of the
    21     SF bit and interpret the  SA  pattern  written  by  the  host  in
    22     response  to  the  transition  to  Step  4 solely as described in
    23     Section 3.2.4.

    24     6.6  Maintenance Read And Maintenance Write Commands

    25     The intended purpose of Maintenance Read and Maintenance Write is
    26     to  allow  host  based  diagnostics  to read and write controller
    27     internal storage independent of any higher level  protocols.   If
    28     the  controller  cannot  confirm  the functioning of its internal
    29     storage on its own, it is required to  support  Maintenance  Read
    30     and Maintenance Write commands.

    31     The Maintenance Read  and  Maintenance  Write  commands  are  not
    32     formally  part of any higher level protocol.  The host should not
    33     mix maintenance  commands  with  commands  from  a  higher  level
    34     protocol.  The operation of the controller under these conditions
    35     is unspecified.  Further, only one maintenance command at a  time
    36     may  be  issued.  The host is to assume that the controller has a
    37     credit limit of 1 for maintenance commands.







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           Storage Systems Port                                Version 3.1.0
           PORT/CONTROLLER DIAGNOSTIC AND MAINTENANCE FACILITIES    Page 6-7
           Maintenance Read And Maintenance Write Commands   9 November 1989


     1     6.6.1  Maintenance Read Command

     2     The format of the Maintenance Read command packet is given below.
     3     The  displayed packet comprises the text of the message contained
     4     in the earlier specified command/response envelope (beginning  at
     5     word [text+0]).

     6          Command Packet Format:

     7               31                     8 7      0            
     8               +-----------------------+--------+           
     9               |    command reference number    |           
    10               +--------------------------------+           
    11               |           undefined            |           
    12               +-----------------------+--------+           
    13               |      reserved         | opcode | = 030 (8) 
    14               +-----------------------+--------+           
    15               |           byte count           |           
    16               +--------------------------------+           
    17               |                                |           
    18               +---          buffer          ---+           
    19               |                                |           
    20               +---        descriptor        ---+           
    21               |                                |           
    22               +--------------------------------+           
    23               |           region id            |           
    24               +--------------------------------+           
    25               |         region offset          |           
    26               +--------------------------------+           

    27         region id

    28             Selects the internal storage area within  the  controller
    29             referenced by the command.

    30         region offset

    31             Allows access to a specific area within a region.

    32     The  controller  shall  respond  to  the  Maintenance   Read   by
    33     transferring  the  requested  data  to the host buffer (up to the
    34     amount specified by  the  byte  count)  and  then  returning  the
    35     following response:









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           Maintenance Read And Maintenance Write Commands   9 November 1989


     1          End Packet Format:

     2               31            16 15     8 7     0            
     3               +---------------+--------+-------+           
     4               |    command reference number    |           
     5               +--------------------------------+           
     6               |           reserved             |           
     7               +---------------+--------+-------+           
     8               |     status    | unused |endcode| = 230 (8) 
     9               +---------------+--------+-------+           
    10               |          byte count            |           
    11               +--------------------------------+           

    12         Status Codes:

    13             Success
    14             Invalid Command
    15             Host Buffer Access Error

    16                 See Section 6.6.3, "Maintenance  Read/Write  Response
    17                 Status Codes." 

    18         byte count

    19             The byte count field contains a count of  the  number  of
    20             bytes  transferred  to  the  host by the Maintenance Read
    21             command.

























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           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           PORT/CONTROLLER DIAGNOSTIC AND MAINTENANCE FACILITIES    Page 6-9
           Maintenance Read And Maintenance Write Commands   9 November 1989


     1     6.6.2  Maintenance Write Command

     2     The Maintenance Write command is used by the host to send to  the
     3     controller  information  which is outside the scope of the higher
     4     level protocol.

     5     The Maintenance Write command packet format is given below:

     6          Command Packet Format:

     7               31                     8 7      0            
     8               +-----------------------+--------+           
     9               |    command reference number    |           
    10               +--------------------------------+           
    11               |           undefined            |           
    12               +-----------------------+--------+           
    13               |      reserved         | opcode | = 031 (8) 
    14               +-----------------------+--------+           
    15               |           byte count           |           
    16               +--------------------------------+           
    17               |                                |           
    18               +---          buffer          ---+           
    19               |                                |           
    20               +---        descriptor        ---+           
    21               |                                |           
    22               +--------------------------------+           
    23               |           region id            |           
    24               +--------------------------------+           
    25               |         region offset          |           
    26               +--------------------------------+           

    27         region id

    28             Selects the internal storage area within  the  controller
    29             referenced by the command.

    30         region offset

    31             Allows access to a specific area within a region.

    32     The  controller  shall  respond  to  the  Maintenance  Write   by
    33     transferring  the  requested data from the host buffer (up to the
    34     amount specified by  the  byte  count)  and  then  returning  the
    35     following response:








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           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           PORT/CONTROLLER DIAGNOSTIC AND MAINTENANCE FACILITIES   Page 6-10
           Maintenance Read And Maintenance Write Commands   9 November 1989


     1          End Packet Format:

     2               31            16 15     8 7     0            
     3               +---------------+--------+-------+           
     4               |    command reference number    |           
     5               +--------------------------------+           
     6               |            reserved            |           
     7               +---------------+--------+-------+           
     8               |     status    | unused |endcode| = 231 (8) 
     9               +---------------+--------+-------+           
    10               |           byte count           |           
    11               +--------------------------------+           

    12         Status Codes:

    13             Success
    14             Invalid Command
    15             Host Buffer Access Error

    16                 See Section 6.6.3, "Maintenance  Read/Write  Response
    17                 Status Codes." 

    18         byte count

    19             The byte count field contains a count of  the  number  of
    20             bytes  written to the controller by the Maintenance Write
    21             command.

    22     6.6.3  Maintenance Read/Write Response Status Codes

    23     The "status code" field is an 8  bit  field  in  the  Maintenance
    24     Read/Write  response  packet.   The  status  codes  that  may  be
    25     returned in the response packets are listed  below.   The  actual
    26     codes used in the status field are given later in this section.

    27         Success

    28             The command was successfully completed.

    29         Invalid Command

    30             This status code is  used  to  report  invalid  parameter
    31             values or an invalid operation code.

    32         Host Buffer Access Error

    33             The controller encountered an error  during  host  memory
    34             access.  Note that this status code is not used to report
    35             conditions that cause fatal port  errors.   Those  errors
    36             are reported through the SA register.  See Section 2.3.9,


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           Maintenance Read And Maintenance Write Commands   9 November 1989


     1             "Self Detected Fatal Port/Controller Errors."

     2     The  following  are  the  status  code  values  for   Maintenance
     3     Read/Write responses:

     4         Success                       -    0
     5         Invalid Command               -    1
     6         Host Buffer Access Error      -    9












































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           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           CONNECTION ID, PORT TYPE, AND MODEL DEFINITIONS          Page A-1
                                                             9 November 1989


     1                                APPENDIX A

     2              CONNECTION ID, PORT TYPE, AND MODEL DEFINITIONS


     3                     Table A-1:  Connection ID Values

     4           +----------------+----------------------------------+
     5           |    ID Number   |             Purpose              |
     6           |    (Decimal)   |                                  |
     7           +----------------+----------------------------------+
     8           |        0       |       Disk                       |
     9           |        1       |       Tape                       |
    10           |        2       |       DUP                        |
    11           |      3-253     |       Unassigned                 |
    12           |       254      |       Verification Testing       |
    13           |       255      |       Maintenance Protocol       |
    14           +----------------+----------------------------------+


    15                       Table A-2:  Port Type Values

    16           +----------------+----------------------------------+
    17           |     Values     |     Corresponding Port Type      |
    18           |    (Decimal)   |                                  |
    19           +----------------+----------------------------------+
    20           |        0       | Storage Systems Port             |
    21           |       1-7      | Unassigned                       |
    22           +----------------+----------------------------------+























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           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           CONNECTION ID, PORT TYPE, AND MODEL DEFINITIONS          Page A-2
                                                             9 November 1989


     1                   Table A-3:  Controller Model Values

     2           +----------------+----------------------------------+
     3           |   Model Code   |         Controller Type          |
     4           |    (Decimal)   |                                  |
     5           +----------------+----------------------------------+
     6           |        0       |    UDA50                         |
     7           |        1       |    RC25 Integrated Controller    |
     8           |        2       |    RUX50                         |
     9           |        3       |    TQK50/TUK50                   |
    10           |        4       |    Unassigned                    |
    11           |        5       |    TU81 Integrated Controller    |
    12           |        6       |    UDA50A                        |
    13           |        7       |    RQDX1/RQDX2                   |
    14  |        |        8       |    Unassigned                    |
    15  |        |        9       |    Unassigned                    |
    16  |        |       10       |    Unassigned                    |
    17  |        |       11       |    Unassigned                    |
    18  |        |       12       |    Unassigned                    |
    19           |       13       |    KDA50-Q                       |
    20           |       14       |    TQK70                         |
    21           |       15       |    RV20                          |
    22           |       16       |    KRQ50                         |
    23           |       17       |    Unassigned                    |
    24           |       18       |    KDB50                         |
    25           |       19       |    RQDX3                         |
    26           |       20       |    Assigned*                     |
    27           |       21       |    SSP/DSSI Disk                 |
    28           |       22       |    SSP/DSSI Tape                 |
    29           |       23       |    SSP/DSSI Disk and Tape        |
    30           |       24       |    SSP DSSI Other                |
    31           |       25       |    Unassigned                    |
    32  |        |       26       |    Assigned*                     |
    33  |        |       27       |    KDM70                         |
    34  |        |       28       |    Assigned*                     |
    35  |        |       29       |    Assigned*                     |
    36           |       30       |    Unassigned                    |
    37           |       31       |    Unassigned                    |
    38           +----------------+----------------------------------+
    39           | Notes: 1. The  unassigned values are reserved for |
    40           |           assignment   as   new  controllers  are |
    41           |           developed.  The  preferred  method  for |
    42           |           assigning  values to new controllers is |
    43           |           to  keep  the  model  type identical to |
    44           |           those     assigned    in    the    MSCP |
    45           |           Specification,  Table  C-2  (i.e., with |
    46           |           MSCP value assigned first).             |
    47           |                                                   |
    48           |        2. The  asterisk   indicates  that   these |
    49           |           values  are  assigned  to   unannounced |


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           Storage Systems Port                                Version 3.1.0
           CONNECTION ID, PORT TYPE, AND MODEL DEFINITIONS          Page A-3
                                                             9 November 1989



     1                Table A-3: Controller Model Values (cont.)

     2           +----------------+----------------------------------+
     3           |   Model Code   |         Controller Type          |
     4           |    (Decimal)   |                                  |
     5           +----------------+----------------------------------+
     6           |           products and may be found in Appendix E.|
     7           +---------------------------------------------------+











































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           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           PORT FATAL ERROR CODE DEFINITIONS                        Page B-1
                                                             9 November 1989


     1                                APPENDIX B

     2                     PORT FATAL ERROR CODE DEFINITIONS


     3                 Table B-1:  Port Fatal Error Code Ranges

     4           +----------------+----------------------------------+
     5           |      Range     |       Associated Controller      |
     6           |    (Decimal)   |                                  |
     7           +----------------+----------------------------------+
     8           |       0        |    Reserved                      |
     9           |    001-099     |    Generic, all controllers      |
    10           |    100-199     |    UDA50, UDA50A, KDA50-Q,       |
    11           |                |    and KDB50                     |
    12           |    200-299     |    RC25 Integrated Controller    |
    13           |    300-399     |    TU81 Integrated Controller    |
    14           |    400-449     |    RQDX1/RQDX2                   |
    15           |    450-499     |    RQDX3                         |
    16           |    500-599     |    RUX50                         |
    17           |    600-699     |    TQK50/TUK50/TQK70             |
    18           |    700-749     |    KRQ50                         |
    19           |    750-799     |    RV20                          |
    20           |    800-849     |    DSSI Devices                  |
    21  |        |    850-899     |    KDM70                         |
    22  |        |    900-949     |    Assigned*                     |
    23           |    950+        |    Unassigned                    |
    24           +----------------+----------------------------------+
    25           |    Note:  The  asterisk   indicates  that   these |
    26           |           values  are  assigned  to   unannounced |
    27           |           products and may be found in Appendix E.|
    28           +---------------------------------------------------+




















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           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           WAIVERS AND EXCEPTIONS                                   Page C-1
                                                             9 November 1989


     1                                APPENDIX C

     2                          WAIVERS AND EXCEPTIONS

















































                 *** R E S T R I C T E D  D I S T R I B U T I O N ***
           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           REVISION HISTORY                                         Page D-1
                                                             9 November 1989


     1                                APPENDIX D

     2                             REVISION HISTORY


     3     Changes from V1.5 to V2.0

     4          1.  Addition of address mapping functionality.

     5          2.  Addition of byte aligned transfer capability.

     6          3.  Addition  of  controller   model   identifier   to   the
     7              Initialization, Step 4 response.

     8          4.  Changed  Maintenance   Read/Write   functionality   from
     9              required to optional.

    10          5.  Added Maintenance Read/Write response status codes.

    11          6.  Editorial changes.



    12     Changes from V2.0 to V2.0.1

    13          1.  Corrected V2.0 typos.

    14          2.  Editorial changes, not all of which have change bars.

    15          3.  Addition of port fatal error code "23."



    16     Changes from V2.0.1 to V2.0.2

    17          1.  Added additional requirement  that  "Credits"  field  be
    18              ignored when "msgtyp" is maintenance.

    19          2.  Defined the sequence of operations that  the  controller
    20              is to follow when it loads the SA register.

    21          3.  Defined the "ER"  and  step  bits  as  the  SA  register
    22              "qualifier" bits.

    23          4.  Defined action of controller when host reads  IP  before
    24              controller has been initialized.

    25          5.  Redefined bits 30-31 of  the  Mapped  Buffer  Descriptor
    26              second longword as being MBZ rather than "unused."



                 *** R E S T R I C T E D  D I S T R I B U T I O N ***
           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           REVISION HISTORY                                         Page D-2
                                                             9 November 1989


     1     Changes from V2.0.2 to V2.0.3

     2          1.  Clarified the definitions of "message"  and  "envelope."
     3              Changed  the  title of the "Message Envelope" section to
     4              "Messages and Message Buffers."

     5          2.  Made  the  definition  and  usage  of  "message  length"
     6              consistent with the MSCP spec.

     7          3.  Updated port communications area access descriptions.



     8     Changes from V2.0.3 to V2.1

     9          1.  The following approved ECOs to V2.0.3 were incorporated:

    10               o  UQSSP203-3 Addition of QDA
    11               o  UQSSP203-4 Extension of Model Field
    12               o  UQSSP203-6 Loop-on-test for QDA
    13               o  UQSSP203-7 RRD50 Addition
    14               o  UQSSP203-8 Dev.  Ass'n Change
    15               o  UQSSP203-10 RQDX3 Addition
    16               o  UQSSP203-13 Cmd/Rsp Indicators
    17               o  UQSSP203-15 Port Fatal Error  Code  and  Model  Code
    18                  Tables
    19               o  UQSSP203-17 Assignment  of  RQDX4  Controller  Error
    20                  Code
    21               o  UQSSP203-19 UQSSP Last Fail Error Packets
    22               o  UQSSP203-20 Assignment of UQSSP/DSSI Generic  Device
    23                  Types  Controller Model Values and DSSI Device Error
    24                  Code Range

    25              Note that due to technical  inaccuracies  the  following
    26              V2.0.3 ECOs, though approved, were not incorporated into
    27              the specification at this time:

    28               o  UQSSP203-9  KDA50-B   Waiver   /   UQSSP203-11   BDA
    29                  Initialization
    30               o  UQSSP203-14 Microcode Loading

    31              ECO proposals correcting the  problems  found  in  those
    32              ECOs will be submitted to V2.1.

    33              The following editorial changes were performed  (on  the
    34              original and ECO text):

    35              a.  The document was  changed  from  section  format  to
    36                  chapter format.



                 *** R E S T R I C T E D  D I S T R I B U T I O N ***
           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           REVISION HISTORY                                         Page D-3
                                                             9 November 1989


     1              b.  A new section, "DSA Subsystem Overview,"  was  added
     2                  and numerous sections were retitled for clarity.

     3              c.  Original Appendix A  was  eliminated  and  four  new
     4                  appendices were added:


     5                      Appendix A, "Connection ID, Port Type, and Model
     6                      Definitions"  (previously  Sections  11.6, 11.8,
     7                      and 11.9)

     8                      Appendix B, "Port Fatal Error Code  Definitions"
     9                      (previously Section 11.7)

    10                      Appendix C, "Waivers and Exceptions" (new)

    11                      Appendix  D,  "Revision   History"   (previously
    12                      prefaced the document)


    13              d.  Spelling errors corrected.

    14              e.  Punctuation errors corrected.

    15              f.  Rewording of text for the sake of clarity.

    16              g.  Removal of redundant words, phrases, or statements.

    17              h.  Addition of numerous section references.




    18     Changes from V2.1 to V2.2.0

    19           o  Added ECO UQSSP21-1 KFQSA CONID Request

    20           o  Reorganized Appendix D so that the revision history goes
    21              from past to present.

    22           o  Added Appendix E to to store Controller Model Values and
    23              Port   Fatal  Error  Code  Definitions  for  unannounced
    24              products.









                 *** R E S T R I C T E D  D I S T R I B U T I O N ***
           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           REVISION HISTORY                                         Page D-4
                                                             9 November 1989


     1     Changes from V2.2.0 to V3.0.0

     2           o  Changed the name from UQSSP to SSP.

     3           o  Removed   references   to   Unibus   and   Q-Bus   where
     4              appropriate.

     5           o  Rewrote  the  KDB50  waiver  that  was  in  Appendix  C,
     6              removing  KDB50  specifics, correcting technical errors,
     7              and putting it in a format appropriate for a chapter  on
     8              VAXBI implementations of SSP.  That became Chapter 4.

     9           o  Included a new  chapter,  Chapter  5,  on  XMI  (Calypso
    10              Memory Interconnect) implementations of SSP.

    11           o  Pushed the chapter  on  Port/Controller  Diagnostic  and
    12              Maintenance Facilities out to Chapter 6.

    13           o  Added many cross-references throughout the document.

    14           o  Ensured that the terminology  is  consistent  throughout
    15              the spec and with MSCP.

    16           o  Made many editorial changes throughout the document.

    17     Changes from V3.0.0 to V3.0.1

    18           o  Incorporated  ECOs   SSP220-2:    Node   Name   Packets,
    19              SSP220-3:   Eliminate  Race Condition, SSP220-5:  Remove
    20              Interlock Requirement.



    21  |  Changes from V3.0.1 to V3.1.0

    22  |        o  Incorporated ECO SSP30-1:  Extended Communications Area

    23  |        o  Incorporated ECO SSP30-2:  XMI Code Update














                 *** R E S T R I C T E D  D I S T R I B U T I O N ***
           Digital Equipment Corporation        Confidential And Proprietary
           Storage Systems Port                                Version 3.1.0
           UNANNOUNCED PRODUCTS                                     Page E-1
                                                             9 November 1989


     1                                APPENDIX E

     2                           UNANNOUNCED PRODUCTS


     3                   Table E-1:  Controller Model Values

     4                              From Table A-3
     5           +----------------+----------------------------------+
     6           |   Model Code   |         Controller Type          |
     7           |    (Decimal)   |                                  |
     8           +----------------+----------------------------------+
     9           |       20       |    RQDX4                         |
    10           |       26       |    KRU50                         |
    11           |       28       |    TQK7L                         |
    12           |       29       |    TM32                          |
    13           |                |                                  |
    14           +---------------------------------------------------+
    15           |     Note: Model   code   values   21  through  24 |
    16           |           identify  DSSI devices and the specific |
    17           |           higher  level  protocol device class or |
    18           |           classes   a   particular  DSSI   device |
    19           |           supports.  DSSI  Other  merely reserves |
    20           |           Model  code  24  in anticipation of any |
    21           |           new  device  class protocol that may be |
    22           |           defined in the future.                  |
    23           +---------------------------------------------------+




    24                 Table E-2:  Port Fatal Error Code Ranges

    25                              From Table B-1
    26           +----------------+----------------------------------+
    27           |      Range     |       Associated Controller      |
    28           |    (Decimal)   |                                  |
    29           +----------------+----------------------------------+
    30           |    450-499     |    RQDX3/RQDX4                   |
    31           |    600-699     |    TQK50/TUK50/TQK70/TQK7L       |
    32           |    700-749     |    KRQ50/KRU50                   |
    33           |    900-949     |    TM32                          |
    34           +----------------+----------------------------------+









                 *** R E S T R I C T E D  D I S T R I B U T I O N ***
