From rwallace@world.std.com Sun Aug 14 07:31:33 PDT 1994 Article: 2745 of vmsnet.pdp-11 Path: nntp-server.caltech.edu!news.cerf.net!mvb.saic.com!info-pdp11 From: Roger N Wallace Newsgroups: vmsnet.pdp-11 Subject: Re: 11/83 11/93 v 11/70? Message-ID: Date: Sat, 13 Aug 1994 19:47:19 -0400 (EDT) Organization: Info-Pdp11<==>Vmsnet.Pdp-11 Gateway X-Gateway-Source-Info: Mailing List Lines: 24 My understanding is that the 11/93 (11/94) is significantly faster (like 2X) than even the 11/83 (11/84) in terms of raw processor-to-memory access. If you have (under RT11) a VM: device, try a timing for COPY/DEV VM: NL: for a simple comparison. However, in some integrated _system_ applications, the 11/83 or /84 may be a better choice, particularly if you have a lot of peripherals that are doing high-speed DMA. In the 11/83, the cache has dual tags, which permit concurrent processor and peripheral DMA operations. That is, once DMA is granted, the processor can continue perform cache reads while DMA is in progress until a "dirty" location is encountered. In the 11/93, with no cache and all memory on the CPU board, I _think_ memory access is an either/or (but not both) situation. That is, if DMA is granted, the CPU either waits until it completes (or participates in controlling the transaction (?)), returning to the computational task at hand only after the DMA cycle completes. My memory is a bit fuzzy here, but I seem to recall some cries of anguish on the net from the Real-Time-Control folks as the 11/9X machines were introduced -- when they found out that the "New" PDP11 couldn't handle their applications gracefully. Perhaps Bob Schor, Terry Kennedy, or Jack Crowell can comment in a more definitive way on this point. Roger Wallace From terry@spcvxb.spc.edu Sun Aug 14 07:32:08 PDT 1994 Article: 2747 of vmsnet.pdp-11 Newsgroups: vmsnet.pdp-11 Path: nntp-server.caltech.edu!news.cerf.net!usc!howland.reston.ans.net!europa.eng.gtefsd.com!MathWorks.Com!solaris.cc.vt.edu!spcuna!spcvxb!terry From: terry@spcvxb.spc.edu (Terry Kennedy, Operations Mgr.) Subject: Re: 11/83 11/93 v 11/70? Nntp-Posting-Host: spcvxa.spc.edu References: Sender: news@spcuna.spc.edu (Network News) Organization: St. Peter's College, US Date: Sun, 14 Aug 1994 11:50:18 GMT Message-ID: <1994Aug14.075018.1@spcvxb.spc.edu> Lines: 31 In article , Roger N Wallace writes: > However, in some integrated _system_ applications, the 11/83 or /84 > may be a better choice, particularly if you have a lot of peripherals that > are doing high-speed DMA. In the 11/83, the cache has dual tags, which > permit concurrent processor and peripheral DMA operations. That is, once > DMA is granted, the processor can continue perform cache reads while DMA is > in progress until a "dirty" location is encountered. In the 11/93, with no > cache and all memory on the CPU board, I _think_ memory access is an > either/or (but not both) situation. That is, if DMA is granted, the CPU > either waits until it completes (or participates in controlling the > transaction (?)), returning to the computational task at hand only after the > DMA cycle completes. My memory is a bit fuzzy here, but I seem to recall > some cries of anguish on the net from the Real-Time-Control folks as the > 11/9X machines were introduced -- when they found out that the "New" PDP11 > couldn't handle their applications gracefully. The various real-time folks I ran into tended to be upset that the 2MB flavor of the board didn't allow Q-bus memory to be used (since they had lots of non-memory memory, so to speak). I recall somebody talking to DEC about this and the DEC folks said that if there was a reasonable order (I believe this was around 100 boards), they'd do an unsupported version of the card using an older layout that allowed this. There is no cache on the '93 - instead, the whole memory array runs at speeds a PDP-11 would consider "cache speed". So, there's no fancy logic for invalidates, DMA stalls, etc. - the CPU can fetch and execute while a DMA operation is in progress. Terry Kennedy Operations Manager, Academic Computing terry@spcvxa.spc.edu St. Peter's College, Jersey City, NJ USA +1 201 915 9381 (voice) +1 201 435-3662 (FAX)