ebay - cardamatic

[Tony Duell]

> I have heard some TTL logic designs where very bad too.

Alas yes.... Mostly where the so-called designer decided to adulterate 
the circuit with RC delays (not that those are _necessarily_ bad. They're 
like GOTOs in programming. Can be useful, but all to easy to misuse...)

But I never came across a designer who'd randomly change TTL AND gates 
for OR gates in the hope it improved matters...

>  From what little I have seen FPGA's 99% is VHDL and VERLOG

The FPGA tools I used started with a schematic capture program. And I 
certainly saw so-called designers who'd make what appeared to be random 
chagnes (and who couldn't explain their changes), recompile, and hope for 
the best.

Oh, and I rememebr many late nights going through the output of that 
compiler to see what mess it had made of my design this time. Patching 
the output (there was a program that let to display the result as a map 
of the logic blocks on the chip and edit the result) was common...

-tony