HDL vs. schematics (was Re: ebay - cardamatic)

[woodelf]

Patrick Finnegan wrote:

>On Wednesday 16 February 2005 11:36, woodelf wrote:
>  
>
>You can make your own 'adder' block if you really want to.  The good 
>thing about HDLs is that they read more like code than like schematics.
>
I did  and I have ... mind you the code is clean but I need to go back a 
document it.

>And, with good HDL CAD software, like what I used in classes at Purdue, 
>there's a 'schematic capture' package that you can use to connect 
>together block of stuff, and it outputs an HDL file (typically VHDL or 
>Verilog).  Usually when you're designing something large (like the 
>32bit RISC CPU with caching, and virtual memory we built in a class I 
>took), you don't want to concern yourself with gate-level semantics.  
>But, if you want to, you still can.
>  
>
Cough Cough gag ... you know what I think about RISC or CISC's.  I think 
working with
a PDP-8 had a bad impact in my life -- I think of small clean processors 
not risc stuff.
My problem with RISC is the load/store aspect of the designs not the 
concept of reduced
instructions.

>>If you care about something like that you can define your own (another 
>>person's) adder like I was showing above, and use that
>>    
>>
Well everybody seems to be re-inventing the wheel.  While I have not 
looked too hard
I have yet to find  (or  designed ) a clean  ALU block  with shifting.

>>Pat
>>    
>>
Ben alias woodelf.