HDL vs. schematics (was Re: ebay - cardamatic)

[woodelf]

Eric Smith wrote:

>I needed a carry lookahead adder for a 512-macrocell CPLD a while back,
>so I wrote one in VHDL.  Took about half an hour to write the adder,
>a test bench, and simulate it.  It would have taken me much longer to
>draw a schematic of one (even using some predefined components) and a
>set of test vectors.
>
>  
>
Well  I am using CUPL since that is the software  Amtel CPLD's uses.
%$#! is my comments on the compiler since it crashes on syntax errors like
a missing ';' or say a forgetten '& ' and you have no idea on just where 
to find
your bug.  Once the the bugs in the code are found then I  have no problems
with HDL's.  Just like C compilers , I like to have the abilty have the 
final
say in the program rather the compiler having the last word.

>Normally for FPGA design, ripply carry is perferred, because there
>is a very fast hardware carry chain in the FPGA.  Using carry lookahead,
>carry skip, carry save, and other such techniques actually results in
>a much slower adder.  But if you're doing an ASIC design, the tradeoffs
>are different.  Good ASIC synthesis tools let you choose what kind of
>adder will be generated, but for FPGAs there is no point.
>  
>
However FPGA fast ripple adders really don't give you  the real idea  of
the FPGA logic speeds since this  is a trick on the FPGA venders to lie
about the speed of the system

>One nice thing about VHDL is that I don't have to zoom in and out.
>Any reasonably sized VHDL module fits just fine in my emacs window.
>
>Also it is much easier to "grep" HDL code.  I spent an hour yesterday
>trying to find an obscure signal on a twelve page schematic; if it
>had been VHDL I would have found it in ten seconds.
>  
>
I tend to do the comple this ... nope it don't fit ... edit edit ... how 
about this idea ...
in developing the bit slices I will be using for my cpu design. Mostly I 
am I/O
bound ... a 84 pin CPLD only has about 64 real I/O pins. I need to be 6
bits wide since I am doing a 18 bit cpu and i/o pins seem to be the 
limiting factor.
I do agree that text ediiting is a lot faster than schematic revising.

>>I have used FPGA's and found CPLD's to be the 'right size'.
>>    
>>
>
>CPLDs are the "right size" for some things, and not for others.
>That's obvious, or there wouldn't be a market for FPGAs.
>
>But I find VHDL to work great for CPLD design as well.
>  
>
If I could figure out what is  generated in VHDL since I find it too verbose
for my likeing and a free compiler I think I  would have more positive
things to say about VHDL.  I  don't have $$$ to burn for licences
and upgrades every few months.  CUPL is  smallish rather than too big
and I don't need to upgrade it.

>In the US, Verilog seems to be more popular than VHDL.  However, I
>prefer VHDL as it is much more expressive.  Though "System Verilog"
>has apparently filled in some of the gaps.
>
>Eric
>  
>