q about PDP11/34 schematics (clock generation)

[Tony Duell]

> 
> 
> 
> Tony Duell wrote:
> > 
> > A delay line is what the name implies. A component that delays a signal,
> > here a digital signal. If the input changes, then the output changes a
> > certain time (here 150ns) later.
> 
> How precise is it? Is it comparable to a crystal oscillator regarding
> stability and accuracy?

I would guess it's considerably less accurate than a crystal, and a bit 
less stable (although not too bad). I wouldn't want to use one, for 
example, as the reference for a real time clock.

One advantage of the delay line approach is that you can get several 
clocks offset from each other by know time delays (one from each tap of 
the line). This is probably why DEC used it in the 11/34

> 
> > The reason for multiple outputs (often called 'taps' is that you can get
> > signals delayed by different amounts. A 150ns delay line may have 5 taps,
> > say, 30ns apart. If the input changes, the first tap changes after
> > 30ns,the next after 60ns, etc.
> 
> Are these typically linear distributed? I mean: are the time differences
> between the taps always the same?

For the stnadard off-the-shelf delay lines, yes. I am sure custom ones 
have been made, though, with taps at odd positions.

-tony