.TOC	"VVAX.MIC -- VVAX Option Instructions"
.TOC	"Revision 2.0"

;	Bob Supnik

.nobin
;****************************************************************************
;*									    *
;*  COPYRIGHT (c) 1988, 1989 BY					    	    *
;*  DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS.		    *
;*  ALL RIGHTS RESERVED.						    *
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;*  THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED   *
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;*  AND  SHOULD  NOT  BE  CONSTRUED AS  A COMMITMENT BY DIGITAL EQUIPMENT   *
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;****************************************************************************
.TOC	"	Revision History"

; Edit	  Date	 Who	     Description
; ---- --------- ---	---------------------
; (2)0 19-Nov-89 RMS	Revised for simplified decoder.
; (1)0 11-Jun-89 RMS	Revised for release to CMS.
;    2 01-Feb-89 RMS	Revised for new microbranch latencies.
;    1 10-Jan-89 RMS	Revised for new microarchitecture.
; (0)0 04-Oct-88 RMS	First edit for Raven.

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;= BEGIN VVAX
.nobin

;	This module implements the VVAX option instruction class.
;	The instructions in this class are:
;
;	Opcode	 Instruction							N Z V C		Exceptions
;	------	 -----------							-------		----------
;
;	02FD	 WAIT								0 0 0 0		prv
;	9AFD	 PROBEVMR mode.rl, base.ab					* * * *		vm, prv
;	9BFD	 PROBEVMW mode.rl, base.ab					* * * *		vm, prv
.TOC	"	WAIT"

;	This instruction signals idle processor time in a virtual machine.
;
;	Mnemonic      Opcode	Operation				Spec	AT/DL	CC	Dispatch	BCOND
;	--------      ------	---------				----	-----	--	--------	-----
;	WAIT		02FD	wait for interrupt			 0	 --	--	IE.RSRV.OPCODE   --
;
;	Entry conditions:
;		None.
;
;	Exit conditions:
;		Reserved instruction fault initiated.
;
;	Condition codes:
;		N <-- 0			(in exception flows)
;		Z <-- 0
;		V <-- 0			[Integer overflow trap disabled.]
;		C <-- 0
;
;	Tradeoffs:
;		None.
;
;	Notes:
;		1) This instruction is implemented as a reserved opcode by the I Box and is dispatched
;		   directly to IE.RSRV.OPCODE in INTEXC.MIC.  It is included here simply for documentation
;		   purposes.
.TOC	"	PROBEVMx"

;	These instructions probe the accessibility of a byte in a virtual machine.
;
;	Mnemonic      Opcode	Operation				Spec	AT/DL	CC	Dispatch	BCOND
;	--------      ------	---------				----	-----	--	--------	-----
;	PROBEVMR	9AFD	probe vm read accessibility		 2	ra/lb	--	PROBEVMX	--
;	PROBEVMW	9BFD	probe vm write accessibility		 2	ra/lb	--	PROBEVMX	--
;
;
;	Entry conditions:
;		W0	=	first (mode) operand
;		W2	=	second (base address) operand
;		DL	=	data length of second operand (byte)
;
;	Exit conditions:
;		The PSL condition codes reflect the result of the probe test.
;
;	Condition codes:
;		N <-- {access control violation}
;		Z <-- {reference allowed}
;		V <-- {translation not valid}	[Integer overflow trap disabled.]
;		C <-- {page not previously modified and PROBEVMW}
;
;	Tradeoffs:
;		None.
;
;	Notes:
;		1) Because the last specifier is address mode, register references are trapped
;		   by the I box, and no register entry point is needed.

.bin

PROBEVMX:
	;********** Hardware dispatch **********;
	RESERVED INSTRUCTION FAULT		; dispatch to exception processing

;= END VVAX