## ASxxxx Cross Assembler Documentation

                                    ASxxxx Assemblers

                                           and

                                ASLINK Relocating Linker

                                     Version   4.00
                                      November 2003

            CHAPTER 1  THE ASSEMBLER                                     1-1
              1.1     THE ASXXXX ASSEMBLERS                              1-1
              1.1.1     Assembly Pass 1                                  1-2
              1.1.2     Assembly Pass 2                                  1-2
              1.1.3     Assembly Pass 3                                  1-2
              1.2     SOURCE PROGRAM FORMAT                              1-3
              1.2.1     Statement Format                                 1-3
              1.2.1.1     Label Field                                    1-3
              1.2.1.2     Operator Field                                 1-5
              1.2.1.3     Operand Field                                  1-5
              1.2.1.4     Comment Field                                  1-6
              1.3     SYMBOLS AND EXPRESSIONS                            1-6
              1.3.1     Character Set                                    1-6
              1.3.2     User-Defined Symbols                            1-10
              1.3.3     Reusable Symbols                                1-10
              1.3.4     Current Location Counter                        1-12
              1.3.5     Numbers                                         1-13
              1.3.6     Terms                                           1-14
              1.3.7     Expressions                                     1-14
              1.4     GENERAL ASSEMBLER DIRECTIVES                      1-16
              1.4.1     .module Directive                               1-16
              1.4.2     .title Directive                                1-16
              1.4.3     .sbttl Directive                                1-17
              1.4.4     .page Directive                                 1-17
              1.4.5     .msg Directive                                  1-17
              1.4.6     .error Directive                                1-17
              1.4.7     .byte, .db, and .fcb Directives                 1-18
              1.4.8     .word, .dw, and .fdb Directives                 1-18
              1.4.9     .3byte and .triple Directives                   1-19
              1.4.10    .4byte and .quad Directive                      1-19
              1.4.11    .blkb, .ds, ,rmb, and .rs Directives            1-20
              1.4.12    .blkw, .blk3, and .blk4 Directives              1-20
              1.4.13    .ascii, .str, and .fcc Directives               1-20
              1.4.14    .ascis and .strs Directives                     1-21
              1.4.15    .asciz and .strz Directives                     1-21
              1.4.16    .assume Directive                               1-22
              1.4.17    .radix Directive                                1-22
              1.4.18    .even Directive                                 1-22
              1.4.19    .odd Directive                                  1-23
              1.4.20    .area Directive                                 1-23
              1.4.21    .bank Directive                                 1-25
              1.4.22    .org Directive                                  1-26
              1.4.23    .globl Directive                                1-27
              1.4.24    .local Directive                                1-27
              1.4.25    .equ, .gblequ, and .lclequ Directives           1-28
              1.4.26    .if, .else, and .endif Directives               1-28
              1.4.27    .ifdef, .else, and .endif Directives            1-29
              1.4.28    .ifndef, .else, and .endif Directives           1-30
              1.4.29    .include Directive                              1-31
              1.4.30    .define and .undefine Directives                1-31
              1.4.31    .setdp Directive                                1-32
              1.4.32    .16bit, .24bit, and .32bit Directives           1-34
              1.4.33    .end Directive                                  1-34
              1.5     INVOKING ASXXXX                                   1-35
              1.6     ERRORS                                            1-36
              1.7     LISTING FILE                                      1-37

                                                                     Page ii

              1.8     SYMBOL TABLE FILE                                 1-39
              1.9     OBJECT FILE                                       1-40

            CHAPTER 2  THE LINKER                                        2-1
              2.1     ASLINK RELOCATING LINKER                           2-1
              2.2     INVOKING ASLINK                                    2-2
              2.3     LIBRARY PATH(S) AND FILE(S)                        2-3
              2.4     ASLINK PROCESSING                                  2-4
              2.5     ASXXXX VERSION 4.XX LINKING                        2-7
              2.5.1     Object Module Format                             2-7
              2.5.2     Header Line                                      2-8
              2.5.3     Module Line                                      2-8
              2.5.4     Merge Mode Line                                  2-8
              2.5.5     Bank Line                                        2-9
              2.5.6     Area Line                                        2-9
              2.5.7     Symbol Line                                      2-9
              2.5.8     T Line                                          2-10
              2.5.9     R Line                                          2-10
              2.5.10    P Line                                          2-11
              2.5.11    24-Bit and 32-Bit Addressing                    2-11
              2.5.12    ASlink V4.xx Error Messages                     2-12
              2.6     ASXXXX VERSION 3.XX LINKING                       2-14
              2.6.1     Object Module Format                            2-14
              2.6.2     Header Line                                     2-14
              2.6.3     Module Line                                     2-15
              2.6.4     Area Line                                       2-15
              2.6.5     Symbol Line                                     2-15
              2.6.6     T Line                                          2-15
              2.6.7     R Line                                          2-16
              2.6.8     P Line                                          2-16
              2.6.9     24-Bit and 32-Bit Addressing                    2-17
              2.6.10    ASlink V3.xx Error Messages                     2-17
              2.7     INTEL IHX OUTPUT FORMAT (16-BIT)                  2-20
              2.8     INTEL I86 OUTPUT FORMAT (24 OR 32-BIT)            2-21
              2.9     MOTORLA S1-S9 OUTPUT FORMAT (16-BIT)              2-22
              2.10    MOTORLA S2-S8 OUTPUT FORMAT (24-BIT)              2-23
              2.11    MOTORLA S3-S7 OUTPUT FORMAT (32-BIT)              2-24

            CHAPTER 3  BUILDING ASXXXX AND ASLINK                        3-1
              3.1     BUILDING AN ASSEMBLER                              3-1
              3.2     BUILDING ASLINK                                    3-2

            APPENDIX A  ASAVR ASSEMBLER                                  A-1
              A.1     AVR ASSEMBLER NOTES                                A-1
              A.1.1     Processor Specific Directive                     A-1
              A.2     AVR REGISTER SET                                   A-2
              A.3     AVR INSTRUCTION SET                                A-2
              A.3.1     AVR Arithmetic and Logical Instructions          A-4
              A.3.2     AVR Bit and Bit-Test Instructions                A-5
              A.3.3     AVR Skip on Test Instructions                    A-5
              A.3.4     AVR Jump/Call/Return Instructions                A-5
              A.3.5     AVR Short Branch Instructions                    A-5

                                                                    Page iii

              A.3.6     AVR Short Branch Instructions with Bit Test      A-6
              A.3.7     AVR Data Transfer Instructions                   A-6

            APPENDIX B  ASPIC ASSEMBLER                                  B-1
              B.1     PIC ASSEMBLER NOTES                                B-1
              B.2     PROCESSOR SPECIFIC DIRECTIVES                      B-1
              B.2.1     .pic Directive                                   B-2
              B.2.2     .picnopic Directive                              B-2
              B.2.3     .pic12bit Directive                              B-3
              B.2.4     .pic14bit Directive                              B-3
              B.2.5     .pic16bit Directive                              B-3
              B.2.6     .pic20bit Directive                              B-3
              B.2.7     .picfix Directive                                B-4
              B.2.8     .maxram Directive                                B-4
              B.2.9     .badram Directive                                B-4
              B.2.10    .setdmm Directive                                B-5
              B.3     12-BIT OPCODE PIC                                  B-5
              B.4     14-BIT OPCODE PIC                                  B-6
              B.5     16-BIT OPCODE PIC                                  B-7
              B.6     20-BIT ADDRESSING PIC                              B-8
              B.7     PIC OPCODES                                       B-10

            APPENDIX C  ASRAB ASSEMBLER                                  C-1
              C.1     ACKNOWLEDGMENT                                     C-1
              C.2     PROCESSOR SPECIFIC DIRECTIVES                      C-1
              C.2.1     .r2k Directive                                   C-2
              C.2.2     .hd64 Directive                                  C-2
              C.2.3     .z80 Directive                                   C-2
              C.3     RABBIT 2000/3000 ADDRESSING AND INSTRUCTIONS       C-3
              C.3.1     Instruction Symbols                              C-3
              C.3.2     Rabbit Instructions                              C-5
              C.4     Z80/HD64180 ADDRESSING AND INSTRUCTIONS            C-7
              C.4.1     Inherent Instructions                            C-8
              C.4.2     Implicit Operand Instructions                    C-8
              C.4.3     Load Instruction                                 C-9
              C.4.4     Call/Return Instructions                         C-9
              C.4.5     Jump and Jump to Subroutine Instructions         C-9
              C.4.6     Bit Manipulation Instructions                   C-10
              C.4.7     Interrupt Mode and Reset Instructions           C-10
              C.4.8     Input and Output Instructions                   C-10
              C.4.9     Register Pair Instructions                      C-10
              C.4.10    HD64180 Specific Instructions                   C-11

            APPENDIX D  AS8XCXXX ASSEMBLER                               D-1
              D.1     ACKNOWLEDGMENTS                                    D-1
              D.2     DS8XCXXX ASSEMBLER DIRECTIVES                      D-1
              D.2.1     DS80C390 Addressing Mode Directive               D-2
              D.3     DS8XCXXX REGISTER SET                              D-3
              D.4     DS8XCXXX INSTRUCTION SET                           D-3
              D.4.1     Inherent Instructions                            D-4
              D.4.2     Move Instructions                                D-4
              D.4.3     Single Operand Instructions                      D-4

                                                                     Page iv

              D.4.4     Two Operand Instructions                         D-5
              D.4.5     Call and Return Instructions                     D-5
              D.4.6     Jump Instructions                                D-5
              D.5     DS8XCXXX SPECIAL FUNCTION REGISTERS                D-6
              D.5.1     SFR Map                                          D-6
              D.5.2     Bit Addressable Registers:  Generic              D-7
              D.5.3     Bit Addressable Registers:  Specific             D-8
              D.5.4     Optional Symbols:  Control Bits                  D-9
              D.6     DS80C310 SPECIAL FUNCTION REGISTERS               D-10
              D.6.1     SFR Map                                         D-10
              D.6.2     Bit Addressable Registers:  Generic             D-11
              D.6.3     Bit Addressable Registers:  Specific            D-12
              D.6.4     Optional Symbols:  Control Bits                 D-13
              D.7     DS80C320/DS80C323 SPECIAL FUNCTION REGISTERS      D-14
              D.7.1     SFR Map                                         D-14
              D.7.2     Bit Addressable Registers:  Generic             D-15
              D.7.3     Bit Addressable Registers:  Specific            D-16
              D.7.4     Optional Symbols:  Control Bits                 D-17
              D.8     DS80C390 SPECIAL FUNCTION REGISTERS               D-18
              D.8.1     SFR Map                                         D-18
              D.8.2     Bit Addressable Registers:  Generic             D-19
              D.8.3     Bit Addressable Registers:  Specific            D-20
              D.8.4     Optional Symbols:  Control Bits                 D-21
              D.9     DS83C520/DS87C520 SPECIAL FUNCTION REGISTERS      D-23
              D.9.1     SFR Map                                         D-23
              D.9.2     Bit Addressable Registers:  Generic             D-24
              D.9.3     Bit Addressable Registers:  Specific            D-25
              D.9.4     Optional Symbols:  Control Bits                 D-26
              D.10    DS83C530/DS87C530 SPECIAL FUNCTION REGISTERS      D-27
              D.10.1    SFR Map                                         D-27
              D.10.2    Bit Addressable Registers:  Generic             D-28
              D.10.3    Bit Addressable Registers:  Specific            D-29
              D.10.4    Optional Symbols:  Control Bits                 D-30
              D.11    DS83C550/DS87C550 SPECIAL FUNCTION REGISTERS      D-31
              D.11.1    SFR Map                                         D-31
              D.11.2    Bit Addressable Registers:  Generic             D-33
              D.11.3    Bit Addressable Registers:  Specific            D-34
              D.11.4    Optional Symbols:  Control Bits                 D-36

            APPENDIX E  ASZ80 ASSEMBLER                                  E-1
              E.1     .hd64 DIRECTIVE                                    E-1
              E.2     Z80 REGISTER SET AND CONDITIONS                    E-1
              E.3     Z80 INSTRUCTION SET                                E-2
              E.3.1     Inherent Instructions                            E-3
              E.3.2     Implicit Operand Instructions                    E-3
              E.3.3     Load Instruction                                 E-4
              E.3.4     Call/Return Instructions                         E-4
              E.3.5     Jump and Jump to Subroutine Instructions         E-4
              E.3.6     Bit Manipulation Instructions                    E-5
              E.3.7     Interrupt Mode and Reset Instructions            E-5
              E.3.8     Input and Output Instructions                    E-5
              E.3.9     Register Pair Instructions                       E-5

                                                                      Page v

              E.3.10    HD64180 Specific Instructions                    E-6

            APPENDIX F  ASGB ASSEMBLER                                   F-1
              F.1     ACKNOWLEDGEMENT                                    F-1
              F.2     INTRODUCTION                                       F-1
              F.3     GAMEBOY REGISTER SET AND CONDITIONS                F-1
              F.4     GAMEBOY INSTRUCTION SET                            F-2
              F.4.1     .tile Directive                                  F-2
              F.4.2     Potentially Controversial Mnemonic Selection     F-4
              F.4.2.1     Auto-Indexing Loads                            F-4
              F.4.2.2     Input and Output Operations                    F-4
              F.4.2.3     The 'stop' Instruction                         F-5
              F.4.3     Inherent Instructions                            F-5
              F.4.4     Implicit Operand Instructions                    F-5
              F.4.5     Load Instructions                                F-6
              F.4.6     Call/Return Instructions                         F-6
              F.4.7     Jump Instructions                                F-6
              F.4.8     Bit Manipulation Instructions                    F-6
              F.4.9     Input and Output Instructions                    F-7
              F.4.10    Register Pair Instructions                       F-7

            APPENDIX G  AS430 ASSEMBLER                                  G-1
              G.1     MPS430 REGISTER SET                                G-1
              G.2     MPS430 ADDRESSING MODES                            G-2
              G.2.1     MPS430 Instruction Mnemonics                     G-3

            APPENDIX H  ASH8 ASSEMBLER                                   H-1
              H.1     H8/3XX REGISTER SET                                H-1
              H.2     H8/3XX INSTRUCTION SET                             H-1
              H.2.1     Inherent Instructions                            H-2
              H.2.2     Branch Instructions                              H-2
              H.2.3     Single Operand Instructions                      H-3
              H.2.4     Double Operand Instructions                      H-4
              H.2.5     Mov Instructions                                 H-5
              H.2.6     Bit Manipulation Instructions                    H-6
              H.2.7     Extended Bit Manipulation Instructions           H-7
              H.2.8     Condition Code Instructions                      H-7
              H.2.9     Other Instructions                               H-8
              H.2.10    Jump and Jump to Subroutine Instructions         H-8

            APPENDIX I  AS6800 ASSEMBLER                                 I-1
              I.1     6800 REGISTER SET                                  I-1
              I.2     6800 INSTRUCTION SET                               I-1
              I.2.1     Inherent Instructions                            I-2
              I.2.2     Branch Instructions                              I-2
              I.2.3     Single Operand Instructions                      I-3
              I.2.4     Double Operand Instructions                      I-4
              I.2.5     Jump and Jump to Subroutine Instructions         I-4
              I.2.6     Long Register Instructions                       I-5

            APPENDIX J  AS6801 ASSEMBLER                                 J-1
              J.1     .hd6303 DIRECTIVE                                  J-1

                                                                     Page vi

              J.2     6801 REGISTER SET                                  J-1
              J.3     6801 INSTRUCTION SET                               J-1
              J.3.1     Inherent Instructions                            J-2
              J.3.2     Branch Instructions                              J-2
              J.3.3     Single Operand Instructions                      J-3
              J.3.4     Double Operand Instructions                      J-4
              J.3.5     Jump and Jump to Subroutine Instructions         J-5
              J.3.6     Long Register Instructions                       J-5
              J.3.7     6303 Specific Instructions                       J-5

            APPENDIX K  AS6804 ASSEMBLER                                 K-1
              K.1     6804 REGISTER SET                                  K-1
              K.2     6804 INSTRUCTION SET                               K-1
              K.2.1     Inherent Instructions                            K-2
              K.2.2     Branch Instructions                              K-2
              K.2.3     Single Operand Instructions                      K-2
              K.2.4     Jump and Jump to Subroutine Instructions         K-2
              K.2.5     Bit Test Instructions                            K-2
              K.2.6     Load Immediate data Instruction                  K-3
              K.2.7     6804 Derived Instructions                        K-3

            APPENDIX L  AS6805 ASSEMBLER                                 L-1
              L.1     6805 REGISTER SET                                  L-1
              L.2     6805 INSTRUCTION SET                               L-1
              L.2.1     Control Instructions                             L-2
              L.2.2     Bit Manipulation Instructions                    L-2
              L.2.3     Branch Instructions                              L-2
              L.2.4     Read-Modify-Write Instructions                   L-3
              L.2.5     Register\Memory Instructions                     L-3
              L.2.6     Jump and Jump to Subroutine Instructions         L-4

            APPENDIX M  AS6808 ASSEMBLER                                 M-1
              M.1     68HC08 REGISTER SET                                M-1
              M.2     68HC08 INSTRUCTION SET                             M-1
              M.2.1     Control Instructions                             M-2
              M.2.2     Bit Manipulation Instructions                    M-2
              M.2.3     Branch Instructions                              M-3
              M.2.4     Complex Branch Instructions                      M-3
              M.2.5     Read-Modify-Write Instructions                   M-4
              M.2.6     Register\Memory Instructions                     M-5
              M.2.7     Double Operand Move Instruction                  M-5
              M.2.8     16-Bit  Index Register Instructions         M-5
              M.2.9     Jump and Jump to Subroutine Instructions         M-5

            APPENDIX N  AS6809 ASSEMBLER                                 N-1
              N.1     6809 REGISTER SET                                  N-1
              N.2     6809 INSTRUCTION SET                               N-1
              N.2.1     Inherent Instructions                            N-3
              N.2.2     Short Branch Instructions                        N-3
              N.2.3     Long Branch Instructions                         N-3
              N.2.4     Single Operand Instructions                      N-4
              N.2.5     Double Operand Instructions                      N-5

                                                                    Page vii

              N.2.6     D-register Instructions                          N-5
              N.2.7     Index/Stack Register Instructions                N-5
              N.2.8     Jump and Jump to Subroutine Instructions         N-6
              N.2.9     Register - Register Instructions                 N-6
              N.2.10    Condition Code Register Instructions             N-6
              N.2.11    6800 Compatibility Instructions                  N-6

            APPENDIX O  AS6811 ASSEMBLER                                 O-1
              O.1     68HC11 REGISTER SET                                O-1
              O.2     68HC11 INSTRUCTION SET                             O-1
              O.2.1     Inherent Instructions                            O-2
              O.2.2     Branch Instructions                              O-2
              O.2.3     Single Operand Instructions                      O-3
              O.2.4     Double Operand Instructions                      O-4
              O.2.5     Bit Manupulation Instructions                    O-4
              O.2.6     Jump and Jump to Subroutine Instructions         O-5
              O.2.7     Long Register Instructions                       O-5

            APPENDIX P  AS6812 ASSEMBLER                                 P-1
              P.1     68HC12 REGISTER SET                                P-1
              P.2     68HC12 INSTRUCTION SET                             P-1
              P.2.1     Inherent Instructions                            P-3
              P.2.2     Short Branch Instructions                        P-3
              P.2.3     Long Branch Instructions                         P-3
              P.2.4     Branch on Decrement, Test, or Increment          P-4
              P.2.5     Bit Clear and Set Instructions                   P-4
              P.2.6     Branch on Bit Clear or Set                       P-4
              P.2.7     Single Operand Instructions                      P-5
              P.2.8     Double Operand Instructions                      P-6
              P.2.9     Move Instructions                                P-6
              P.2.10    D-register Instructions                          P-6
              P.2.11    Index/Stack Register Instructions                P-7
              P.2.12    Jump and Jump/Call to Subroutine
                        Instructions                                     P-7
              P.2.13    Other Special Instructions                       P-7
              P.2.14    Register - Register Instructions                 P-7
              P.2.15    Condition Code Register Instructions             P-7
              P.2.16    M68HC11 Compatibility Mode Instructions          P-8

            APPENDIX Q  AS6816 ASSEMBLER                                 Q-1
              Q.1     68HC16 REGISTER SET                                Q-1
              Q.2     68HC16 INSTRUCTION SET                             Q-1
              Q.2.1     Inherent Instructions                            Q-2
              Q.2.2     Push/Pull Multiple Register Instructions         Q-3
              Q.2.3     Short Branch Instructions                        Q-3
              Q.2.4     Long Branch Instructions                         Q-3
              Q.2.5     Bit Manipulation Instructions                    Q-3
              Q.2.6     Single Operand Instructions                      Q-4
              Q.2.7     Double Operand Instructions                      Q-5
              Q.2.8     Index/Stack Register Instructions                Q-5
              Q.2.9     Jump and Jump to Subroutine Instructions         Q-6
              Q.2.10    Condition Code Register Instructions             Q-6

                                                                   Page viii

              Q.2.11    Multiply and Accumulate Instructions             Q-6

            APPENDIX R  AS8051 ASSEMBLER                                 R-1
              R.1     ACKNOWLEDGMENT                                     R-1
              R.2     8051 REGISTER SET                                  R-1
              R.3     8051 INSTRUCTION SET                               R-2
              R.3.1     Inherent Instructions                            R-2
              R.3.2     Move Instructions                                R-3
              R.3.3     Single Operand Instructions                      R-3
              R.3.4     Two Operand Instructions                         R-4
              R.3.5     Call and Return Instructions                     R-4
              R.3.6     Jump Instructions                                R-4
              R.3.7     Predefined Symbols:  SFR Map                     R-5
              R.3.8     Predefined Symbols:  SFR Bit Addresses           R-6
              R.3.9     Predefined Symbols:  Control Bits                R-7

            APPENDIX S  AS8085 ASSEMBLER                                 S-1
              S.1     8085 REGISTER SET                                  S-1
              S.2     8085 INSTRUCTION SET                               S-1
              S.2.1     Inherent Instructions                            S-2
              S.2.2     Register/Memory/Immediate Instructions           S-2
              S.2.3     Call and Return Instructions                     S-2
              S.2.4     Jump Instructions                                S-2
              S.2.5     Input/Output/Reset Instructions                  S-3
              S.2.6     Move Instructions                                S-3
              S.2.7     Other Instructions                               S-3

            APPENDIX T  AS6500 ASSEMBLER                                 T-1
              T.1     ACKNOWLEDGMENT                                     T-1
              T.2     6500 REGISTER SET                                  T-2
              T.3     6500 INSTRUCTION SET                               T-2
              T.3.1     Processor Specific Directives                    T-3
              T.3.2     65xx Core Inherent Instructions                  T-3
              T.3.3     65xx Core Branch Instructions                    T-3
              T.3.4     65xx Core Single Operand Instructions            T-3
              T.3.5     65xx Core Double Operand Instructions            T-4
              T.3.6     65xx Core Jump and Jump to Subroutine
                        Instructions                                     T-4
              T.3.7     65xx Core Miscellaneous X and Y Register
                        Instructions                                     T-4
              T.3.8     65F11 and 65F12 Specific Instructions            T-5
              T.3.9     65C00/21 and 65C29 Specific Instructions         T-5
              T.3.10    65C02, 65C102, and 65C112 Specific
                        Instructions                                     T-6

            APPENDIX U  AS740 ASSEMBLER                                  U-1
              U.1     ACKNOWLEDGMENT                                     U-1
              U.2     740 REGISTER SET                                   U-1
              U.3     740 INSTRUCTION SET                                U-1
              U.3.1     Inherent Instructions                            U-3
              U.3.2     Branch Instructions                              U-3
              U.3.3     Single Operand Instructions                      U-3

                                                                     Page ix

              U.3.4     Double Operand Instructions                      U-4
              U.3.5     Jump and Jump to Subroutine Instructions         U-4
              U.3.6     Miscellaneous X and Y Register Instructions      U-4
              U.3.7     Bit Instructions                                 U-4
              U.3.8     Other Instructions                               U-4

            APPENDIX V  AS1802 ASSEMBLER                                 V-1
              V.1     ACKNOWLEDGMENT                                     V-1
              V.2     1802 REGISTER SET                                  V-1
              V.3     1802 INSTRUCTION SET                               V-1
              V.3.1     1802 Inherent Instructions                       V-2
              V.3.2     1802 Short Branch Instructions                   V-2
              V.3.3     1802 Long Branch Instructions                    V-3
              V.3.4     1802 Immediate Instructions                      V-3
              V.3.5     1802 Register Instructions                       V-3
              V.3.6     1802 Input and Output Instructions               V-3
              V.3.7     CDP1802 COSMAC Microprocessor Instruction
                        Set Summary                                      V-4

            APPENDIX W  AS61860 ASSEMBLER                                W-1
              W.1     ACKNOWLEDGMENT                                     W-1
              W.2     61860 REGISTER SET                                 W-1
              W.3     PROCESSOR SPECIFIC DIRECTIVES                      W-2
              W.4     61860 INSTRUCTION SET                              W-2
              W.4.1     Load Immediate Register                          W-3
              W.4.2     Load Accumulator                                 W-3
              W.4.3     Store Accumulator                                W-3
              W.4.4     Move Data                                        W-3
              W.4.5     Exchange Data                                    W-4
              W.4.6     Stack Operations                                 W-4
              W.4.7     Block Move Data                                  W-4
              W.4.8     Block Exchange Data                              W-4
              W.4.9     Increment and Decrement                          W-5
              W.4.10    Increment/Decrement with Load/Store              W-5
              W.4.11    Fill                                             W-5
              W.4.12    Addition and Subtraction                         W-6
              W.4.13    Shift Operations                                 W-6
              W.4.14    Boolean Operations                               W-6
              W.4.15    Compare                                          W-7
              W.4.16    CPU Control                                      W-7
              W.4.17    Absolute Jumps                                   W-7
              W.4.18    Relative Jumps                                   W-8
              W.4.19    Calls                                            W-8
              W.4.20    Input and output                                 W-8
              W.4.21    Unknown Commands                                 W-9

                                                                      Page 2

                                      P R E F A C E

               The  ASxxxx  assemblers  were  written following the style of
            several cross assemblers found in the Digital Equipment Corpora-
            tion  Users  Society  (DECUS)  distribution of the C programming
            language.  The DECUS code was provided with no documentation  as
            to  the  input  syntax  or the output format.  Study of the code
            revealed that the unknown author of the code  had  attempted  to
            formulate  an assembler with attributes similiar to those of the
            PDP-11 MACRO assembler (without macro's).  The  incomplete  code
            from  the  DECUS C distribution has been largely rewritten, only
            the program structure, and C source  file  organization  remains
            relatively  unchanged.   However, I wish to thank the author for
            his contribution to this set of assemblers.

               The  ASLINK  program was written as a companion to the ASxxxx
            assemblers, its design and implementation was not  derived  from
            any other work.

               I  would  greatly  appreciate  receiving  the  details of any
            changes, additions, or errors pertaining to these  programs  and
            will  attempt  to  incorporate  any  fixes  or  generally useful
            changes in a future update to these programs.

                    Alan R.  Baldwin
                    Kent State University
                    Physics Department
                    Kent, Ohio 44242
                    U.S.A.

                    http://shop-pdp.kent.edu/ashtml/asxxxx.htm

                    baldwin@kent.edu
                    baldwin@shop-pdp.kent.edu
                    tel:  (330) 672 2531
                    fax:  (330) 672 2959

                                                                      Page 3

                   E N D   U S E R   L I C E N S E   A G R E E M E N T

               This software is FREEWARE which means it is NOT public domain
            but  fully  copyrighted  material  that  is  distributed  freely
            without  money.   Its  electronic distribution through BBSs, the
            Internet, or other such means is encouraged provided no money is
            requested in return.

               It is forbidden to distribute this software should this file,
            or any of the remaining files, change in any way or  be  omitted
            from the archive.

               If you would like to include this software together with your
            own work you MUST include it only as the original  complete  un-
            modified archive in which I distribute it and not as independent
            files.   If  uncertain,  simply  point  others   or   link   to:
            http://shop-pdp.kent.edu/asxhtm/asxxxx.htm

               Please note that although I have done my best to ensure there
            is no potentially dangerous code  (or  accidental  virus  infec-
            tions),  the  nature of programming is such that it forces me to
            provide absolutely no warranty, express or  implied,  with  this
            version  of the software, and I bear no responsibility for what-
            ever damages, direct or consequential, you may suffer  from  its
            use.   I definitely do not warrant this software for suitability
            for any particular purpose, either.  It is  also  possible  that
            the instructions, the extra utilities, or the examples that come
            with the software contain errors,  none  of  which  were  inten-
            tional.

                                                                      Page 4

                                 C O N T R I B U T O R S

            Thanks  to Marko Makela for his contribution of the AS6500 cross
            assembler.

                    Marko Makela
                    Sillitie 10 A
                    01480 Vantaa
                    Finland
                    Internet: Marko dot Makela at Helsinki dot Fi
                    EARN/BitNet: msmakela at finuh

            Thanks  to John Hartman for his contribution of the AS8051 cross
            assembler and updates to the ASxxxx and ASLINK internals.

                    John L. Hartman
                    jhartman at compuserve dot com
                    noice @ noicedebugger dot com

            Thanks  to  G.   Osborn  for  his  contributions  to LKS19.C and
            LKIHX.C.

                    G. Osborn
                    gary at s-4 dot com

            Thanks to Ken Hornstein for his contribution of object libraries
            contained in LKLIBR.C.

                    Ken Hornstein
                    kenh at cmf dot nrl dot navy dot mil

                                                                      Page 5

            Thanks  to  Bill  McKinnon for his contributions to the AS8XCXXX
            cross assembler for the DS8XCXXX series of microprocessors.

                    Bill McKinnon
                    w_mckinnon at conknet dot com

            Thanks  to Roger Ivie for his contribution of the ASGB cross as-
            sembler for the GameBoy.

                    Roger Ivie
                    ivie at cc dot usu dot edu

            Thanks  to  Uwe  Steller for his contribution of the AS740 cross
            assembler.

                    Uwe Stellar
                    Uwe dot Steller at t-online dot de

            Thanks  to  Shujen Chen for his contribution of the AS1802 cross
            assembler.

                    Shugen Chen
                    DeVry University
                    Tinley Park IL
                    schen at tp dot devry dot edu

            Thanks  to  Edgar Puehringer for his contribution of the AS61860
            cross assembler.

                    Edgar Puehringer
                    edgar_pue at yahoo dot com

                                                                      Page 6

            Thanks to Ulrich Raich and Razaq Ijoduola for their contribution
            of the ASRAB cross assembler.

                    Ulrich Raich and Razaq Ijoduola
                    PS Division
                    CERN
                    CH-1211 Geneva-23
                    Ulrich dot Raich at cern dot ch

                                                                      Page 7

            ASxxxx Cross Assemblers, Version 4.00, November 2003

            Submitted by Alan R.  Baldwin,
            Kent State University, Kent, Ohio

            Operating System:  MS-DOS, Windows, Linux
            or other supporting ANSII C.

            Source Langauge:  C

            Abstract:

               The  ASxxxx  assemblers are a series of microprocessor assem-
            blers written in the C programming  language.   This  collection
            contains  cross  assemblers  for the AVR, PIC, Rabbit 2000/3000,
            DS8xCxxx,   z80(hd64180),    GameBoy(Z80),    MPS430,    H8/3xx,
            6800(6802/6808), 6801(hd6303), 6804, 6805, 68HC08, 6809, 68HC11,
            68HC12, 68HC16, 8051, 8085(8080), 6500,  1802,  740,  and  61860
            series  microprocessors.   Each  assembler has a device specific
            section which includes:  (1) device description, byte order, and
            file  extension  information,  (2)  a table of assembler general
            directives, special directives, assembler  mnemonics  and  asso-
            ciated operation codes, (3) machine specific code for processing
            the device mnemonics, addressing modes, and special directives.

               The assemblers have a common device independent section which
            handles the details of file input/output, symbol  table  genera-
            tion,  program/data  areas,  expression  analysis, and assembler
            directive processing.

               The  assemblers  provide  the following features:  (1) alpha-
            betized, formatted symbol table listings, (2) relocatable object
            modules, (3) global symbols for linking object modules, (4) con-
            ditional assembly directives, (5) reusable  local  symbols,  and
            (6) include-file processing.

               The  companion program ASLINK is a relocating linker perform-
            ing the following functions:  (1) bind multiple  object  modules
            into  a  single  memory  image,  (2) resolve inter-module symbol
            references,  (3)  resolve  undefined  symbols   from   specified
            librarys of object modules, (4) process absolute, relative, con-
            catenated, and overlay attributes in data and program  sections,
            (5)  perform  byte and word program-counter relative (pc or pcr)
            addressing calculations, (6) define absolute  symbol  values  at
            link  time, (7) define absolute area base address values at link
            time, (8) produce Intel Hex or Motorola S  record  output  file,
            (9)  produce  a  map of the linked memory image, and (10) update
            the ASxxxx assembler listing files with the absolute linked  ad-
            dresses and data.

               The  assemblers  and  linker  have  been  tested using Linux,
            DJGPP,  Cygwin,  Symantec  C/C++   V6.1/V7.2,   and   VC6   with
            MS-DOS/Windows  3.x/9x/NT/2000/XP.  Complete source code and do-
            cumentation for the assemblers and linker is included  with  the
            distribution.   Additionally,  test  code for each assembler and
            several microprocessor monitors ( ASSIST05 for the 6805,  MONDEB
            and  ASSIST09  for  the  6809, and BUFFALO 2.5 for the 6811) are
            included as working examples of use of these assemblers.

                                        CHAPTER 1

                                      THE ASSEMBLER

            1.1  THE ASXXXX ASSEMBLERS

               The  ASxxxx  assemblers are a series of microprocessor assem-
            blers written in the C programming language.  Each assembler has
            a device specific section which includes:

                 1.  device  description, byte order, and file extension in-
                     formation

                 2.  a  table  of  the assembler general directives, special
                     device directives, assembler mnemonics  and  associated
                     operation codes

                 3.  machine specific code for processing the device mnemon-
                     ics, addressing modes, and special directives

            The device specific information is detailed in the appendices.

               The assemblers have a common device independent section which
            handles the details of file input/output, symbol  table  genera-
            tion,  program/data  areas,  expression  analysis, and assembler
            directive processing.

            The assemblers provide the following features:

                 1.  Command string control of assembly functions

                 2.  Alphabetized, formatted symbol table listing

                 3.  Relocatable object modules

                 4.  Global symbols for linking object modules

                 5.  Conditional assembly directives

            THE ASSEMBLER                                           PAGE 1-2
            THE ASXXXX ASSEMBLERS

                 6.  Program sectioning directives

               ASxxxx assembles one or more source files into a single relo-
            catable ascii object file.  The output of the ASxxxx  assemblers
            consists of an ascii relocatable object file(*.rel), an assembly
            listing file(*.lst), and a symbol file(*.sym).

            1.1.1  Assembly Pass 1

               During  pass  1, ASxxxx opens all source files and performs a
            rudimenatry assembly of each source statement.  During this pro-
            cess  all symbol tables are built, program sections defined, and
            number of bytes for each assembled source line is estimated.

               At the end of pass 1 all undefined symbols may be made global
            (external) using the ASxxxx switch -g, otherwise undefined  sym-
            bols will be flagged as errors during succeeding passes.

            1.1.2  Assembly Pass 2

               During  pass  2  the ASxxxx assembler resolves forward refer-
            ences and determines the number  of  bytes  for  each  assembled
            line.   The  number  of bytes used by a particular assembler in-
            struction may depend upon the addressing mode, whether  the  in-
            struction allows multiple forms based upon the relative distance
            to the addressed location, or other factors.   Pass  2  resolves
            these cases and determines the address of all symbols.

            1.1.3  Assembly Pass 3

               Pass 3 by the assembler generates the listing file, the relo-
            catable output file, and the symbol tables.  Also during pass  3
            the errors will be reported.

               The  relocatable object file is an ascii file containing sym-
            bol references and definitions, program  area  definitions,  and
            the  relocatable assembled code, the linker ASLINK will use this
            information to generate an absolute load file (Motorola or Intel
            formats).

            THE ASSEMBLER                                           PAGE 1-3
            SOURCE PROGRAM FORMAT

            1.2  SOURCE PROGRAM FORMAT

            1.2.1  Statement Format

               A source program is composed of assembly-language statements.
            Each statement must be completed on one line.  A line  may  con-
            tain a maximum of 128 characters, longer lines are truncated and
            lost.

               An  ASxxxx  assembler  statement  may  have  as  many as four
            fields.  These fields are identified by their order  within  the
            statement  and/or  by separating characters between fields.  The
            general format of the ASxxxx statement is:

                  [label:]  Operator        Operand         [;Comment(s)]

               The  label and comment fields are optional.  The operator and
            operand fields are interdependent.  The operator field may be an
            assembler  directive or an assembly mnemonic.  The operand field
            may be optional or required as defined in  the  context  of  the
            operator.

               ASxxxx  interprets  and  processes source statements one at a
            time.  Each statement causes a particular operation to  be  per-
            formed.

            1.2.1.1  Label Field  -

               A  label is a user-defined symbol which is assigned the value
            of the current location counter and entered into  the  user  de-
            fined  symbol  table.   The  current location counter is used by
            ASxxxx to assign memory addresses to the source  program  state-
            ments as they are encountered during the assembly process.  Thus
            a label is a means  of  symbolically  referring  to  a  specific
            statement.

               When  a program section is absolute, the value of the current
            location counter is absolute;  its value references an  absolute
            memory  address.   Similarly, when a program section is relocat-
            able, the value of the current location counter is  relocatable.
            A  relocation  bias  calculated at link time is added to the ap-
            parent value of the current location counter  to  establish  its
            effective  absolute  address  at  execution time.  (The user can
            also force the linker to relocate sections defined as  absolute.
            This may be required under special circumstances.)

               If  present,  a  label  must  be  the first field in a source
            statement and must be terminated by a colon (:).   For  example,

            THE ASSEMBLER                                           PAGE 1-4
            SOURCE PROGRAM FORMAT

            if  the  value  of  the  current  location  counter  is absolute
            01F0(H), the statement:

                  abcd:     nop

            assigns  the  value  01F0(H) to the label abcd.  If the location
            counter value were relocatable, the final value of abcd would be
            01F0(H)+K, where K represents the relocation bias of the program
            section, as calculated by the linker at link time.

               More  than  one label may appear within a single label field.
            Each label so specified is assigned the same address value.  For
            example,  if  the  value  of  the  current  location  counter is
            1FF0(H), the multiple labels in the following statement are each
            assigned the value 1FF0(H):

                  abcd:     aq:     $abc:   nop

               Multiple labels may also appear on successive lines.  For ex-
            ample, the statements

                  abcd:
                  aq:
                  $abc:     nop

            likewise  cause  the  same value to be assigned to all three la-
            bels.

               A  double  colon  (::)  defines the label as a global symbol.
            For example, the statement

                  abcd::    nop

            establishes the label abcd as a global symbol.  The distinguish-
            ing attribute of a global symbol is that it  can  be  referenced
            from  within an object module other than the module in which the
            symbol is defined.  References to this label  in  other  modules
            are  resolved when the modules are linked as a composite execut-
            able image.

            The legal characters for defining labels are:

                    A through Z
                    a through z
                    0 through 9
                    . (Period)
                    $ (Dollar sign)
                    _ (underscore)

               A  label  may  be  any  length,  however  only  the  first 79
            characters are significant and, therefore must be  unique  among
            all   labels  in  the  source  program  (not  necessarily  among

            THE ASSEMBLER                                           PAGE 1-5
            SOURCE PROGRAM FORMAT

            separately compiled modules).  An error code(s) (m or p) will be
            generated  in the assembly listing if the first 79 characters in
            two or more labels are the same.  The m code is  caused  by  the
            redeclaration  of  the symbol or its reference by another state-
            ment.  The p code is generated because the symbols  location  is
            changing on each pass through the source file.

               The  label  must  not  start with the characters 0-9, as this
            designates a reusable symbol with special  attributes  described
            in a later section.

               The  label  must  not  start  with  the  sequence $$, as this
            represents the temporary radix 16 for constants.

            1.2.1.2  Operator Field  -

               The  operator field specifies the action to be performed.  It
            may consist of an instruction mnemonic (op code) or an assembler
            directive.

               When  the  operator is an instruction mnemonic, a machine in-
            struction is generated and the assembler evaluates the addresses
            of  the operands which follow.  When the operator is a directive
            ASxxxx performs certain control actions or processing operations
            during assembly of the source program.

               Leading  and  trailing  spaces  or tabs in the operator field
            have no significance;  such characters serve  only  to  separate
            the operator field from the preceeding and following fields.

               An operator is terminated by a space, tab or end of line.

            1.2.1.3  Operand Field  -

               When  the  operator is an instruction mnemonic (op code), the
            operand  field  contains  program  variables  that  are  to   be
            evaluated/manipulated by the operator.

               Operands  may  be  expressions  or  symbols, depending on the
            operator.  Multiple expressions used in the operand  fields  may
            be  separated  by a comma.  An operand should be preceeded by an
            operator field;  if it is not, the statement will give an  error
            (q  or  o).   All  operands  following instruction mnemonics are
            treated as expressions.

               The operand field is terminated by a semicolon when the field
            is followed  by  a  comment.   For  example,  in  the  following
            statement:

                  label:    lda     abcd,x          ;Comment field

            THE ASSEMBLER                                           PAGE 1-6
            SOURCE PROGRAM FORMAT

            the  tab  between lda and abcd terminates the operator field and
            defines the beginning of the operand field;  a  comma  separates
            the operands abcd and x;  and a semicolon terminates the operand
            field and defines the beginning of the comment field.   When  no
            comment  field  follows,  the operand field is terminated by the
            end of the source line.

            1.2.1.4  Comment Field  -

               The comment field begins with a semicolon and extends through
            the end of the line.  This field is optional and may contain any
            7-bit ascii character except null.

               Comments  do not affect assembly processing or program execu-
            tion.

            1.3  SYMBOLS AND EXPRESSIONS

               This  section  describes the generic components of the ASxxxx
            assemblers:  the character set, the conventions observed in con-
            structing  symbols,  and  the use of numbers, operators, and ex-
            pressions.

            1.3.1  Character Set

               The following characters are legal in ASxxxx source programs:

                 1.  The  letters  A  through Z.  Both upper- and lower-case
                     letters are acceptable.  The  assemblers,  by  default,
                     are  case  sensitive,  i.e.   ABCD and abcd are not the
                     same symbols.  (The assemblers can be made case  insen-
                     sitive by using the -z command line option.)

                 2.  The digits 0 through 9

                 3.  The  characters . (period), $ (dollar sign), and _ (un-
                     derscore).

                 4.  The special characters listed in Tables 1 through 6.

               Tables  1  through  6  describe  the various ASxxxx label and
            field terminators, assignment operators, operand separators, as-
            sembly, unary, binary, and radix operators.

            THE ASSEMBLER                                           PAGE 1-7
            SYMBOLS AND EXPRESSIONS

            Table 1         Label Terminators and Assignment Operators
            ----------------------------------------------------------------

                    :   Colon               Label terminator.

                    ::  Double colon        Label  Terminator;   defines the
                                            label as a global label.

                    =   Equal sign          Direct assignment operator.

                    ==  Global equal        Direct assignment operator;  de-
                                            fines the  symbol  as  a  global
                                            symbol.

                    =:  Local equal         Direct assignment operator;  de-
                                            fines the symbol as a local sym-
                                            bol.

            ----------------------------------------------------------------

            Table 2         Field Terminators and Operand Separators
            ----------------------------------------------------------------

                        Tab                 Item or field terminator.

                        Space               Item or field terminator.

                    ,   Comma               Operand field separator.

                    ;   Semicolon           Comment field indicator.

            ----------------------------------------------------------------

            THE ASSEMBLER                                           PAGE 1-8
            SYMBOLS AND EXPRESSIONS

            Table 3         Assembler Operators
            ----------------------------------------------------------------

                    #   Number sign         Immediate expression indicator.

                    .   Period              Current location counter.

                    (   Left parenthesis    Expression delimiter.

                    )   Right parenthesis   Expression delimeter.

            ----------------------------------------------------------------

            Table 4         Unary Operators
            ----------------------------------------------------------------

                    <   Left bracket           Right bracket       >FEDC   Produces  the upper byte
                                                    value of the expression.
                                                    (FE)

                    +   Plus sign           +A      Positive value of A

                    -   Minus sign          -A      Produces   the  negative
                                                    (2's complement) of A.

                    ~   Tilde               ~A      Produces the 1's comple-
                                                    ment of A.

                    '   Single quote        'D      Produces  the  value  of
                                                    the character D.

                    "   Double quote        "AB     Produces the double byte
                                                    value for AB.

                    \   Backslash           '\n     Unix style characters
                                                    \b, \f, \n, \r, \t
                                         or '\001   or octal byte values.

            ----------------------------------------------------------------

            THE ASSEMBLER                                           PAGE 1-9
            SYMBOLS AND EXPRESSIONS

            Table 5         Binary Operators
            ----------------------------------------------------------------

                    <<  Double          0800 << 4   Produces the 4 bit
                        Left bracket                left-shifted   value  of
                                                    0800.  (8000)

                    >>  Double          0800 >> 4   Produces the 4 bit
                        Right bracket               right-shifted  value  of
                                                    0800.  (0080)

                    +   Plus sign       A + B       Arithmetic      Addition
                                                    operator.

                    -   Minus sign      A - B       Arithmetic   Subtraction
                                                    operator.

                    *   Asterisk        A * B       Arithmetic   Multiplica-
                                                    tion operator.

                    /   Slash           A / B       Arithmetic      Division
                                                    operator.

                    &   Ampersand       A & B       Logical AND operator.

                    |   Bar             A | B       Logical OR operator.

                    %   Percent sign    A % B       Modulus operator.

                    ^   Up arrow or     A ^ B       EXCLUSIVE OR operator.
                        circumflex

            ----------------------------------------------------------------

            Table 6         Temporary Radix Operators
            ----------------------------------------------------------------

                    $%,   0b, 0B            Binary radix operator.

                    $&,   0o, 0O, 0q, 0Q    Octal radix operator.

                    $#,   0d, 0D            Decimal radix operator.

                    $$,   0h, 0H, 0x, 0X    Hexidecimal radix operator.

                    Potential  ambiguities arising from the use of 0b and 0d
                    as temporary radix  operators  may  be  circumvented  by

            THE ASSEMBLER                                          PAGE 1-10
            SYMBOLS AND EXPRESSIONS

                    preceding  all non-prefixed hexidecimal numbers with 00.
                    Leading 0's are required in any  case  where  the  first
                    hexidecimal  digit is abcdef as the assembler will treat
                    the letter sequence as a label.

            ----------------------------------------------------------------

            1.3.2  User-Defined Symbols

               User-defined  symbols are those symbols that are equated to a
            specific value through a direct assignment statement  or  appear
            as  labels.  These symbols are added to the User Symbol Table as
            they are encountered during assembly.

            The following rules govern the creation of user-defined symbols:

                 1.  Symbols  can  be  composed  of alphanumeric characters,
                     dollar signs ($),  periods  (.),  and  underscores  (_)
                     only.

                 2.  The  first  character  of a symbol must not be a number
                     (except in the case of reusable symbols).

                 3.  The  first 79 characters of a symbol must be unique.  A
                     symbol  can  be  written  with  more  than   79   legal
                     characters,  but the 80th and subsequent characters are
                     ignored.

                 4.  Spaces and Tabs must not be embedded within a symbol.

            1.3.3  Reusable Symbols

               Reusable  symbols are specially formatted symbols used as la-
            bels within a block of coding that has been delimited as a reus-
            able symbol block.  Reusable symbols are of the form n$, where n
            is a decimal integer from 0 to 65535,  inclusive.   Examples  of
            reusable symbols are:

                  1$
                  27$
                  138$
                  244$

            THE ASSEMBLER                                          PAGE 1-11
            SYMBOLS AND EXPRESSIONS

               The range of a reusable symbol block consists of those state-
            ments between two normally constructed  symbolic  labels.   Note
            that a statement of the form:

                  ALPHA = EXPRESSION

            is a direct assignment statement but does not create a label and
            thus does not delimit the range of a reusable symbol block.

               Note  that  the  range  of a reusable symbol block may extend
            across program areas.

               Reusable symbols provide a convenient means of generating la-
            bels for branch instructions and other  such  references  within
            reusable symbol blocks.  Using reusable symbols reduces the pos-
            sibility of symbols with multiple definitions appearing within a
            user  program.   In  addition,  the use of reusable symbols dif-
            ferentiates entry-point labels from other labels, since reusable
            labels cannot be referenced from outside their respective symbol
            blocks.  Thus, reusable symbols of the same name can  appear  in
            other  symbol blocks without conflict.  Reusable symbols require
            less symbol table space  than  normal  symbols.   Their  use  is
            recommended.

               The  use  of  the  same reusable symbol within a symbol block
            will generate one or both of the m or p errors.

            Example of reusable symbols:

                    a:      ldx     #atable ;get table address
                            lda     #0d48   ;table length
                    1$:     clr     ,x+     ;clear
                            deca
                            bne     1$

                    b:      ldx     #btable ;get table address
                            lda     #0d48   ;table length
                    1$:     clr     ,x+     ;clear
                            deca
                            bne     1$

            THE ASSEMBLER                                          PAGE 1-12
            SYMBOLS AND EXPRESSIONS

            1.3.4  Current Location Counter

               The  period  (.) is the symbol for the current location coun-
            ter.  When used in the operand  field  of  an  instruction,  the
            period   represents  the  address  of  the  first  byte  of  the
            instruction:

                    AS:     ldx     #.      ;The period (.) refers to
                                            ;the address of the ldx
                                            ;instruction.

               When  used  in  the  operand field of an ASxxxx directive, it
            represents the address of the current byte or word:

                    QK = 0

                    .word   0xFFFE,.+4,QK   ;The operand .+4 in the .word
                                            ;directive represents a value
                                            ;stored in the second of the
                                            ;three words during assembly.

               If  we  assume  the  current  value of the program counter is
            0H0200, then during assembly, ASxxxx  reserves  three  words  of
            storage  starting  at  location 0H0200.  The first value, a hex-
            idecimal constant FFFE, will be stored at location 0H0200.   The
            second  value  represented  by  .+4  will  be stored at location
            0H0202, its value will be 0H0206 ( = 0H0202  +  4).   The  third
            value  defined  by  the  symbol  QK  will  be placed at location
            0H0204.

               At the beginning of each assembly pass, ASxxxx resets the lo-
            cation counter.  Normally, consecutive memory locations are  as-
            signed  to  each  byte  of  object code generated.  However, the
            value of the location counter can be changed  through  a  direct
            assignment statement of the following form:

                  . = . + expression

               The  new  location  counter can only be specified relative to
            the current location counter.  Neglecting to specify the current
            program  counter  along with the expression on the right side of
            the assignment operator will generate the (.) error.   (Absolute
            program areas may use the .org directive to specify the absolute
            location of the current program counter.)

            The following coding illustrates the use of the current location
            counter:

                    .area   CODE1   (ABS)   ;program area CODE1
                                            ;is ABSOLUTE

            THE ASSEMBLER                                          PAGE 1-13
            SYMBOLS AND EXPRESSIONS

                    .org    0H100           ;set location to
                                            ;0H100 absolute

            num1:   ldx     #.+0H10         ;The label num1 has
                                            ;the value 0H100.
                                            ;X is loaded with
                                            ;0H100 + 0H10

                    .org    0H130           ;location counter
                                            ;set to 0H130

            num2:   ldy     #.              ;The label num2 has
                                            ;the value 0H130.
                                            ;Y is loaded with
                                            ;value 0H130.

                    .area   CODE2   (REL)   ;program area CODE2
                                            ;is RELOCATABLE

                    . = . + 0H20            ;Set location counter
                                            ;to relocatable 0H20 of
                                            ;the program section.

            num3:   .word   0               ;The label num3 has
                                            ;the value
                                            ;of relocatable 0H20.

                    . = . + 0H40            ;will reserve 0H40
                                            ;bytes of storage as will
                    .blkb   0H40            ;or
                    .blkw   0H20

               The  .blkb  and .blkw directives are the preferred methods of
            allocating space.

            1.3.5  Numbers

               ASxxxx  assumes that all numbers in the source program are to
            be interpreted in decimal radix unless otherwise specified.  The
            .radix  directive  may  be used to specify the default as octal,
            decimal, or hexidecimal.  Individual numbers can  be  designated
            as  binary, octal, decimal, or hexidecimal through the temporary
            radix prefixes shown in table 6.

               Negative  numbers  must be preceeded by a minus sign;  ASxxxx
            translates such numbers into two's  complement  form.   Positive
            numbers may (but need not) be preceeded by a plus sign.

            THE ASSEMBLER                                          PAGE 1-14
            SYMBOLS AND EXPRESSIONS

               Numbers are always considered to be absolute values, therefor
            they are never relocatable.

            1.3.6  Terms

               A  term is a component of an expression and may be one of the
            following:

                 1.  A number.

                 2.  A symbol:
                     1.  A  period (.) specified in an expression causes the
                         current location counter to be used.
                     2.  A User-defined symbol.
                     3.  An undefined symbol is assigned a value of zero and
                         inserted in the User-Defined symbol table as an un-
                         defined symbol.

                 3.  A single quote followed by a single ascii character, or
                     a double quote followed by two ascii characters.

                 4.  An  expression enclosed in parenthesis.  Any expression
                     so enclosed is evaluated and reduced to a  single  term
                     before  the remainder of the expression in which it ap-
                     pears is evaluated.  Parenthesis, for example,  may  be
                     used  to  alter the left-to-right evaluation of expres-
                     sions, (as in A*B+C versus A*(B+C)), or to apply a  un-
                     ary operator to an entire expression (as in -(A+B)).

                 5.  A unary operator followed by a symbol or number.

            1.3.7  Expressions

               Expressions  are  combinations  of  terms  joined together by
            binary operators.  Expressions reduce to a value.   The  evalua-
            tion  of  an expression includes the determination of its attri-
            butes.  A resultant expression value may be one of  three  types
            (as  described  later  in this section):  relocatable, absolute,
            and external.

            THE ASSEMBLER                                          PAGE 1-15
            SYMBOLS AND EXPRESSIONS

            Expressions are evaluate with an operand hierarchy as follows:

                    *       /       %       multiplication,
                                            division, and
                                            modulus first.

                    +       -               addition and
                                            subtraction second.

                    <<      >>              left shift and
                                            right shift third.

                    ^                       exclusive or fourth.

                    &                       logical and fifth.

                    |                       logical or last

                    except that unary operators take precedence over binary
                    operators.

               A  missing  or  illegal  operator  terminates  the expression
            analysis, causing error codes (o) and/or  (q)  to  be  generated
            depending upon the context of the expression itself.

               At assembly time the value of an external (global) expression
            is equal to the value of the absolute part of  that  expression.
            For  example,  the expression external+4, where 'external' is an
            external symbol, has the value of 4.  This expression,  however,
            when  evaluated  at link time takes on the resolved value of the
            symbol 'external', plus 4.

               Expressions,  when  evaluated  by  ASxxxx,  are  one of three
            types:  relocatable, absolute, or external.  The following  dis-
            tinctions are important:

                 1.  An  expression is relocatable if its value is fixed re-
                     lative to the base address of the program area in which
                     it appears;  it will have an offset value added at link
                     time.  Terms that contain labels defined in relocatable
                     program  areas  will  have  a relocatable value;  simi-
                     larly, a period (.)  in  a  relocatable  program  area,
                     representing  the value of the current program location
                     counter, will also have a relocatable value.

                 2.  An  expression  is  absolute if its value is fixed.  An
                     expression whose terms are numbers and ascii characters
                     will  reduce  to  an absolute value.  A relocatable ex-
                     pression or term minus a relocatable term,  where  both
                     elements  being  evaluated  belong  to the same program
                     area, is an absolute expression.  This is because every

            THE ASSEMBLER                                          PAGE 1-16
            SYMBOLS AND EXPRESSIONS

                     term  in  a  program area has the same relocation bias.
                     When one term is subtracted from the other the  reloca-
                     tion bias is zero.

                 3.  An  expression is external (or global) if it contains a
                     single global reference (plus or minus an absolute  ex-
                     pression  value) that is not defined within the current
                     program.  Thus, an external  expression  is  only  par-
                     tially  defined following assembly and must be resolved
                     at link time.

            1.4  GENERAL ASSEMBLER DIRECTIVES

               An  ASxxxx  directive  is placed in the operator field of the
            source line.  Only one directive is  allowed  per  source  line.
            Each  directive  may  have  a blank operand field or one or more
            operands.  Legal operands differ with each directive.

            1.4.1  .module Directive

            Format:

                    .module string

               The .module directive causes the string to be included in the
            assemblers output file as an identifier for this particular  ob-
            ject  module.   The  string  may  be  from 1 to 79 characters in
            length.  Only one identifier is allowed  per  assembled  module.
            The  main use of this directive is to allow the linker to report
            a modules' use of undefined symbols.  At link time all undefined
            symbols  are  reported  and  the  modules  referencing  them are
            listed.

            1.4.2  .title Directive

            Format:

                    .title  string

               The .title directive provides a character string to be placed
            on the second line of each page during listing.

            THE ASSEMBLER                                          PAGE 1-17
            GENERAL ASSEMBLER DIRECTIVES

            1.4.3  .sbttl Directive

            Format:

                    .sbttl  string

               The .sbttl directive provides a character string to be placed
            on the third line of each page during listing.

            1.4.4  .page Directive

            Format:

                    .page

               The .page directive causes a page ejection with a new heading
            to be printed.  The new page occurs after the next line  of  the
            source  program is processed, this allows an immediately follow-
            ing .sbttl directive to appear  on  the  new  page.   The  .page
            source  line will not appear in the file listing.  Paging may be
            disabled by invoking the -p directive.

            1.4.5  .msg Directive

            Format:

                    .msg text

            where:  text    represents  a  delimited  string.  The string is
                            printed to the console during the final assembly
                            pass.

               The  .msg  directive  is  useful to report assembly status or
            other information during the assembly process.

            1.4.6  .error Directive

            Format:

                    .error exp

            where:  exp     represents   an  absolute  expression.   If  the
                            evaluation of the expression results  in  a  non
                            zero value then an 'e' error is reported and the
                            text line is listed in the generated error.

            THE ASSEMBLER                                          PAGE 1-18
            GENERAL ASSEMBLER DIRECTIVES

               The  .error  directive  is  useful to report configuration or
            value errors during the assembly process.  (The .error directive
            is  identical in function to the .assume directive, just perhaps
            more descriptive.)

            1.4.7  .byte, .db, and .fcb Directives

            Format:

                    .byte   exp             ;Stores the binary value
                    .db     exp             ;of the expression in the
                    .fcb    exp             ;next byte.

                    .byte   exp1,exp2,expn  ;Stores the binary values
                    .db     exp1,exp2,expn  ;of the list of expressions
                    .fcb    exp1,exp2,expn  ;in successive bytes.

            where:  exp,    represent expressions that will be
                    exp1,   truncated to 8-bits of data.
                    .       Each expression will be calculated,
                    .       the high-order byte will be truncated.
                    .       Multiple expressions must be
                    expn    separated by commas.

               The  .byte, .db, or .fcb directives are used to generate suc-
            cessive bytes of binary data in the object module.

            1.4.8  .word, .dw, and .fdb Directives

            Format:

                    .word   exp             ;Stores the binary value
                    .dw     exp             ;of the expression in
                    .fdb    exp             ;the next word.

                    .word   exp1,exp2,expn  ;Stores the binary values
                    .dw     exp1,exp2,expn  ;of the list of expressions
                    .fdb    exp1,exp2,expn  ;in successive words.

            where:  exp,    represent expressions that will occupy two
                    exp1,   bytes of data. Each expression will be
                    .       calculated as a 16-bit word expression.
                    .       Multiple expressions must be
                    expn    separated by commas.

               The  .word, .dw, or .fdb directives are used to generate suc-
            cessive words of binary data in the object module.

            THE ASSEMBLER                                          PAGE 1-19
            GENERAL ASSEMBLER DIRECTIVES

            1.4.9  .3byte and .triple Directives

            Format:

                    .3byte  exp             ;Stores the binary value
                    .triple exp             ;of the expression in
                                            ;the next triple (3 bytes).

                    .3byte  exp1,exp2,expn  ;Stores the binary values
                    .triple exp1,exp2,expn  ;of the list of expressions
                                            ;in successive triples
                                            ;(3 bytes).

            where:  exp,    represent expressions that will occupy three
                    exp1,   bytes of data. Each expression will be
                    .       calculated as a 24-bit word expression.
                    .       Multiple expressions must be
                    expn    separated by commas.

               The  .3byte  or .triple directive is used to generate succes-
            sive triples of binary data in the object module.  (These direc-
            tives   are  only  available  in  assemblers  supporting  24-bit
            addressing.)

            1.4.10  .4byte and .quad Directive

            Format:

                    .4byte  exp             ;Stores the binary value
                    .quad   exp             ;of the expression in
                                            ;the next quad (4 bytes).

                    .4byte  exp1,exp2,expn  ;Stores the binary values
                    .quad   exp1,exp2,expn  ;of the list of expressions
                                            ;in successive quads
                                            ;(4 bytes).

            where:  exp,    represent expressions that will occupy three
                    exp1,   bytes of data. Each expression will be
                    .       calculated as a 32-bit word expression.
                    .       Multiple expressions must be
                    expn    separated by commas.

               The  .4byte or .quad directive is used to generate successive
            quads of binary data in the object  module.   (These  directives
            are only available in assemblers supporting 32-bit addressing.)

            THE ASSEMBLER                                          PAGE 1-20
            GENERAL ASSEMBLER DIRECTIVES

            1.4.11  .blkb, .ds, ,rmb, and .rs Directives

            Format:

                    .blkb   N       ;reserve N bytes of space
                    .ds     N       ;reserve N bytes of space
                    .rmb    N       ;reserve N bytes of space
                    .rs     N       ;reserve N bytes of space

               The  .blkb, .ds, .rmb, and .rs directives reserve byte blocks
            in the object module;

            1.4.12  .blkw, .blk3, and .blk4 Directives

            Format:

                    .blkw   N       ;reserve N words of space
                    .blk3   N       ;reserve N triples of space
                    .blk4   N       ;reserve N quads of space

               The .blkw directive reserves word blocks;  the .blk3 reserves
            3  byte  blocks(available  in   assemblers   supporting   24-bit
            addressing);  the .blk4 reserves 4 byte blocks (available in as-
            semblers supporting 32-bit addressing).

            1.4.13  .ascii, .str, and .fcc Directives

            Format:

                    .ascii  /string/

                    .fcc    /string/

                    .str    /string/

            where:  string  is a string of printable ascii characters.

                    /  /    represent   the  delimiting  characters.   These
                            delimiters   may   be   any   paired    printing
                            characters,  as  long  as the characters are not
                            contained within  the  string  itself.   If  the
                            delimiting  characters  do not match, the .ascii
                            directive will give the (q) error.

            The  .ascii,  .fcc, and .str directives place one binary byte of
            data for each character in the string into the object module.

            THE ASSEMBLER                                          PAGE 1-21
            GENERAL ASSEMBLER DIRECTIVES

            1.4.14  .ascis and .strs Directives

            Format:

                    .ascis  /string/

                    .strs   /string/

            where:  string  is a string of printable ascii characters.

                    /  /    represent   the  delimiting  characters.   These
                            delimiters   may   be   any   paired    printing
                            characters,  as  long  as the characters are not
                            contained within  the  string  itself.   If  the
                            delimiting  characters  do not match, the .ascis
                            and .strs directives will give the (q) error.

               The .ascis and .strs directives place one binary byte of data
            for each character in the string into the  object  module.   The
            last character in the string will have the high order bit set.

            1.4.15  .asciz and .strz Directives

            Format:

                    .asciz  /string/

                    .strz   /string/

            where:  string  is a string of printable ascii characters.

                    /  /    represent   the  delimiting  characters.   These
                            delimiters   may   be   any   paired    printing
                            characters,  as  long  as the characters are not
                            contained within  the  string  itself.   If  the
                            delimiting  characters  do not match, the .asciz
                            and .strz directive will give the (q) error.

               The .asciz and .strz directives place one binary byte of data
            for each character in the string into the object  module.   Fol-
            lowing  all  the  character data a zero byte is inserted to ter-
            minate the character string.

            THE ASSEMBLER                                          PAGE 1-22
            GENERAL ASSEMBLER DIRECTIVES

            1.4.16  .assume Directive

            Format:

                    .assume exp

            where:  exp     represents   an  absolute  expression.   If  the
                            evaluation of the expression results  in  a  non
                            zero value then an 'e' error is reported and the
                            text line is listed in the generated error.

               The  .assume  directive  is useful to check assumptions about
            assembler values.  (The .assume directive is identical in  func-
            tion to the .error directive, just perhaps more descriptive.)

            1.4.17  .radix Directive

            Format:

                    .radix  character

            where:  character  represents  a single character specifying the
                    default radix to be used for  succeeding  numbers.   The
                    character may be any one of the following:

                            B,b     Binary

                            O,o     Octal
                            Q,q

                            D,d     Decimal
                            'blank'

                            H,h     Hexidecimal
                            X,x

            1.4.18  .even Directive

            Format:

                    .even

               The .even directive ensures that the current location counter
            contains an even boundary value by adding 1 if the current loca-
            tion is odd.

            THE ASSEMBLER                                          PAGE 1-23
            GENERAL ASSEMBLER DIRECTIVES

            1.4.19  .odd Directive

            Format:

                    .odd

               The  .odd directive ensures that the current location counter
            contains an odd boundary value by adding one if the current  lo-
            cation is even.

            1.4.20  .area Directive

            Format:

                    .area   name    [(options)]

            where:  name    represents the symbolic name of the program sec-
                            tion.   This  name  may  be  the  same  as   any
                            user-defined  symbol  or  bank as the area names
                            are independent  of  all  symbols,  labels,  and
                            banks.

                    options specify the type of program or data area:
                            ABS     absolute (automatically invokes OVR)
                            REL     relocatable
                            OVR     overlay
                            CON     concatenate
                            NOPAG   non-paged area
                            PAG     paged area

                    options specify a code or data segment:
                            CSEG    Code segment
                            DSEG    Data segment

                    option  specifies the data area bank:
                            BANK    Named collection of areas

               The .area directive provides a means of defining and separat-
            ing multiple programming and data sections.   The  name  is  the
            area  label used by the assembler and the linker to collect code
            from various separately assembled modules into one section.  The
            name may be from 1 to 79 characters in length.

               The options are specified within parenthesis and separated by
            commas as shown in the following example:

                    .area  TEST  (REL,CON)  ;This section is relocatable
                                            ;and concatenated with other
                                            ;sections of this program area.

            THE ASSEMBLER                                          PAGE 1-24
            GENERAL ASSEMBLER DIRECTIVES

                    .area  DATA  (REL,OVR)  ;This section is relocatable
                                            ;and overlays other sections
                                            ;of this program area.

                    .area  SYS   (ABS,OVR)  ;(CON not allowed with ABS)
                                            ;This section is defined as
                                            ;absolute. Absolute sections
                                            ;are always overlayed with
                                            ;other sections of this program
                                            ;area.

                    .area  PAGE  (PAG)      ;This is a paged section. The
                                            ;section must be on a 256 byte
                                            ;boundary and its length is
                                            ;checked by the linker to be
                                            ;no larger than 256 bytes.
                                            ;This is useful for direct page
                                            ;areas.

               The  default  area type is REL|CON;  i.e.  a relocatable sec-
            tion which is concatenated with other sections of code with  the
            same area name.  The ABS option indicates an absolute area.  The
            OVR and CON options indicate if program  sections  of  the  same
            name  will overlay each other (start at the same location) or be
            concatenated with each other (appended to each other).

               The  area can be specified as either a code segment, CSEG, or
            a data segment, DSEG.  The CSEG and DSEG descriptors are  useful
            when  the  microprocessor  code  and  data  unit allocations are
            unequal:  e.g.  the executable code  uses  an  allocation  of  2
            bytes for each instruction and is addressed at an increment of 1
            for every instruction, and the data uses an allocation of 1 byte
            for  each element and is addressed at an increment of 1 for each
            data byte.  The allocation units are defined by the architecture
            of the particular microprocessor.

               The  .area  directive also provides a means of specifying the
            bank this area is associated with.  All areas associated with  a
            particular  bank  are  combined  at  link  time  into a block of
            code/data.

               The  CSEG,  DSEG,  and  BANK options are specified within the
            parenthesis as shown in the following examples:

                    .area   C_SEG   (CSEG,BANK=C1)
                                            ;This is a code section
                                            ;and is included in bank C1
                    .area   D_SEG   (DSEG,BANK=D1)
                                            ;This is a data section
                                            ;and is included in bank D1.

            THE ASSEMBLER                                          PAGE 1-25
            GENERAL ASSEMBLER DIRECTIVES

               Multiple  invocations  of  the  .area directive with the same
            name must specify the same options or leave  the  options  field
            blank,  this  defaults  to  the previously specified options for
            this program area.

            The   ASxxxx   assemblers   automatically  provide  two  program
            sections:

                    '_CODE'         This  is  the  default  code/data  area.
                                    This   program   area   is    of    type
                                    (REL,CON,CSEG).

                    '_DATA'         This  is the default optional data area.
                                    This   program   area   is    of    type
                                    (REL,CON,DSEG).

            The  ASxxxx  assemblers  also automatically generate two symbols
            for each program area:

                    's_'      This is the starting address of the pro-
                                    gram area.

                    'l_'      This is the length of the program area.

            The .area names and options are never case sensitive.

            1.4.21  .bank Directive

            Format:

                    .bank   name    [(options)]

            where:  name    represents  the  symbolic  name of the bank sec-
                            tion.   This  name  may  be  the  same  as   any
                            user-defined  symbol  or  area as the bank names
                            are independent  of  all  symbols,  labels,  and
                            areas.   The name may be from 1 to 79 characters
                            in length.

                    options specify the parameters of the bank:
                            BASE    base address of bank
                            SIZE    maximum size of bank
                            FSFX    file suffix for this bank
                            MAP     NOICE mapping

               The  .bank  directive allows an arbitrary grouping of program
            and/or data areas to be communicated to the  linker.   The  bank
            parameters are all optional and are described as follows:

            THE ASSEMBLER                                          PAGE 1-26
            GENERAL ASSEMBLER DIRECTIVES

                 1.  BASE, the  starting  address of the bank (default is 0)
                     may be defined.  This address can be overridden by  us-
                     ing  the linker -b option for the first area within the
                     bank.  The bank address is always specified  in  'byte'
                     addressing.  A first area which is not 'byte' addressed
                     (e.g.  a processor addressed by a 'word' of 2  or  more
                     bytes)  has  the  area  address  scaled to begin at the
                     'byte' address.

                 2.  SIZE, the  maximum  length  of  the  bank  specified in
                     bytes.  The size is always specified in terms of bytes.

                 3.  FSFX, the file suffix to be used by the linker for this
                     bank.  The suffix may not contain embedded white space.

                 4.  MAP,  NOICE   mapping   parameter   for  this  bank  of
                     code/data.

               The options are specified within parenthesis and separated by
            commas as shown in the following example:

                    .BANK  C1  (BASE=0x0100,SIZE=0x1000,FSFX=_C1)
                                            ;This bank starts at 0x0100,
                                            ;has a maximum size of 0x1000,
                                            ;and is to be placed into
                                            ;a file with a suffix of _C1

               The parameters must be absolute (external symbols are not al-
            lowed.)

            1.4.22  .org Directive

            Format:

                    .org    exp

            where:  exp     is  an absolute expression that becomes the cur-
                            rent location counter.

            The  .org directive is valid only in an absolute program section
            and will give a (q) error if used in a relocatable program area.
            The  .org  directive specifies that the current location counter
            is to become the specified absolute value.

            THE ASSEMBLER                                          PAGE 1-27
            GENERAL ASSEMBLER DIRECTIVES

            1.4.23  .globl Directive

            Format:

                    .globl  sym1,sym2,...,symn

            where:  sym1,           represent legal symbolic names.
                    sym2,...        When multiple symbols are specified,
                    symn            they are separated by commas.

               A  .globl directive may also have a label field and/or a com-
            ment field.

               The  .globl directive is provided to define (and thus provide
            linkage to) symbols not  otherwise  defined  as  global  symbols
            within  a  module.   In  defining  global  symbols the directive
            .globl J is similar to:

                  J == expression or J::

               Because  object  modules  are linked by global symbols, these
            symbols are vital to a program.  All internal symbols  appearing
            within  a  given program must be defined at the end of pass 1 or
            they will be considered undefined.  The assembly directive  (-g)
            can  be  be  invoked to make all undefined symbols global at the
            end of pass 1.

            1.4.24  .local Directive

            Format:

                    .local  sym1,sym2,...,symn

            where:  sym1,           represent legal symbolic names.
                    sym2,...        When multiple symbols are specified,
                    symn            they are separated by commas.

               A  .local directive may also have a label field and/or a com-
            ment field.

               The  .local  directive is provided to define symbols that are
            local to the current assembly process.  Local  symbols  are  not
            effected  by  the assembler option -a (make all symbols global).
            In defining local symbols the directive .local J is similar to:

                  J =: expression

               The  .local directive and the =:  construct are useful in de-
            fining symbols and constants within a header or definition  file
            that  contains  many  symbols  specific  to the current assembly
            process that should not be exported into the .rel  output  file.

            THE ASSEMBLER                                          PAGE 1-28
            GENERAL ASSEMBLER DIRECTIVES

            A  typical  usage is in the definition of SFRs (Special Function
            Registers) for a microprocessor.

               The  .local  directive and =:  construct can be overridden by
            the .globl directive.

            1.4.25  .equ, .gblequ, and .lclequ Directives

            Format:

                    sym1    .equ    expr    ; equivalent to sym1  = expr
                    sym2    .gblequ expr    ; equivalent to sym2 == expr
                    sym3    .lclequ expr    ; equivalent to sym3 =: expr

               These  alternate  forms  of equivalence are provided for user
            convenience.

            1.4.26  .if, .else, and .endif Directives

            Format:

                    .if     expr
                    .                       ;}
                    .                       ;} range of true condition
                    .                       ;}
                    .else
                    .                       ;}
                    .                       ;} range of false condition
                    .                       ;}
                    .endif

               The  conditional  assembly directives allow you to include or
            exclude blocks of source code during the assembly process, based
            on the evaluation of the condition test.

               The  range of true condition will be processed if the expres-
            sion 'expr' is not zero (i.e.  true) and the range of false con-
            dition  will  be processed if the expression 'expr' is zero (i.e
            false).  The range of true condition is optional as is the .else
            directive  and  the range of false condition.  The following are
            all valid .if/.else/.endif constructions:

                    .if     A-4             ;evaluate A-4
                    .byte   1,2             ;insert bytes if A-4 is
                    .endif                  ;not zero

                    .if     K+3             ;evaluate K+3
                    .else
                    .byte   3,4             ;insert bytes if K+3
                    .endif                  ;is zero

            THE ASSEMBLER                                          PAGE 1-29
            GENERAL ASSEMBLER DIRECTIVES

                    .if     J&3             ;evaluate J masked by 3
                    .byte   12              ;insert this byte if J&3
                    .else                   ;is not zero
                    .byte   13              ;insert this byte if J&3
                    .endif                  ;is zero

            The .if/.else/.endif directives may be nested upto 10 levels.

               The  .page  directive  is  processed within a false condition
            range to allow extended textual information to  be  incorporated
            in  the  source  program  with  out  the need to use the comment
            delimiter (;):

                    .if     0

                    .page
                    This text will be bypassed during assembly
                    but appear in the listing file.
                    .
                    .
                    .

                    .endif

            1.4.27  .ifdef, .else, and .endif Directives

            Format:

                    .ifdef  sym
                    .                       ;}
                    .                       ;} range of true condition
                    .                       ;}
                    .else
                    .                       ;}
                    .                       ;} range of false condition
                    .                       ;}
                    .endif

               The  conditional  assembly directives allow you to include or
            exclude blocks of source code during the assembly process, based
            on the evaluation of the condition test.

               The  range  of true condition will be processed if the symbol
            'sym' is defined (i.e.  true) and the range of  false  condition
            will  be  processed  if  the  symbol  'sym'  is not defined (i.e
            false).  The range of true condition is optional as is the .else
            directive  and  the range of false condition.  The following are
            all valid .ifdef/.else/.endif constructions:

            THE ASSEMBLER                                          PAGE 1-30
            GENERAL ASSEMBLER DIRECTIVES

                    .ifdef  sym$1           ;lookup symbol sym$1
                    .byte   1,2             ;insert bytes if sym$1 is
                    .endif                  ;defined

                    .ifdef  sym$2           ;lookup symbol sym$2
                    .else
                    .byte   3,4             ;insert bytes if sym$1
                    .endif                  ;is not defined

                    .ifdef  sym$3           ;lookup symbol sym$3
                    .byte   12              ;insert this byte if sym$3
                    .else                   ;is defined
                    .byte   13              ;insert this byte if sym$3
                    .endif                  ;is not defined

            The .ifdef/.else/.endif directives may be nested upto 10 levels.

            1.4.28  .ifndef, .else, and .endif Directives

            Format:

                    .ifndef sym
                    .                       ;}
                    .                       ;} range of true condition
                    .                       ;}
                    .else
                    .                       ;}
                    .                       ;} range of false condition
                    .                       ;}
                    .endif

               The  conditional  assembly directives allow you to include or
            exclude blocks of source code during the assembly process, based
            on the evaluation of the condition test.

               The  range  of true condition will be processed if the symbol
            'sym' is not defined (i.e.  true) and the range of false  condi-
            tion  will  be  processed  if  the  symbol 'sym' is defined (i.e
            false).  The range of true condition is optional as is the .else
            directive  and  the range of false condition.  The following are
            all valid .ifndef/.else/.endif constructions:

                    .ifndef sym$1           ;lookup symbol sym$1
                    .byte   1,2             ;insert bytes if sym$1 is
                    .endif                  ;not defined

                    .ifndef sym$2           ;lookup symbol sym$2
                    .else
                    .byte   3,4             ;insert bytes if sym$1
                    .endif                  ;is defined

            THE ASSEMBLER                                          PAGE 1-31
            GENERAL ASSEMBLER DIRECTIVES

                    .ifndef sym$3           ;lookup symbol sym$3
                    .byte   12              ;insert this byte if sym$3
                    .else                   ;is not defined
                    .byte   13              ;insert this byte if sym$3
                    .endif                  ;is defined

            The  .ifndef/.else/.endif  directives may be nested upto 10 lev-
            els.

            1.4.29  .include Directive

            Format:

                    .include        string

            where:  string  represents  a  delimited string that is the file
                            specification of an ASxxxx source file.

               The .include directive is used to insert a source file within
            the source file currently being assembled.  When this  directive
            is encountered, an implicit .page directive is issued.  When the
            end of the specified source file is reached, an  implicit  .page
            directive is issued and input continues from the previous source
            file.  The maximum nesting level of source files specified by  a
            .include directive is five.

               The  total  number  of separately specified .include files is
            unlimited as each .include file is opened and then closed during
            each pass made by the assembler.

               The  default  directory  path,  if none is specified, for any
            .include file is the directory path of the  current  file.   For
            example:   if  the  current  source file, D:\proj\file1.asm, in-
            cludes  a  file  specified   as   "include1"   then   the   file
            D:\proj\include1.asm is opened.

            1.4.30  .define and .undefine Directives

            Format:

                    .define        keyword  string

                    .undefine      keyword

            where:  keyword  is  the  substitutable  string which must start
                            with a letter and may contain any combination of
                            digits and letters.

            THE ASSEMBLER                                          PAGE 1-32
            GENERAL ASSEMBLER DIRECTIVES

            where:  string   represents  a  delimited string that is substi-
                            tuted for the keyword.  The string  may  contain
                            any   sequence  of  characters  including  white
                            space.

               The  .define  directive specifies a user defined string which
            is substituted for the keyword.  The substitution string may it-
            self  contain other keywords that are substitutable.  The assem-
            bler resumes the parse of the line at the point the keyword  was
            found.  Care must be excersized to avoid any circular references
            within .define directives, otherwise the assembler may  enter  a
            'recursion runaway' resulting in an 's' error.

               The  .undefine  directive removes the keyword as a substitut-
            able string.  No error is returned if the keyword  was  not  de-
            fined.

            1.4.31  .setdp Directive

            Format:

                    .setdp [base [,area]]

            The set direct page directive has a common format in all the as-
            semblers supporting a paged mode.  The .setdp directive is  used
            to  inform  the  assembler of the current direct page region and
            the offset address within the selected area.  The normal invoca-
            tion methods are:

                    .area   DIRECT  (PAG)
                    .setdp

                    or

                    .setdp  0,DIRECT

            for  all  the  68xx microprocessors (the 6804 has only the paged
            ram area).  The commands specify that the direct page is in area
            DIRECT and its offset address is 0 (the only valid value for all
            but the 6809 microprocessor).  Be sure to place the DIRECT  area
            at address 0 during linking.  When the base address and area are
            not specified, then zero and the current area are the  defaults.
            If  a  .setdp directive is not issued the assembler defaults the
            direct page to the area "_CODE" at offset 0.

               The  assembler  verifies  that  any  local variable used in a
            direct variable reference is located in this area.  Local  vari-
            able  and  constant value direct access addresses are checked to
            be within the address range from 0 to 255.

            THE ASSEMBLER                                          PAGE 1-33
            GENERAL ASSEMBLER DIRECTIVES

               External direct references are assumed by the assembler to be
            in the correct area and have valid  offsets.   The  linker  will
            check all direct page relocations to verify that they are within
            the correct area.

               The  6809  microprocessor  allows the selection of the direct
            page to be on any 256 byte boundary by loading  the  appropriate
            value  into the dp register.  Typically one would like to select
            the page boundary at link time, one method follows:

                    .area   DIRECT  (PAG)   ; define the direct page
                    .setdp
                    .
                    .
                    .
                    .area   PROGRAM
                    .
                    ldd     #DIRECT         ; load the direct page register
                    tfr     a,dp            ; for access to the direct page

            At  link  time specify the base and global equates to locate the
            direct page:

                    -b DIRECT = 0x1000
                    -g DIRECT = 0x1000

            Both  the  area address and offset value must be specified (area
            and variable names are independent).   The  linker  will  verify
            that  the  relocated  direct page accesses are within the direct
            page.
            The  preceeding  sequence  could  be repeated for multiple paged
            areas, however an alternate method is to define a non-paged area
            and use the .setdp directive to specify the offset value:

                    .area   DIRECT          ; define non-paged area
                    .
                    .
                    .
                    .area   PROGRAM
                    .
                    .setdp  0,DIRECT        ; direct page area
                    ldd     #DIRECT         ; load the direct page register
                    tfr     a,dp            ; for access to the direct page
                    .
                    .
                    .setdp  0x100,DIRECT    ; direct page area
                    ldd     #DIRECT+0x100   ; load the direct page register
                    tfr     a,dp            ; for access to the direct page

            The  linker  will  verify that subsequent direct page references
            are in the specified area and offset address range.  It  is  the
            programmers  responsibility  to  load  the  dp register with the

            THE ASSEMBLER                                          PAGE 1-34
            GENERAL ASSEMBLER DIRECTIVES

            correct page segment corresponding to the  .setdp  base  address
            specified.

               For  those  cases  where a single piece of code must access a
            defined data structure within a direct page and there  are  many
            pages,  define  a  dumby  direct page linked at address 0.  This
            dumby page is used only to define  the  variable  labels.   Then
            load  the dp register with the real base address but donot use a
            .setdp directive.  This method is equivalent to indexed address-
            ing,  where the dp register is the index register and the direct
            addressing is the offset.

            1.4.32  .16bit, .24bit, and .32bit Directives

            Format:

                    .16bit          ;specify 16-bit addressing
                    .24bit          ;specify 24-bit addressing
                    .32bit          ;specify 32-bit addressing

               The  .16bit, .24bit, and .32bit directives are special direc-
            tives for assembler configuration when default  values  are  not
            used.  (Currently only the as8xCxxx and aspic assemblers can use
            the .16bit, .24bit, or .32bit directives in special mode.)

            1.4.33  .end Directive

            Format:

                    .end

                    .end    exp

            where:  exp     represents  any expression, including constants,
                            symbols, or labels.

               The  .end  directive is used to specify a code entry point to
            be included in the linker output file.  Review  the  I86  and  S
            record formats described in the linker section for details.

               The .end directive without an expression is ignored.

            THE ASSEMBLER                                          PAGE 1-35
            GENERAL ASSEMBLER DIRECTIVES

            1.5  INVOKING ASXXXX

               The ASxxxx assemblers are command line oriented.  Most sytems
            require the option(s) and file(s) arguments to follow the ASxxxx
            assembler name:

            as6809 [-Options] file1 [file2 file3 ...]

            Some  systems  may  request the arguments after the assembler is
            started at a system specific prompt:

            as6809
            argv:  [-Options] file1 [file2 file3 ...]

            The options are:

                    -d      decimal listing
                    -q      octal   listing
                    -x      hex     listing (default)

                            The listing radix affects the
                            .lst, .rel, and .sym files.

                    -g      undefined symbols made global
                    -a      all user symbols made global

                    -b      display .define substitutions in listing
                    -bb     and display without .define substitutions

                    -j      enable NOICE debug symbols
                    -y      enable SDCC debug symbols

                    -l      create list   output file1.lst
                    -o      create object output file1.rel
                    -s      create symbol output file1.sym

                    -p      disable listing pagination
                    -u      disable .list/.nlist processing
                    -w      wide listing format for symbol table

                    -z      disable case sensitivity for symbols

                            relocatable reference flagging:

                    -f      by  `   in the listing file
                    -ff     by mode in the listing file

               The file name for the .lst, .rel, and .sym files is the first
            file name specified in the command line.  All output  files  are

            THE ASSEMBLER                                          PAGE 1-36
            INVOKING ASXXXX

            ascii  text  files which may be edited, copied, etc.  The output
            files are the concatenation of all the input files, if files are
            to  be  assembled  independently  invoke  the assembler for each
            file.

               The  .rel  file contains a radix directive so that the linker
            will use the proper conversion for this file.  Linked files  may
            have different radices.

               If  the list (l) option is specified without the symbol table
            (s) option, the symbol table is placed at the end of the listing
            file.

            1.6  ERRORS

               The  ASxxxx assemblers provide limited diagnostic error codes
            during the assembly process, these errors will be noted  in  the
            listing file and printed on the stderr device.

               The assembler reports the errors on the stderr device as

                    ?ASxxxx-Error-<*> in line nnn of filename

            where  * is the error code, nnn is the line number, and filename
            is the source/include file.

               The errors are:

                  (.)   This  error  is caused by an absolute direct assign-
                        ment of the current location counter
                              . = expression (incorrect)
                        rather than the correct
                              . = . + expression

                  (a)   Indicates  a machine specific addressing or address-
                        ing mode error.

                  (b)   Indicates a direct page boundary error.

                  (d)   Indicates a direct page addressing error.

                  (e)   Caused by a .error or .assume directive.

                  (i)   Caused  by  an  .include file error or an .if/.endif
                        mismatch.

                  (m)   Multiple  definitions  of  the  same label, multiple
                        .module directives, or multiple  conflicting  attri-
                        butes in an .area or .bank directive.

            THE ASSEMBLER                                          PAGE 1-37
            ERRORS

                  (o)   Directive  or  mnemonic error or the use of the .org
                        directive in a relocatable area.

                  (p)   Phase error:  label location changing between passes
                        2 and 3.  Normally caused by having  more  than  one
                        level of forward referencing.

                  (q)   Questionable syntax:  missing or improper operators,
                        terminators, or delimiters.

                  (r)   Relocation  error:   logic  operation attempted on a
                        relocatable term, addition of two relocatable terms,
                        subtraction  of two relocatable terms not within the
                        same programming area or external symbols.

                  (s)   String Substitution / recursion error.

                  (u)   Undefined symbol encountered during assembly.

                  (z)   Divide by 0 or Modulus by 0 error:  result is 0.

            1.7  LISTING FILE

               The  (-l) option produces an ascii output listing file.  Each
            page of output contains a five line header:

                 1.  The ASxxxx program name and page number

                 2.  Assembler Radix and Address Bits

                 3.  Title from a .title directive (if any)

                 4.  Subtitle from a .sbttl directive (if any)

                 5.  Blank line

            Each succeeding line contains five fields:

                 1.  Error field (first two characters of line)

                 2.  Current location counter

                 3.  Generated code in byte format

                 4.  Source text line number

            THE ASSEMBLER                                          PAGE 1-38
            LISTING FILE

                 5.  Source text

               The error field may contain upto 2 error flags indicating any
            errors encountered while assembling this line of source code.

               The  current  location  counter  field  displays  the 16-bit,
            24-bit, or 32-bit program position.  This field will be  in  the
            selected radix.

               The generated code follows the program location.  The listing
            radix determines the number of bytes that will be  displayed  in
            this field.  Hexidecimal listing allows six bytes of data within
            the field, decimal and octal allow four bytes within the  field.
            If more than one field of data is generated from the assembly of
            a single line of source code, then the data field is repeated on
            successive lines.

               The source text line number is printed in decimal and is fol-
            lowed by the source text.  A Source line with a .page  directive
            is never listed.

               Two  additional options are available for printing the source
            line text.  If the -b option is specified then the listed source
            line  contains all the .define substitutions.  If the -bb option
            is specified then the original source line is printed before the
            source line with substitutions.

               Two  data  field  options  are  available to flag those bytes
            which will be relocated by the linker.   If  the  -f  option  is
            specified  then  each  byte to be relocated will be preceeded by
            the '`' character.  If the -ff option  is  specified  then  each
            byte  to  be relocated will be preceeded by one of the following
            characters:

                 1.  *   paged relocation

                 2.  u   low  byte of unsigned word or unsigned byte

                 3.  v   high byte of unsigned word

                 4.  p   PCR low  byte of word relocation or PCR byte

                 5.  q   PCR high byte of word relocation

                 6.  r   low  byte relocation or byte relocation

                 7.  s   high byte relocation

               Assemblers  which  use 24-bit or 32-bit addressing use an ex-
            tended flagging mode:

            THE ASSEMBLER                                          PAGE 1-39
            LISTING FILE

                 1.  *   paged relocation

                 2.  u   1st  byte of unsigned value

                 3.  v   2nd  byte of unsigned value

                 4.  U   3rd  byte of unsigned value

                 5.  V   4th  byte of unsigned value

                 6.  p   PCR 1st  byte of relocation value or PCR byte

                 7.  q   PCR 2nd  byte of relocation value

                 8.  P   PCR 3rd  byte of relocation value

                 9.  Q   PCR 4th  byte of relocation value

                10.  r   1st  byte of relocation value or byte relocation

                11.  s   2nd  byte of relocation value

                12.  R   3rd  byte of relocation value

                13.  S   4th  byte of relocation value

            1.8  SYMBOL TABLE FILE

               The symbol table has two parts:

                 1.  The alphabetically sorted list of symbols and/or labels
                     defined or referenced in the source program.

                 2.  A  list of the program areas defined during assembly of
                     the source program.

               The sorted list of symbols and/or labels contains the follow-
            ing information:

                 1.  Program  area  number (none if absolute value or exter-
                     nal)

                 2.  The symbol or label

                 3.  Directly assigned symbol is denoted with an (=) sign

            THE ASSEMBLER                                          PAGE 1-40
            SYMBOL TABLE FILE

                 4.  The  value of a symbol, location of a label relative to
                     the  program  area  base  address  (=0),  or   a   ****
                     indicating the symbol or label is undefined.

                 5.  The  characters:   G - global, R - relocatable, and X -
                     external.

               The list of program areas provides the correspondence between
            the program area numbers and the defined program areas, the size
            of the program areas, and the area flags (attributes).

            1.9  OBJECT FILE

               The  object  file is an ascii file containing the information
            needed by the linker to bind multiple object modules into a com-
            plete  loadable  memory  image.   The object module contains the
            following designators:

                    [XDQ][HL][234]
                            X       Hexidecimal radix
                            D       Decimal radix
                            Q       Octal radix

                            H       Most significant byte first
                            L       Least significant byte first

                            2       16-Bit Addressing
                            3       24-Bit Addressing
                            4       32-Bit Addressing

                    H       Header
                    M       Module
                    G       Merge Mode
                    B       Bank
                    A       Area
                    S       Symbol
                    T       Object code
                    R       Relocation information
                    P       Paging information

               Refer to the linker for a detailed description of each of the
            designators and the format of the information contained  in  the
            object file.

                                        CHAPTER 2

                                       THE LINKER

            2.1  ASLINK RELOCATING LINKER

               ASLINK  is  the  companion  linker for the ASxxxx assemblers.
            The linker supports versions 3.xx and 4.xx of the ASxxxx  assem-
            blers.   Object  files  from version 3 and 4 may be freely mixed
            while linking.  Note that version 3 object files contain only  a
            subset of the options available in version 4.

               The  program ASLINK is a general relocating linker performing
            the following functions:

                 1.  Bind multiple object modules into a single memory image

                 2.  Resolve inter-module symbol references

                 3.  Combine  code  belonging to the same area from multiple
                     object files into a single contiguous memory region

                 4.  Search and import object module libraries for undefined
                     global variables

                 5.  Perform   byte   and   word  program  counter  relative
                     (pc or pcr) addressing calculations

                 6.  Define absolute symbol values at link time

                 7.  Define absolute area base address values at link time

                 8.  Produce Intel Hex or Motorola S output files

                 9.  Produce a map of the linked memory image

                10.  Produce  an updated listing file with the relocated ad-
                     dresses and data

            THE LINKER                                              PAGE 2-2
            INVOKING ASLINK

            2.2  INVOKING ASLINK

               Most  sytems require the options to be entered on the command
               line:

                    aslink -[options] -[option arg] files

               Some  systems  may  request the arguments after the linker is
               started at a system specific prompt:

                    aslink
                    argv:  -[options] -[option arg] files

            The allowed linker commands are:

                 1.  -c         ASlink >> prompt mode.
                     The  ASlink >>  prompt  mode reads linker commands from
                     stdin.

                 2.  -f  file   Command file mode.
                     The  command file mode imports linker commands from the
                     specified file (extension must be  .lnk),  imported  -c
                     and  -f  commands  are ignored.  If the directory path,
                     for a file to be linked, is not specified in  the  com-
                     mand  file  then  the  path  defaults  to the .lnk file
                     directory path.

                 3.  -p/-n   enable/disable echoing commands to stdout.

                 4.  -i/-s   Intel  Hex  (file.i--) or Motorola S (file.s--)
                     image output file.

                 5.  -o/-v   Specifies      that      subsequent      linked
                     files/libraries will generate object  output  (default)
                     or  suppress  object  output.   (if option -s or -i was
                     specified)

                 6.  -z      Disable Case Sensitivity for Symbols

                 7.  -m      Generate a map file (file.map).  This file con-
                     tains a list of the symbols (by area) with absolute ad-
                     dresses,  sizes  of  linked  areas,  and  other linking
                     information.

                 8.  -w      Specifies  that  a  wide listing format be used
                     for the map file.

                 9.  -xdq    Specifies  the  number  radix  for the map file
                     (Hexidecimal, Decimal, or Octal).

            THE LINKER                                              PAGE 2-3
            INVOKING ASLINK

                10.  -u      Generate  an  updated  listing  file (file.rst)
                     derived from the relocated addresses and data from  the
                     linker.

                11.  file    File(s) to be linked.  Files may be on the same
                     line as the above options or on a separate line(s)  one
                     file  per line or multiple files separated by spaces or
                     tabs.

                12.  -b  area=expression
                     (one definition per line in a linker command file.)
                     This  specifies  an area base address where the expres-
                     sion may contain constants and/or defined symbols  from
                     the linked files.

                13.  -g  symbol=expression
                     (one definition per line in a linker command file.)
                     This  specifies  the value for the symbol where the ex-
                     pression may contain constants and/or  defined  symbols
                     from the linked files.

                14.  -k  library directory path
                     (one definition per line in a linker command file.)
                     This  specifies one possible path to an object library.
                     More than one path is allowed.

                15.  -l  library file specification
                     (one definition per line in a linker command file.)
                     This  specifies a possible library file.  More than one
                     file is allowed.

                16.  -e      or null line, terminates input to the linker.

            2.3  LIBRARY PATH(S) AND FILE(S)

               The process of resolving undefined symbols after scanning the
            input object  files  includes  the  scanning  of  object  module
            libraries.   The  linker will search through all combinations of
            the library path specifications (input by the -k option) and the
            library  file  specifications (input by the -l option) that lead
            to an existing library file.  Each library file contains a  list
            (one  file  per  line)  of  modules  included in this particular
            library.  Each existing object module is scanned for a match  to
            the undefined symbol.  The first module containing the symbol is
            then linked with the previous modules to resolve the symbol  de-
            finition.   The  library  object  modules are rescanned until no
            more symbols can be resolved.   The  scanning  algorithm  allows
            resolution  of  back references.  No errors are reported for non
            existant library files or object modules.

            THE LINKER                                              PAGE 2-4
            LIBRARY PATH(S) AND FILE(S)

               The  library  file  specification may be formed in one of two
            ways:

                 1.  If  the  library  file  contained an absolute path/file
                     specification  then  this  is   the   object   module's
                     path/file.
                     (i.e.  C:\...  or C:/...)

                 2.  If  the  library  file  contains  a  relative path/file
                     specification then the concatenation of  the  path  and
                     this  file  specification  becomes  the object module's
                     path/file.
                     (i.e.  \...  or /...)

               As  an example, assume there exists a library file termio.lib
            in the syslib directory specifying the following object modules:

            \6809\io_disk        first object module
            d:\special\io_comm   second object module

            and the following parameters were specified to the linker:

            -k c:\iosystem\    the first path
            -k c:\syslib\      the second path

            -l termio          the first library file
            -l io              the second library file (no such file)

            The  linker  will attempt to use the following object modules to
            resolve any undefined symbols:

            c:\syslib\6809\io_disk.rel     (concatenated path/file)
            d:\special\io_comm.rel         (absolute path/file)

            all  other path(s)/file(s) don't exist.  (No errors are reported
            for non existant path(s)/file(s).)

            2.4  ASLINK PROCESSING

               The  linker  processes  the  files  in  the  order  they  are
            presented.  The first pass through the input files  is  used  to
            define  all  program  areas, the section area sizes, and symbols
            defined or referenced.  Undefined symbols will initiate a search
            of any specified library file(s) and the importing of the module
            containing the symbol definition.  After the first pass  the  -b
            (area  base  address) definitions, if any, are processed and the
            areas linked.

            THE LINKER                                              PAGE 2-5
            ASLINK PROCESSING

               The  area  linking proceeds by first examining the area types
            ABS, CON, REL, OVR and PAG.  Absolute areas (ABS) from  separate
            object modules are always overlayed and have been assembled at a
            specific address, these are not normally relocated (if a -b com-
            mand  is  used  on an absolute area the area will be relocated).
            Relative areas (normally defined as REL|CON) have a base address
            of  0x0000  as read from the object files, the -b command speci-
            fies the beginning address of the area.  All subsequent relative
            areas  will  be  concatenated  with  proceeding  relative areas.
            Where specific ordering is desired, the first linker input  file
            should  have  the area definitions in the desired order.  At the
            completion of the area linking all area  addresses  and  lengths
            have  been determined.  The areas of type PAG are verified to be
            on a 256 byte boundary and that the length does not  exceed  256
            bytes.  Any errors are noted on stderr and in the map file.

               Next  the  global symbol definitions (-g option), if any, are
            processed.  The symbol definitions have been delayed until  this
            point because the absolute addresses of all internal symbols are
            known and can be used in the expression calculations.

               Before  continuing  with the linking process the symbol table
            is scanned to determine if any symbols have been referenced  but
            not defined.  Undefined symbols are listed on the stderr device.
            if a .module directive was included in the  assembled  file  the
            module  making  the reference to this undefined variable will be
            printed.

               Constants  defined  as global in more than one module will be
            flagged as multiple definitions if their values are not  identi-
            cal.

               After  the  preceeding  processes are complete the linker may
            output a map file (-m option).  This file provides the following
            information:

                 1.  Global symbol values and label absolute addresses

                 2.  Defined areas and there lengths

                 3.  Remaining undefined symbols

                 4.  List of modules linked

                 5.  List of library modules linked

                 6.  List of -b and -g definitions

            THE LINKER                                              PAGE 2-6
            ASLINK PROCESSING

               The final step of the linking process is performed during the
            second pass of the input files.  As the xxx.rel files  are  read
            the code is relocated by substituting the physical addresses for
            the referenced symbols and areas and may be output in  Intel  or
            Motorola  formats.   The  number of files linked and symbols de-
            fined/referenced is limited by the processor space available  to
            build the area/symbol lists.  If the -u option is specified then
            the listing files  (file.lst)  associated  with  the  relocation
            files  (file.rel)  are  scanned  and  used  to create a new file
            (file.rst) which has all addresses and data relocated  to  their
            final values.

               The  -o/-v  options  allow the simple creation of loadable or
            overlay modules.  Loadable and overlay modules normally need  to
            be  linked  with  a  main module(s) to resolve external symbols.
            The -o/-v options can be used to enable object  output  for  the
            loadable  or overlay module(s) and suppress the object code from
            the linked main module(s).  The -o/-v  options  can  be  applied
            repeatedly  to specify a single linked file, groups of files, or
            libraries for object code inclusion or suppression.

            THE LINKER                                              Page 2-7
            ASXXXX VERSION 4.XX LINKING

            2.5  ASXXXX VERSION 4.XX LINKING

               The  linkers'  input  object file is an ascii file containing
            the information needed by the linker  to  bind  multiple  object
            modules into a complete loadable memory image.

            The object module contains the following designators:

                    [XDQ][HL][234]
                            X       Hexidecimal radix
                            D       Decimal radix
                            Q       Octal radix

                            H       Most significant byte first
                            L       Least significant byte first

                            2       16-Bit Addressing
                            3       24-Bit Addressing
                            4       32-Bit Addressing

                    H       Header
                    M       Module
                    G       Merge Mode
                    B       Bank
                    A       Area
                    S       Symbol
                    T       Object code
                    R       Relocation information
                    P       Paging information

            2.5.1  Object Module Format

               The   first   line   of   an   object   module  contains  the
            [XDQ][HL][234] format specifier  (i.e.   XH2  indicates  a  hex-
            idecimal  file  with  most significant byte first and 16-bit ad-
            dressing) for the following designators.

            THE LINKER                                              PAGE 2-8
            ASXXXX VERSION 4.XX LINKING

            2.5.2  Header Line

                    H aa areas gg global symbols

               The  header  line  specifies  the number of areas(aa) and the
            number of global symbols(gg) defined or referenced in  this  ob-
            ject module segment.

            2.5.3  Module Line

                    M name

               The  module  line  specifies  the module name from which this
            header segment was assembled.  The module line will  not  appear
            if the .module directive was not used in the source program.

            2.5.4  Merge Mode Line

                    G nn ii 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

               The  mode  structure  contains  the specification (or partial
            specification) of one of the assemblers' merge  modes.   Sixteen
            bits  may  be  specified  on a single line.  Each assembler must
            specify at least one merge mode.  The merging specification  al-
            lows  arbitrarily defined active bits and bit positions.  The 32
            element arrays are indexed from 0 to 31.  Index 0 corresponds to
            bit  0,  ...,  and  31 corresponds to bit 31 of a normal integer
            value.

                 1.   nn is merge mode number

                 2.   ii is the beginning bit position of the following data

                 3.   00 ...  merge mode bit elements

                        The value of the element specifies if the normal in-
                        teger bit is active (bit <7> is set, 0x80) and  what
                        destination  bit  (bits  <4:0>,  0  -  31) should be
                        loaded with this normal integer bit.

            THE LINKER                                              PAGE 2-9
            ASXXXX VERSION 4.XX LINKING

            2.5.5  Bank Line

                    B string base nn size nn map nn flags nn fsfx string

               The  B  line  defines  a  bank name as 'string'.  A bank is a
            structure containing a collection of areas.  The bank is treated
            as  a  unique linking structure seperate from other banks.  Each
            bank can have a unique base  address  (starting  address).   The
            size  specification  may  be  used to signal the overflow of the
            banks' allocated space.  The Linker combines all areas  included
            within  a  bank  as  seperate from other areas.  The code from a
            bank may be output to a unique file by specifying the File  Suf-
            fix  parameter  (fsfx).   This allows the seperation of multiple
            data and code segments into  isolated  output  files.   The  map
            parameter  is  for  NOICE processing.  The flags indicate if the
            parameters have been set.

            2.5.6  Area Line

                    A label size ss flags ff

               The  area  line  defines the area label, the size (ss) of the
            area in bytes, and the area flags (ff).  The area flags  specify
            the ABS, REL, CON, OVR, and PAG parameters:

                    OVR/CON  (0x04/0x00 i.e.  bit position 2)

                    ABS/REL  (0x08/0x00 i.e.  bit position 3)

                    PAG      (0x10 i.e.  bit position 4)

            2.5.7  Symbol Line

                    S string Defnnnn

                            or

                    S string Refnnnn

               The  symbol line defines (Def) or references (Ref) the symbol
            'string' with the value nnnn.  The defined value is relative  to
            the  current area base address.  References to constants and ex-
            ternal global symbols will always appear before the  first  area
            definition.  References to external symbols will have a value of
            zero.

            THE LINKER                                             PAGE 2-10
            ASXXXX VERSION 4.XX LINKING

            2.5.8  T Line

                    T xx xx nn nn nn nn nn ...

               The  T  line contains the assembled code output by the assem-
            bler with xx xx being the offset address from the  current  area
            base address and nn being the assembled instructions and data in
            byte format.  (xx xx and nn nn can be 2, 3, or 4 bytes as speci-
            fied by the .REL file header.)

            2.5.9  R Line

                    R 0 0 nn nn n1 n2 xx xx ...

               The R line provides the relocation information to the linker.
            The nn nn value is the current area index, i.e.  which area  the
            current  values  were  assembled.  Relocation information is en-
            coded in groups of 4 bytes:

                 1.  n1 is the relocation mode and object format.
                     1.  bits <1:0> specify the number of bytes to output
                     2.  bits <2:3> normal(0x00) /   MSB   (0x0C)
                                    signed(0x04) / unsigned(0x08)
                     3.  bit 4  normal(0x00)/page   '0' (0x10) reference
                     4.  bit 5  normal(0x00)/page 'nnn' (0x20) reference
                                PAGX mode if both bits are set (0x30)
                     5.  bit 6  normal(0x00)/PC relative(0x40) relocation
                     6.  bit 7  relocatable area(0x00)/symbol(0x80)

                 2.  n2 is a byte index and a merge mode index
                     1.  bits <3:0>  are a byte index into the corresponding
                         (i.e.  preceeding) T line data (i.e.  a pointer  to
                         the data to be updated by the relocation).
                     2.  bits <7:4> are an index into a selected merge mode.
                         Currently mode 0 simply specifies to  use  standard
                         byte processing modes and merging is ignored.

                 3.  xx xx  is the area/symbol index for the area/symbol be-
                     ing referenced.  the corresponding area/symbol is found
                     in the header area/symbol lists.

            The groups of 4 bytes are repeated for each item requiring relo-
            cation in the preceeding T line.

            THE LINKER                                             PAGE 2-11
            ASXXXX VERSION 4.XX LINKING

            2.5.10  P Line

                    P 0 0 nn nn n1 n2 xx xx

               The  P  line provides the paging information to the linker as
            specified by a .setdp directive.  The format of  the  relocation
            information is identical to that of the R line.  The correspond-
            ing T line has the following information:
                    T xx xx aa aa bb bb

               Where  aa aa is the area reference number which specifies the
            selected page area and bb bb is the base address  of  the  page.
            bb bb will require relocation processing if the 'n1 n2 xx xx' is
            specified in the P line.  The linker will verify that  the  base
            address is on a 256 byte boundary and that the page length of an
            area defined with the PAG type is not larger than 256 bytes.

               The  linker  defaults any direct page references to the first
            area defined in the input REL file.  All ASxxxx assemblers  will
            specify the _CODE area first, making this the default page area.

            2.5.11  24-Bit and 32-Bit Addressing

               When  24-bit  or  32-bit  addressing is specified in the file
            format line [XDQ][HL][234] then the S and T Lines have  modified
            formats:
                    S string Defnnnnnn                      (24-bit)
                    S string Refnnnnnn                      (24-bit)
                    T xx xx xx nn nn nn nn nn ...           (24-bit)

                    S string Defnnnnnnnn                    (32-bit)
                    S string Refnnnnnnnn                    (32-bit)
                    T xx xx xx xx nn nn nn nn nn ...        (32-bit)

               The  multibyte  formats for byte data replace the 2-byte form
            for 16-bit data with 3-byte or 4-byte data for 24-bit or  32-bit
            data  respectively.  The 2nd byte format (also named MSB) always
            uses the second byte of the 2, 3, or 4-byte data.

            THE LINKER                                             PAGE 2-12
            ASXXXX VERSION 4.XX LINKING

            2.5.12  ASlink V4.xx Error Messages

               The linker provides detailed error messages allowing the pro-
            grammer to quickly find the errant code.   As  the  linker  com-
            pletes  pass 1  over  the  input  file(s)  it  reports  any page
            boundary or page length errors as follows:

            ?ASlink-Warning-Paged Area PAGE0 Boundary Error

            and/or

            ?ASlink-Warning-Paged Area PAGE0 Length Error

            where PAGE0 is the paged area.

               During  Pass  two the linker reads the T, R, and P lines per-
            forming the necessary relocations and  outputting  the  absolute
            code.  Various errors may be reported during this process
            The P line processing can produce only one possible error:

            ?ASlink-Warning-Page Definition Boundary Error
                     file        module      pgarea    pgoffset
              PgDef  t6809l      t6809l      PAGE0         0001

            The error message specifies the file and module where the .setdp
            direct was issued and indicates  the  page  area  and  the  page
            offset value determined after relocation.

            The R line processing produces various error messages:

            ?ASlink-Warning-Signed value error
            ?ASlink-Warning-Unsigned value error
            ?ASlink-Warning-Byte PCR relocation error
            ?ASlink-Warning-Word PCR relocation error
            ?ASlink-Warning-3-Byte PCR relocation error
            ?ASlink-Warning-4-Byte PCR relocation error
            ?ASlink-Warning-Page0 relocation error
            ?ASlink-Warning-PageN relocation error
            ?ASlink-Warning-PageX relocation error
            ?ASlink-Warning-Signed Merge Bit Range error
            ?ASlink-Warning-Unsigned/Overflow Merge Bit Range error

            These  error  messages  also specify the file, module, area, and
            offset within the area of the code referencing (Refby)  and  de-
            fining (Defin) the symbol:

            ?ASlink-Warning-Signed value error for symbol  two56
                     file        module      area        offset
              Refby  t           Pagetest    PROGRAM     0006
              Defin  t           Pagetest    DIRECT      0100

            THE LINKER                                             PAGE 2-13
            ASXXXX VERSION 4.XX LINKING

            If the symbol is defined in the same module as the reference the
            linker is unable to report the symbol name.  The assembler list-
            ing  file(s) should be examined at the offset from the specified
            area to locate the offending code.

               The errors are:

                 1.  The  Signed value error indicates an indexing value ex-
                     ceeded the maximum negative or maximum  positive  value
                     for the current variable size.

                 2.  The  Unsigned  value  error indicates an indexing value
                     was greater than maximum positive value for the current
                     variable size.

                 3.  The  byte PCR error is caused by exceeding the pc rela-
                     tive byte branch range.

                 4.  The  word PCR error is caused by exceeding the pc rela-
                     tive word branch range.

                 5.  The  3-byte PCR error is caused by exceeding the pc re-
                     lative 3-byte branch range.

                 6.  The  4-byte PCR error is caused by exceeding the pc re-
                     lative 4-byte branch range.

                 7.  The  Page0  error is generated if the direct page vari-
                     able is not in the page0 range of 0 to 255.

                 8.  The  PageN  error is generated if the direct page vari-
                     able is not within the Nth page range of 0 to 255.

                 9.  The  PageX  error is generated if the direct page vari-
                     able is not within the extended page range.

                10.  The  Signed Merge Bit Range error indicates an indexing
                     value exceeded the maximum negative or maximum positive
                     value for the current signed merge variable size.

                11.  The  Unsigned/Overflow  Merge Bit Range error indicates
                     an indexing value was  greater  than  maximum  positive
                     value for the current unsigned merge variable size.

            THE LINKER                                             Page 2-14
            ASXXXX VERSION 3.XX LINKING

            2.6  ASXXXX VERSION 3.XX LINKING

               The  linkers'  input  object file is an ascii file containing
            the information needed by the linker  to  bind  multiple  object
            modules into a complete loadable memory image.

            The object module contains the following designators:

                    [XDQ][HL][234]
                            X       Hexidecimal radix
                            D       Decimal radix
                            Q       Octal radix

                            H       Most significant byte first
                            L       Least significant byte first

                            2       16-Bit Addressing
                            3       24-Bit Addressing
                            4       32-Bit Addressing

                    H       Header
                    M       Module
                    A       Area
                    S       Symbol
                    T       Object code
                    R       Relocation information
                    P       Paging information

            2.6.1  Object Module Format

               The   first   line   of   an   object   module  contains  the
            [XDQ][HL][234] format specifier  (i.e.   XH2  indicates  a  hex-
            idecimal  file  with  most significant byte first and 16-bit ad-
            dressing) for the following designators.

            2.6.2  Header Line

                    H aa areas gg global symbols

               The  header  line  specifies  the number of areas(aa) and the
            number of global symbols(gg) defined or referenced in  this  ob-
            ject module segment.

            THE LINKER                                             PAGE 2-15
            ASXXXX VERSION 3.XX LINKING

            2.6.3  Module Line

                    M name

               The  module  line  specifies  the module name from which this
            header segment was assembled.  The module line will  not  appear
            if the .module directive was not used in the source program.

            2.6.4  Area Line

                    A label size ss flags ff

               The  area  line  defines the area label, the size (ss) of the
            area in bytes, and the area flags (ff).  The area flags  specify
            the ABS, REL, CON, OVR, and PAG parameters:

                    OVR/CON  (0x04/0x00 i.e.  bit position 2)

                    ABS/REL  (0x08/0x00 i.e.  bit position 3)

                    PAG      (0x10 i.e.  bit position 4)

            2.6.5  Symbol Line

                    S string Defnnnn

                            or

                    S string Refnnnn

               The  symbol line defines (Def) or references (Ref) the symbol
            'string' with the value nnnn.  The defined value is relative  to
            the  current area base address.  References to constants and ex-
            ternal global symbols will always appear before the  first  area
            definition.  References to external symbols will have a value of
            zero.

            2.6.6  T Line

                    T xx xx nn nn nn nn nn ...

               The  T  line contains the assembled code output by the assem-
            bler with xx xx being the offset address from the  current  area
            base address and nn being the assembled instructions and data in
            byte format.

            THE LINKER                                             PAGE 2-16
            ASXXXX VERSION 3.XX LINKING

            2.6.7  R Line

                    R 0 0 nn nn n1 n2 xx xx ...

               The R line provides the relocation information to the linker.
            The nn nn value is the current area index, i.e.  which area  the
            current  values  were  assembled.  Relocation information is en-
            coded in groups of 4 bytes:

                 1.  n1  is  the  relocation mode and object format, for the
                     adhoc extension modes refer to asxxxx.h or aslink.h
                     1.  bit 0  word(0x00)/byte(0x01)
                     2.  bit 1  relocatable area(0x00)/symbol(0x02)
                     3.  bit 2  normal(0x00)/PC relative(0x04) relocation
                     4.  bit 3  1-byte(0x00)/2-byte(0x08) object format
                     5.  bit 4  signed(0x00)/unsigned(0x10) byte data
                     6.  bit 5  normal(0x00)/page   '0'(0x20) reference
                     7.  bit 6  normal(0x00)/page 'nnn'(0x40) reference
                     8.  bit 7  LSB  byte(0x00)/2nd  byte(0x80)  with 2-byte
                         mode

                 2.  n2  is  a byte index into the corresponding (i.e.  pre-
                     ceeding) T line data (i.e.  a pointer to the data to be
                     updated  by  the  relocation).   The T line data may be
                     1-byte or  2-byte  byte  data  format  or  2-byte  word
                     format.

                 3.  xx xx  is the area/symbol index for the area/symbol be-
                     ing referenced.  the corresponding area/symbol is found
                     in the header area/symbol lists.

            The groups of 4 bytes are repeated for each item requiring relo-
            cation in the preceeding T line.

            2.6.8  P Line

                    P 0 0 nn nn n1 n2 xx xx

               The  P  line provides the paging information to the linker as
            specified by a .setdp directive.  The format of  the  relocation
            information is identical to that of the R line.  The correspond-
            ing T line has the following information:
                    T xx xx aa aa bb bb

               Where  aa aa is the area reference number which specifies the
            selected page area and bb bb is the base address  of  the  page.
            bb bb will require relocation processing if the 'n1 n2 xx xx' is
            specified in the P line.  The linker will verify that  the  base
            address is on a 256 byte boundary and that the page length of an
            area defined with the PAG type is not larger than 256 bytes.

            THE LINKER                                             PAGE 2-17
            ASXXXX VERSION 3.XX LINKING

               The  linker  defaults any direct page references to the first
            area defined in the input REL file.  All ASxxxx assemblers  will
            specify the _CODE area first, making this the default page area.

            2.6.9  24-Bit and 32-Bit Addressing

               When  24-bit  or  32-bit  addressing is specified in the file
            format line [XDQ][HL][234] then the S and T Lines have  modified
            formats:
                    S string Defnnnnnn                      (24-bit)
                    S string Refnnnnnn                      (24-bit)
                    T xx xx xx nn nn nn nn nn ...           (24-bit)

                    S string Defnnnnnnnn                    (32-bit)
                    S string Refnnnnnnnn                    (32-bit)
                    T xx xx xx xx nn nn nn nn nn ...        (32-bit)

               The  multibyte  formats for byte data replace the 2-byte form
            for 16-bit data with 3-byte or 4-byte data for 24-bit or  32-bit
            data  respectively.  The 2nd byte format (also named MSB) always
            uses the second byte of the 2, 3, or 4-byte data.

            2.6.10  ASlink V3.xx Error Messages

               The linker provides detailed error messages allowing the pro-
            grammer to quickly find the errant code.   As  the  linker  com-
            pletes  pass 1  over  the  input  file(s)  it  reports  any page
            boundary or page length errors as follows:

            ?ASlink-Warning-Paged Area PAGE0 Boundary Error

            and/or

            ?ASlink-Warning-Paged Area PAGE0 Length Error

            where PAGE0 is the paged area.

               During  Pass  two the linker reads the T, R, and P lines per-
            forming the necessary relocations and  outputting  the  absolute
            code.  Various errors may be reported during this process

            THE LINKER                                             PAGE 2-18
            ASXXXX VERSION 3.XX LINKING

            The P line processing can produce only one possible error:

            ?ASlink-Warning-Page Definition Boundary Error
                     file        module      pgarea      pgoffset
              PgDef  t6809l      t6809l      PAGE0       0001

            The error message specifies the file and module where the .setdp
            direct was issued and indicates  the  page  area  and  the  page
            offset value determined after relocation.

            The R line processing produces various errors:

            ?ASlink-Warning-Byte PCR relocation error for symbol  bra2
            ?ASlink-Warning-Unsigned Byte error for symbol  two56
            ?ASlink-Warning-Page0 relocation error for symbol  ltwo56
            ?ASlink-Warning-Page Mode relocation error for symbol  two56
            ?ASlink-Warning-Page Mode relocation error
            ?ASlink-Warning-2K Page relocation error
            ?ASlink-Warning-512K Page relocation error

            These  error  messages  also specify the file, module, area, and
            offset within the area of the code referencing (Refby)  and  de-
            fining (Defin) the symbol:

            ?ASlink-Warning-Unsigned Byte error for symbol  two56
                     file        module      area        offset
              Refby  t6800l      t6800l      DIRECT      0015
              Defin  tconst      tconst      .  .ABS.    0100

            If the symbol is defined in the same module as the reference the
            linker is unable to report the symbol name.  The assembler list-
            ing  file(s) should be examined at the offset from the specified
            area to locate the offending code.

               The errors are:

                 1.  The  byte PCR error is caused by exceeding the pc rela-
                     tive byte branch range.

                 2.  The Unsigned byte error indicates an indexing value was
                     negative or larger than 255.

                 3.  The  Page0  error is generated if the direct page vari-
                     able is not in the page0 range of 0 to 255.

                 4.  The page mode error is generated if the direct variable
                     is not within the current direct page (6809).

                 5.  The  2K  Page  relocation  error  is  generated  if the
                     destination is not within the current  2K  page  (8051,
                     DS8xCxxx).

            THE LINKER                                             PAGE 2-19
            ASXXXX VERSION 3.XX LINKING

                 6.  The  512K  Page  relocation  error  is generated if the
                     destination  is  not  within  the  current  512K   page
                     (DS80C390).

            THE LINKER                                             Page 2-20
            INTEL IHX OUTPUT FORMAT

            2.7  INTEL IHX OUTPUT FORMAT (16-BIT)

            Record Mark Field    -  This  field  signifies  the  start  of a
                                    record, and consists of an  ascii  colon
                                    (:).

            Record Length Field  -  This   field   consists   of  two  ascii
                                    characters which indicate the number  of
                                    data   bytes   in   this   record.   The
                                    characters are the result of  converting
                                    the  number  of  bytes  in binary to two
                                    ascii characters, high digit first.   An
                                    End  of  File  record contains two ascii
                                    zeros in this field.

            Load Address Field   -  This  field  consists  of the four ascii
                                    characters which result from  converting
                                    the  the  binary value of the address in
                                    which to begin loading this record.  The
                                    order is as follows:

                                        High digit of high byte of address.
                                        Low digit of high byte of address.
                                        High digit of low byte of address.
                                        Low digit of low byte of address.

                                    In an End of File record this field con-
                                    sists of either four ascii zeros or  the
                                    program entry address.

            Record Type Field    -  This  field  identifies the record type,
                                    which is either 0 for data records or  1
                                    for  an End of File record.  It consists
                                    of two ascii characters, with  the  high
                                    digit of the record type first, followed
                                    by the low digit of the record type.

            Data Field           -  This  field consists of the actual data,
                                    converted to two ascii characters,  high
                                    digit first.  There are no data bytes in
                                    the End of File record.

            Checksum Field       -  The  checksum  field is the 8 bit binary
                                    sum of the record length field, the load
                                    address  field,  the  record type field,
                                    and the data field.  This  sum  is  then
                                    negated  (2's  complement) and converted
                                    to  two  ascii  characters,  high  digit
                                    first.

            THE LINKER                                             Page 2-21
            INTEL I86 OUTPUT FORMAT

            2.8  INTEL I86 OUTPUT FORMAT (24 OR 32-BIT)

            Record Mark Field    -  This  field  signifies  the  start  of a
                                    record, and consists of an  ascii  colon
                                    (:).

            Record Length Field  -  This   field   consists   of  two  ascii
                                    characters which indicate the number  of
                                    data   bytes   in   this   record.   The
                                    characters are the result of  converting
                                    the  number  of  bytes  in binary to two
                                    ascii characters, high digit first.   An
                                    End  of  File  record contains two ascii
                                    zeros in this field.

            Load Address Field   -  This  field  consists  of the four ascii
                                    characters which result from  converting
                                    the  the  binary value of the address in
                                    which to begin loading this record.  The
                                    order is as follows:

                                        High digit of high byte of address.
                                        Low digit of high byte of address.
                                        High digit of low byte of address.
                                        Low digit of low byte of address.

                                    In an End of File record this field con-
                                    sists of either four ascii zeros or  the
                                    program entry address.

            Record Type Field    -  This  field  identifies the record type,
                                    which is either 0 for  data  records,  1
                                    for  an  End  of File record, or 4 for a
                                    segment  record.   It  consists  of  two
                                    ascii characters, with the high digit of
                                    the record type first, followed  by  the
                                    low digit of the record type.

            Data Field           -  This  field consists of the actual data,
                                    converted to two ascii characters,  high
                                    digit first.  There are no data bytes in
                                    the End of File record.

            Checksum Field       -  The  checksum  field is the 8 bit binary
                                    sum of the record length field, the load
                                    address  field,  the  record type field,
                                    and the data field.  This  sum  is  then
                                    negated  (2's  complement) and converted
                                    to  two  ascii  characters,  high  digit
                                    first.

            THE LINKER                                             Page 2-22
            MOTOROLA S1-S9 OUTPUT FORMAT

            2.9  MOTORLA S1-S9 OUTPUT FORMAT (16-BIT)

            Record Type Field    -  This  field  signifies  the  start  of a
                                    record and  identifies  the  the  record
                                    type as follows:

                                        Ascii S1 - Data Record
                                        Ascii S9 - End of File Record

            Record Length Field  -  This  field  specifies the record length
                                    which includes the  address,  data,  and
                                    checksum   fields.   The  8  bit  record
                                    length value is converted to  two  ascii
                                    characters, high digit first.

            Load Address Field   -  This  field  consists  of the four ascii
                                    characters which result from  converting
                                    the  the  binary value of the address in
                                    which to begin loading this record.  The
                                    order is as follows:

                                        High digit of high byte of address.
                                        Low digit of high byte of address.
                                        High digit of low byte of address.
                                        Low digit of low byte of address.

                                    In an End of File record this field con-
                                    sists of either four ascii zeros or  the
                                    program entry address.

            Data Field           -  This  field consists of the actual data,
                                    converted to two ascii characters,  high
                                    digit first.  There are no data bytes in
                                    the End of File record.

            Checksum Field       -  The  checksum  field is the 8 bit binary
                                    sum of the record length field, the load
                                    address field, and the data field.  This
                                    sum is then  complemented  (1's  comple-
                                    ment)   and   converted   to  two  ascii
                                    characters, high digit first.

            THE LINKER                                             Page 2-23
            MOTOROLA S2-S8 OUTPUT FORMAT

            2.10  MOTORLA S2-S8 OUTPUT FORMAT (24-BIT)

            Record Type Field    -  This  field  signifies  the  start  of a
                                    record and  identifies  the  the  record
                                    type as follows:

                                        Ascii S2 - Data Record
                                        Ascii S8 - End of File Record

            Record Length Field  -  This  field  specifies the record length
                                    which includes the  address,  data,  and
                                    checksum   fields.   The  8  bit  record
                                    length value is converted to  two  ascii
                                    characters, high digit first.

            Load Address Field   -  This  field  consists  of  the six ascii
                                    characters which result from  converting
                                    the  the  binary value of the address in
                                    which to begin loading this record.  The
                                    order is as follows:

                                        High digit of 3rd byte of address.
                                        Low digit of 3rd byte of address.
                                        High digit of high byte of address.
                                        Low digit of high byte of address.
                                        High digit of low byte of address.
                                        Low digit of low byte of address.

                                    In an End of File record this field con-
                                    sists of either six ascii zeros  or  the
                                    program entry address.

            Data Field           -  This  field consists of the actual data,
                                    converted to two ascii characters,  high
                                    digit first.  There are no data bytes in
                                    the End of File record.

            Checksum Field       -  The  checksum  field is the 8 bit binary
                                    sum of the record length field, the load
                                    address field, and the data field.  This
                                    sum is then  complemented  (1's  comple-
                                    ment)   and   converted   to  two  ascii
                                    characters, high digit first.

            THE LINKER                                             Page 2-24
            MOTOROLA S3-S7 OUTPUT FORMAT

            2.11  MOTORLA S3-S7 OUTPUT FORMAT (32-BIT)

            Record Type Field    -  This  field  signifies  the  start  of a
                                    record and  identifies  the  the  record
                                    type as follows:

                                        Ascii S3 - Data Record
                                        Ascii S7 - End of File Record

            Record Length Field  -  This  field  specifies the record length
                                    which includes the  address,  data,  and
                                    checksum   fields.   The  8  bit  record
                                    length value is converted to  two  ascii
                                    characters, high digit first.

            Load Address Field   -  This  field  consists of the eight ascii
                                    characters which result from  converting
                                    the  the  binary value of the address in
                                    which to begin loading this record.  The
                                    order is as follows:

                                        High digit of 4th byte of address.
                                        Low digit of 4th byte of address.
                                        High digit of 3rd byte of address.
                                        Low digit of 3rd byte of address.
                                        High digit of high byte of address.
                                        Low digit of high byte of address.
                                        High digit of low byte of address.
                                        Low digit of low byte of address.

                                    In an End of File record this field con-
                                    sists of either eight ascii zeros or the
                                    program entry address.

            Data Field           -  This  field consists of the actual data,
                                    converted to two ascii characters,  high
                                    digit first.  There are no data bytes in
                                    the End of File record.

            Checksum Field       -  The  checksum  field is the 8 bit binary
                                    sum of the record length field, the load
                                    address field, and the data field.  This
                                    sum is then  complemented  (1's  comple-
                                    ment)   and   converted   to  two  ascii
                                    characters, high digit first.

                                        CHAPTER 3

                               BUILDING ASXXXX AND ASLINK

               The assemblers and linker have been successfully compiled for
            Linux, DOS,and various flavors of Windows  using  GCC,  Symantec
            C/C++  V6.1/V7.2,  DJGPP,  Cygwin,  and  VC6.  A Linux makefile,
            DJGPP makefile, Symantec project files, Cygwin makefile, and VC6
            project  files are available to build all the assemblers and the
            linker.

            3.1  BUILDING AN ASSEMBLER

               The  building  of  a typical assembler (6809 for example) re-
            quires the following files:

                 1.  m6809.h
                 2.  m09ext.c
                 3.  m09mch.c
                 4.  m09adr.c
                 5.  m09pst.c
                 6.  asxxxx.h
                 7.  asmain.c
                 8.  asdbg.c
                 9.  aslex.c
                10.  assym.c
                11.  assubr.c
                12.  asexpr.c
                13.  asdata.c
                14.  aslist.c
                15.  asout.c

               The  first  five  files are the 6809 processor dependent sec-
            tions which contain the following:

            BUILDING ASXXXX AND ASLINK                              PAGE 3-2
            BUILDING AN ASSEMBLER

                 1.  m6809.h -  header  file containing the machine specific
                     definitions of constants,  variables,  structures,  and
                     types

                 2.  m09ext -  device  description, byte order, and file ex-
                     tension information

                 3.  m09pst -  a  table of the assembler general directives,
                     special device directives, and assembler mnemonics with
                     associated operation codes

                 4.  m09mch / m09adr -  machine specific code for processing
                     the device mnemonics,  addressing  modes,  and  special
                     directives

               The  remaining  files provide the device independent sections
            which handle the details  of  file  input/output,  symbol  table
            generation,  program/data areas, expression analysis, and assem-
            bler directive processing.

            3.2  BUILDING ASLINK

               The building of the linker requires the following files:

                 1.  aslink.h
                 2.  lkmain.c
                 3.  lklex.c
                 4.  lkarea.c
                 5.  lkbank.c
                 6.  lkhead.c
                 7.  lksym.c
                 8.  lkeval.c
                 9.  lkdata.c
                10.  lklist.c
                11.  lkrloc.c
                12.  lkrloc3.c
                13.  lkrloc4.c
                14.  lklibr.c
                15.  lknoice.c
                16.  lksdcdb.c
                17.  lkout.c

                                       APPENDIX A

                                     ASAVR ASSEMBLER

            A.1  AVR ASSEMBLER NOTES

            The  AVR  series  of  processors  uses  a non unified addressing
            scheme:  the instruction addressing is 1 per  instruction  word,
            each  instruction uses 2 bytes of memory.  The processor data is
            addressed as 1 per byte of data.  To properly address  the  pro-
            gram/data spaces you, the programmer, must seperate your program
            and data into seperate code and data areas.  The  data  area  is
            addressed  as 1 per byte and the code area is addressed as 1 per
            instruction.

               The  assembler/linker  processes the instruction code so that
            the linker will output 2 bytes for each instruction  word.   The
            instruction  word  address  will  be  the  file  encoded address
            divided by 2.

            A.1.1  Processor Specific Directive

               The  normal PC relative addressing is -2047 to +2048 relative
            to the current PC.  For a processor with less than 4K  words  of
            program space the AVR relative jump/call can access any location
            due to address wrap around.

               The  ASAVR cross assembler has one (1) processor specific as-
            sembler directive which tells the assembler that the AVR has  4K
            words or less of program space.

                    .avr_4k   0     Normal PC Relative addressing
                    .avr_4k   1     AVR with <= 4K of Memory

               The  remaining  processor specific directives specify the AVR
            processor type.

                    .AT90SXXXX

            ASAVR ASSEMBLER                                         PAGE A-2
            AVR ASSEMBLER NOTES

                    .AT90S1200
                    .AT90S2313
                    .AT90S2323
                    .AT90S2343
                    .AT90S2333
                    .AT90S4433
                    .AT90S4414
                    .AT90S4434
                    .AT90S8515
                    .AT90C8534
                    .AT90S8535
                    .ATmega103
                    .ATmega603
                    .ATmega161
                    .ATmega163
                    .ATtiny10
                    .ATtiny11
                    .ATtiny12
                    .ATtiny15
                    .ATtiny22
                    .ATtiny28

               A  file, avr.sfr, contains definitions for the Spepcial Func-
            tion Registers for all the defined processors.  Edit the file to
            make  your  selection of processor and then .include the file at
            the beginning of your assembler file.

            A.2  AVR REGISTER SET

            The following is a list of the AVR registers used by ASAVR:

                    r0-r31  -       8-bit registers
                    x       -       index register (x = r27:r26)
                    y       -       index register (y = r29:r28)
                    z       -       index register (z = r31:r30)

            A.3  AVR INSTRUCTION SET

               The following tables list all AVR mnemonics recognized by the
            ASAVR assembler.  The designation [] refers to  a  required  ad-
            dressing mode argument.  The following list specifies the format
            for each addressing mode supported by ASAVR:

                    #data           immediate data

                    expr            expression

                    Rd              destination register (0-31)

            ASAVR ASSEMBLER                                         PAGE A-3
            AVR INSTRUCTION SET

                    Rd,Rs           destination register (0-31)
                                    source register (0-31)

                    Rd,#data        destination register (0-31)
                                    immediate data

                    addr            address

                    addr,Rs         destination address
                                    source register

                    Rd,addr         destination register
                                    source address

                    Rs,b            source register
                                    bit position

                    Rd,b            destination register
                                    bit position

                    A               an I/O register (0-31)

                    A,b             an I/O register (0-31)
                                    bit position

                    A,Rs            source register to
                                    output register

                    Rd,A            input register to
                                    destination register

                    Rd,X            load indirect
                    Rd,Y
                    Rd,Z

                    Rd,-X           load indirect pre-decrement
                    Rd,-Y
                    Rd,-Z

                    Rd,X+           load indirect post-increment
                    Rd,Y+
                    Rd,Z+

                    Rd,Z+Q          load indirect with displacement

                    X,Rs            store indirect
                    Y,Rs
                    Z,Rs

                    -X,Rs           store indirect pre-decrement
                    -Y,Rs
                    -Z,Rs

            ASAVR ASSEMBLER                                         PAGE A-4
            AVR INSTRUCTION SET

                    X+,Rs           store indirect post increment
                    Y+,Rs
                    Z+,Rs

                    Z+Q,Rs          store indirect with displacement

                    label           branch label

            The  terms  data, expr, displacement, bit position, A, and label
            may be expressions.

               Note  that not all instructions are available with every pro-
            cessor type.  Not all addressing modes are valid with every  in-
            struction,   refer   to   the   AVR  technical  data  for  valid
            instructions and modes.

            A.3.1  AVR Arithmetic and Logical Instructions

                    add     Rd,Rs           adc     Rd,Rs
                    adiw    Rd,#data        sub     Rd,Rs
                    subi    Rd,#data        sbc     Rd,Rs
                    sbci    Rd,#data        sbiw    Rd,#data
                    and     Rd,Rs           andi    Rd,#data
                    or      Rd,Rs           ori     Rd,#data
                    cp      Rd,Rs           eor     Rd,Rs
                    cpi     Rd,#data        cpc     Rd,Rs
                    cbr     Rd,#data        sbr     Rd,#data
                    clr     Rd              com     Rd
                    dec     Rd              inc     Rd
                    neg     Rd              ser     Rd
                    tst     Rd
                    mul     Rd,Rs           fmul    Rd,Rs
                    muls    Rd,Rs           fmuls   Rd,Rs
                    mulsu   Rd,Rs           fmulsu  Rd,Rs

            ASAVR ASSEMBLER                                         PAGE A-5
            AVR INSTRUCTION SET

            A.3.2  AVR Bit and Bit-Test Instructions

                    lsl     Rd              lsr     Rd
                    rol     Rd              ror     Rd
                    asr     Rd              swap    Rd
                    bset    b               bclr    b
                    sbi     A,b             cbi     A,b
                    bst     Rs,b            bld     Rd,b
                    sec                     sez
                    sen                     sev
                    ses                     seh
                    set                     sei
                    clc                     clz
                    cln                     clv
                    cls                     clh
                    clt                     cli
                    nop                     sleep
                    wdr

            A.3.3  AVR Skip on Test Instructions

                    cpse    Rd,Rs
                    sbrc    Rs,b            sbrs    Rs,b
                    sbic    A,b             sbis    A,b

            A.3.4  AVR Jump/Call/Return Instructions

                    jmp     addr            rjmp    addr
                    ijmp                    eijmp
                    call    addr            rcall   addr
                    icall                   eicall
                    ret                     reti

            A.3.5  AVR Short Branch Instructions

                    brcc    label           brcs    label
                    breq    label           brge    label
                    brhc    label           brhs    label
                    brid    label           brie    label
                    brlo    label           brlt    label
                    brmi    label           brne    label
                    brpl    label           brsh    label
                    brtc    label           brts    label
                    brvc    label           brvs    label

            ASAVR ASSEMBLER                                         PAGE A-6
            AVR INSTRUCTION SET

            A.3.6  AVR Short Branch Instructions with Bit Test

                    brbc    b,label         brbs    b,label

            A.3.7  AVR Data Transfer Instructions

                    mov     Rd,Rs           movw    Rd,Rs
                    ldi     Rd,#data
                    ld      []              st      []
                    ldd     []              std     []
                    lds     Rd,addr         sts     addr,Rs
                    lpm     []              elpm    []
                    spm
                    push    Rs              pop     Rd
                    in      Rd,A            out     A,Rs

                                       APPENDIX B

                                     ASPIC ASSEMBLER

            B.1  PIC ASSEMBLER NOTES

            The  PIC  series  of  processors  uses  a non unified addressing
            scheme:  the instruction addressing is 1 per  instruction  word,
            each  instruction  uses  a  word of memory varying from 12 to 16
            bits in length.  The processor data is addressed as 1  per  byte
            of  data.   To properly address the program/data spaces you, the
            programmer, must seperate your program and  data  into  seperate
            code  and  data areas.  The data area is addressed as 1 per byte
            and the code area is addressed as 1 per instruction.

               The  assembler/linker  processes the instruction code so that
            the linker will output 2 bytes for each instruction  word.   The
            instruction  word  address  will  be  the  file  encoded address
            divided by 2.

            B.2  PROCESSOR SPECIFIC DIRECTIVES

               The  ASPIC assembler has several processor specific assembler
            directives.  These directives specify a processor name, select a
            PIC  processor  family  type,  define  the  maximum ram address,
            specify ram addresses that should not be  accessed,  and  define
            the register file address page.

            ASPIC ASSEMBLER                                         PAGE B-2
            PROCESSOR SPECIFIC DIRECTIVES

            B.2.1  .pic Directive

            Format:

                    .pic    string

               The assembler uses the delimited string to define a processor
            specific symbol.  e.g:  "p12c508" produces the  symbol  __12c508
            having  a  value  of  1.   This  symbol  can  then be used in an
            .ifdef/.else/.endif construct.

               The  assembler  should  be configured by including directives
            similiar to the folowing at the beginning of your assembly file:

                    .pic            "p12c508"       ; Set PIC Name
                    .pic12bit                       ; Select PIC Type

               The  ASPIC assembler will then be configured for the PIC pro-
            cessor type "p12c508".  The .pic directive must precede the  PIC
            type directive.  The PIC type directive configures the assembler
            base on the processor name and type selection.

               An  alternate  method  to configure the ASPIC assembler is as
            follows:

                    .pic            "p12c508"       ; Set PIC Name
                    .include        "piccpu.def"    ; Selects PIC Type

               To  define  the  special function register names, bit values,
            and memory constraints for  a  specific  processor  include  the
            appropriate definition file:

                    .include        "p12c508.def"   ; Definitions

            B.2.2  .picnopic Directive

            Format:

                    .picnopic

               This directive deselects all processor specific mnemonics.

            ASPIC ASSEMBLER                                         PAGE B-3
            PROCESSOR SPECIFIC DIRECTIVES

            B.2.3  .pic12bit Directive

            Format:

                    .pic12bit

               This  directive selects the 12-bit instruction word mnemonics
            and opcode values to be used during the assembly process.

            B.2.4  .pic14bit Directive

            Format:

                    .pic14bit

               This  directive selects the 14-bit instruction word mnemonics
            and opcode values to be used during the assembly process.

            B.2.5  .pic16bit Directive

            Format:

                    .pic16bit

               This  directive selects the 16-bit instruction word mnemonics
            and opcode values to be used during the assembly process.

            B.2.6  .pic20bit Directive

            Format:

                    .pic20bit

               This  directive  selects 20-bit addressing and the 16-bit in-
            struction word mnemonics and opcode values to be used during the
            assembly process.

            ASPIC ASSEMBLER                                         PAGE B-4
            PROCESSOR SPECIFIC DIRECTIVES

            B.2.7  .picfix Directive

            Format:

                    .picfix chip,   mnemonic,       value

               This  directive  can  be  used  to "fix" or change the opcode
            value of any pic instruction of the currently selected pic type.
            e.g.:

               .picfix      "p12c671",      "clrw", 0x0103

            will  change  the  "clrw"  instruction's opcode to 0x0103 if the
            current pic type is "p12c671".

            B.2.8  .maxram Directive

            Format:

                    .maxram value

               Where value is the highest allowed ram address

            B.2.9  .badram Directive

            Format:

                    .badram address
                    .badram lo:hi

               Where  address  is  a single location and lo:hi is a range of
            addresses that should not be used.   Multiple  locations  and/or
            ranges  may  be  specified  by  seperating  the arguments with a
            comma:

                    .badram         0x23, 0x28:0x2F, ...

               The  ASPIC  assembler  will  report an error for any absolute
            register file address in the badram range.

            ASPIC ASSEMBLER                                         PAGE B-5
            PROCESSOR SPECIFIC DIRECTIVES

            B.2.10  .setdmm Directive

            Format:

                    .setdmm value

               The .setdmm (set Data Memory Map) directive is used to inform
            the assembler and linker about which ram bank has been  selected
            for  access.   The PIC17Cxxx microprocessor family allows upto 2
            (or more) banks of 256 byte ram blocks.  The PIC18Cxxx micropro-
            cessor  family allows upto 16 banks of 256 byte ram blocks.  The
            data memory map value must be set on a 256 byte boundary.  e.g.:

               .setdmm      0x0F00

               The  assembler  verifies  that  any  absolute  address to the
            register file is within the  256  byte  page.   External  direct
            references  are  assumed  by  the assembler to be in the correct
            area and have valid offsets.  The linker  will  check  all  page
            relocations  to verify that they are within the correct address-
            ing range.

            B.3  12-BIT OPCODE PIC

            The 12-bit opcode family of PIC processors support the following
            assembler arguments:
                    (*)f
                    (*)f,(#)d
                    (*)f,(#)b
                    (#)k
                    label

                    where:  f       register file address
                            d       destination select:
                                            (0, -> w), (1 -> f)
                                            the letters w or f may be used
                                            to select the destination
                            b       bit address in an 8-bit file register
                            k       literal constant
                            label   label name

                    Items enclosed in () are optional.

               The  terms  f, d, b, k, and label may all be expressions.

               Note  that  not all addressing modes are valid with every in-
            struction,  refer to the processor specific  technical data for
            valid modes.

            ASPIC ASSEMBLER                                         PAGE B-6
            12-BIT OPCODE PIC

                PIC12C5XX CPU Type
                    PIC12C508,      PIC12C509,      PIC12CE518
                    PIC12C508A,     PIC12C509A,     PIC12CE519
                    PIC12CR509A

            B.4  14-BIT OPCODE PIC

            The 14-bit opcode family of PIC processors support the following
            assembler arguments:
                    (*)f
                    (*)f,(#)d
                    (*)f,(#)b
                    (#)k
                    label

                    where:  f       register file address
                            d       destination select:
                                            (0, -> w), (1 -> f)
                                            the letters w or f may be used
                                            to select the destination
                            b       bit address in an 8-bit file register
                            k       literal constant
                            label   label name

                    Items enclosed in () are optional.

               The  terms  f, d, b, k, and label may all be expressions.

               Note  that  not all addressing modes are valid with every in-
            struction,  refer to the processor specific  technical data for
            valid modes.

                PIC12C67X CPU Type
                    PIC12C671,      PIC12C672,      PIC12LC671,
                    PIC12LC672
                    PIC12CE673,     PIC12CE674,     PIC12LCE673,
                    PIC12LCE674

                PIC14000 CPU Type
                    PIC14000

                PIC16C15X CPU Type
                    PIC16C154,      PIC16C156,      PIC16C158
                    PIC16CR154,     PIC16CR156,     PIC16CR158

                PIC16C5X CPU Type

            ASPIC ASSEMBLER                                         PAGE B-7
            14-BIT OPCODE PIC

                    PIC16C52
                    PIC16C54,       PICC16C54A,     PIC16C54B,
                    PIC16C54C
                    PIC16CR54,      PIC16CR54A,     PIC16C54B,
                    PIC16CR54C
                    PIC16C55,       PIC16C55A,      PIC16C56,
                    PIC16C56A
                    PIC16CR56A
                    PIC16C57,       PIC16CR57A,     PIC16C57B,
                    PIC16C57C
                    PIC16C58A,      PIC16CR58A,     PIC16C58B,
                    PIC16CR58B

                PIC16C55X CPU Type
                    PIC16C554,      PIC16C556,      PIC16C558

                PIC16C62X, PIC16C64X and, PIC16C66X CPU Types
                    PIC16C620,      PIC16C621,      PIC16C622
                    PIC16C642,      PIC16C662

                PIC16C7XX CPU Type
                    PIC16C71,       PIC16C72,       PIC16CR72
                    PIC16C73A,      PIC16C74A,      PIC16C76,       PIC16C77
                    PIC16C710,      PIC16C711,      PIC16C715

                PIC16C8X CPU Type
                    PIC16F83,       PIC16CR83,      PIC16F84,
                    PIC16CR84
                    PIC16HV540
                    PIC16F627,      PIC16F628
                    PIC16F870,      PIC16F871,      PIC16F872,
                    PIC16F873
                    PIC16F874,      PIC16F876,      PIC16F877

                PIC16C9XX CPU Type
                    PIC16C923,      PIC16C924

            B.5  16-BIT OPCODE PIC

            The 16-bit opcode family of PIC processors support the following
            assembler arguments:
                    (*)f
                    (*)f,(#)d
                    (*)f,(#)s
                    (*)f,(#)b
                    (*)f,(*)p       /       (*)p,(*)f
                    (#)t,(*)f
                    (#)t,(#)i,(*)f
                    {#}k
                    label

            ASPIC ASSEMBLER                                         PAGE B-8
            16-BIT OPCODE PIC

                    where:  f       register file address
                            d       destination select:
                                            (0, -> w), (1 -> f)
                                            the letters w or f may be used
                                            to select the destination
                            s       destination select:
                                            (0, -> f and w), (1, -> f)
                                            the letters w or f may be used
                                            to select the destination
                            t       table byte select:
                                            (0, -> lower byte)
                                            (1, -> upper byte)
                            i       table pointer control
                                            (0, -> no change)
                                            (1, -> post increment)
                            b       bit address of an 8-bit file register
                            p       peripheral register file address
                            k       literal constant
                            label   label name

                    Items enclosed in () are optional.

               The  terms  f, d, s, t, i, b, p, k,  and  label  may  all be
            expressions.

               Note  that  not all addressing modes are valid with every in-
            struction,  refer to the processor specific  technical data for
            valid modes.

                PIC17CXXX CPU Type
                    PIC17C42,       PIC17C42A,      PIC17C43,       PIC17C44
                    PIC17C752,      PIC17C756,      PIC17C756A
                    PIC17C762,      PIC17C766,      PIC17CR42,
                    PIC17CR43

            B.6  20-BIT ADDRESSING PIC

               The  20-bit  addressing  family of PIC processors support the
            following assembler arguments:
                    (*)f(,a)
                    (*)f,(#)d(,(#)a)
                    (*)f,(#)s
                    (*)f,(#)b(,(#)a)
                    (*)fs,(*)fd
                    (#)t,(*)f
                    (#)t,(#)i,(*)f
                    {#}k

            ASPIC ASSEMBLER                                         PAGE B-9
            20-BIT ADDRESSING PIC

                    label(,(#)s)
                    ((#)s)
                    mm

                    where:  f       register file address
                            fs      register file source
                            fd      register file destination
                            a       ram access bit
                                            (0, -> ACCESS RAM)
                                            (1, -> RAM BANK)
                            d       destination select:
                                            (0, -> w), (1 -> f)
                                            the letters w or f may be used
                                            to select the destination
                            s       fast call/return mode:
                                            (0, -> SLOW), (1, -> FAST)
                            b       bit address of an 8-bit file register
                            mm      TBLRD and TBLWT suffixs
                                            ('*',  -> no change)
                                            ('*+', -> post-increment)
                                            ('*-', -> post-decrement)
                                            ('+*', -> pre-increment)
                            k       literal constant
                            label   label name

                    Items enclosed in () are optional.

               The  terms  f, fs, fd, a, b, d, s, k, and  label  may all be
            expressions.

               Note  that  not all addressing modes are valid with every in-
            struction,  refer to the processor specific  technical data for
            valid modes.

                PIC18CXXX CPU Type
                    PIC18C242,      PIC18C252
                    PIC18C442,      PIC18C452
                    PIC18C658,      PIC18C858

            ASPIC ASSEMBLER                                        PAGE B-10
            PIC OPCODES

            B.7  PIC OPCODES

               The  following table contains all the mnemonics recognized by
            the ASPIC assembler.  The processors  supporting  each  mnemonic
            are  indicated by the code 'PIC:12:14:16:20' after each instruc-
            tion type.  The designation [] refers to a  required  addressing
            mode argument.

                    addwf   []              PIC:12:14:16:20
                    addwfc  []              PIC:--:--:16:20
                    andwf   []              PIC:12:14:16:20
                    comf    []              PIC:12:14:16:20
                    decf    []              PIC:12:14:16:20
                    decfsz  []              PIC:12:14:16:20
                    dcfsnz  []              PIC:--:--:16:20
                    incf    []              PIC:12:14:16:20
                    incfsz  []              PIC:12:14:16:20
                    infsnz  []              PIC:--:--:16:20
                    iorwf   []              PIC:12:14:16:20
                    movf    []              PIC:12:14:--:20
                    negw    []              PIC:--:--:16:--
                    rlf     []              PIC:12:14:--:--
                    rlcf    []              PIC:--:--:16:20
                    rlncf   []              PIC:--:--:16:20
                    rrf     []              PIC:12:14:--:--
                    rrcf    []              PIC:--:--:16:20
                    rrncf   []              PIC:--:--:16:20
                    subfwb  []              PIC:--:--:--:20
                    subwf   []              PIC:12:14:16:20
                    subwfb  []              PIC:--:--:16:20
                    swapf   []              PIC:12:14:16:20
                    xorwf   []              PIC:12:14:16:20

                    movfp   []              PIC:--:--:16:--
                    movpf   []              PIC:--:--:16:--

                    movlb   []              PIC:--:--:16:20
                    movlr   []              PIC:--:--:16:--

                    movff   []              PIC:--:--:--:20

                    lfsr    []              PIC:--:--:--:20

                    clrf    []              PIC:12:14:16:20
                    cpfseq  []              PIC:--:--:16:20
                    cpfsgt  []              PIC:--:--:16:20
                    cpfslt  []              PIC:--:--:16:20
                    movwf   []              PIC:12:14:16:20
                    mulwf   []              PIC:--:--:16:20
                    negf    []              PIC:--:--:--:20

            ASPIC ASSEMBLER                                        PAGE B-11
            PIC OPCODES

                    setf    []              PIC:--:--:16:20
                    tstfsz  []              PIC:--:--:16:20

                    bcf     []              PIC:12:14:16:20
                    bsf     []              PIC:12:14:16:20
                    btfsc   []              PIC:12:14:16:20
                    btfss   []              PIC:12:14:16:20
                    btg     []              PIC:--:--:16:20

                    addlw   []              PIC:--:14:16:20
                    andlw   []              PIC:12:14:16:20
                    iorlw   []              PIC:12:14:16:20
                    movlw   []              PIC:12:14:16:20
                    mullw   []              PIC:--:--:16:20
                    retlw   []              PIC:12:14:16:20
                    sublw   []              PIC:--:14:16:20
                    xorlw   []              PIC:12:14:16:20

                    call    []              PIC:12:14:16:20
                    goto    []              PIC:12:14:16:20
                    lcall   []              PIC:--:--:16:--

                    bc      []              PIC:--:--:--:20
                    bn      []              PIC:--:--:--:20
                    bnc     []              PIC:--:--:--:20
                    bnn     []              PIC:--:--:--:20
                    bnov    []              PIC:--:--:--:20
                    bnc     []              PIC:--:--:--:20
                    bov     []              PIC:--:--:--:20
                    bz      []              PIC:--:--:--:20

                    bra     []              PIC:--:--:--:20
                    rcall   []              PIC:--:--:--:20

                    tablrd  []              PIC:--:--:16:--
                    tablwt  []              PIC:--:--:16:--
                    tlrd    []              PIC:--:--:16:--
                    tlwt    []              PIC:--:--:16:--
                    tblrd   []              PIC:--:--:--:20
                    tblwt   []              PIC:--:--:--:20

                    clrw    []              PIC:12:14:--:--
                    clrwdt                  PIC:12:14:16:20
                    daw                     PIC:--:--:16:20
                    nop                     PIC:12:14:16:20
                    option                  PIC:12:14:--:--
                    pop                     PIC:--:--:--:20
                    push                    PIC:--:--:--:20
                    retfie  []              PIC:--:14:16:20
                    return  []              PIC:--:14:16:20
                    sleep                   PIC:12:14:16:20

            ASPIC ASSEMBLER                                        PAGE B-12
            PIC OPCODES

                    tris    []              PIC:12:14:--:--

                                       APPENDIX C

                                     ASRAB ASSEMBLER

            C.1  ACKNOWLEDGMENT

            Thanks to Ulrich Raich and Razaq Ijoduola for their contribution
            of the ASRAB cross assembler.

               Ulrich Raich and Razaq Ijoduola
               PS Division
               CERN
               CH-1211 Geneva-23
                    Ulrich Raich
                    Ulrich dot Raich at cern dot ch

            C.2  PROCESSOR SPECIFIC DIRECTIVES

               The  ASRAB  assembler is a port of the ASZ80 assembler.  This
            assembler can process Z80, HD64180 (Z180), and Rabbit  2000/3000
            (default)  code.   The  following  processor  specific assembler
            directives specify which processor to target when processing the
            input assembler files.

            ASRAB ASSEMBLER                                         PAGE C-2
            PROCESSOR SPECIFIC DIRECTIVES

            C.2.1  .r2k Directive

            Format:

                    .r2k

            The  .r2k  directive  enables processing of the Rabbit 2000/3000
            specific mnemonics.  Mnemonics not associated  with  the  Rabbit
            2000/3000 processor will be flagged with an 'o' error.  Address-
            ing modes not supported by the Rabbit 2000/3000 will be  flagged
            with  an 'a' error.  A synonym of .r2k is .r3k.  The default as-
            sembler mode is .r2k.

            C.2.2  .hd64 Directive

            Format:

                    .hd64

            The  .hd64  directive  enables  processing of the HD64180 (Z180)
            specific mnemonics not included  in  the  Z80  instruction  set.
            Rabbit  2000/3000  mnemonics encountered will be flagged with an
            'o' error.  Addressing modes not supported by the HD64180 (Z180)
            will be flagged with an 'a' error.  A synonym of .hd64 is .z180.

            C.2.3  .z80 Directive

            Format:

                    .z80

            The  .z80  directive  enables  processing  of  the  Z80 specific
            mnemonics.  HD64180 and Rabbit 2000/3000 specific mnemonics will
            be flagged with an 'o' error.  Addressing modes not supported by
            the z80 will be flagged with an 'a' error.

            ASRAB ASSEMBLER                                         PAGE C-3
            PROCESSOR SPECIFIC DIRECTIVES

            C.3  RABBIT 2000/3000 ADDRESSING AND INSTRUCTIONS

            C.3.1  Instruction Symbols

            b       Bit select
                            (000 = bit 0, 001 = bit 1,
                             010 = bit 2, 011 = bit 3,
                             100 = bit 4, 101 = bit 5,
                             110 = bit 6, 111 = bit 7)
            cc      Condition code select
                            (00 = NZ, 01 = Z, 10 = NC, 11 = C)
            d       8-bit (signed) displacement.
                    Expressed in two\'s complement.
            dd      word register select-destination
                            (00 = BC, 01 = DE, 10 = HL, 11 = SP)
            dd'     word register select-alternate
                            (00 = BC', 01 = DE', 10 = HL')
            e       8-bit (signed) displacement added to PC.
            f       condition code select
                            (000 = NZ, 001 = Z, 010 = NC, 011 = C,
                             100 = LZ/NV, 101 = LO/V, 110 = P, 111 = M)
            m       the most significant bits(MSB) of a 16-bit constant
            mn      16-bit constant
            n       8-bit constant or the least significant bits(LSB)
                    of a 16-bit constant
            r, g    byte register select
                            (000 = B, 001 = C, 010 = D, 011 = E,
                             100 = H, 101 = L, 111 = A)
            ss      word register select-source
                            (00 = BC, 01 = DE, 10 = HL, 11 = SP)
            v       Restart address select
                            (010 = 0020h, 011 = 0030h, 100 = 0040h,
                             101 = 0050h, 111 = 0070h)
            x       an 8-bit constant to load into the XPC
            xx      word register select
                            (00 = BC, 01 = DE, 10 = IX, 11 = SP)
            yy      word register select
                            (00 = BC, 01 = DE, 10 = IY, 11 = SP)
            zz      word register select
                            (00 = BC, 01 = DE, 10 = HL, 11 = AF)

            ASRAB ASSEMBLER                                         PAGE C-4
            RABBIT 2000/3000 ADDRESSING AND INSTRUCTIONS

                    C  -    carry bit set
                    M  -    sign bit set
                    NC -    carry bit clear
                    NZ -    zero bit clear
                    P  -    sign bit clear
                    PE -    parity even
                    V  -    overflow bit set
                    PO -    parity odd
                    NV -    overflow bit clear
                    Z  -    zero bit set

            The  terms  m, mn, n, and x may all be expressions.  The terms b
            and v are not allowed to be external references.

            ASRAB ASSEMBLER                                         PAGE C-5
            RABBIT 2000/3000 ADDRESSING AND INSTRUCTIONS

            C.3.2  Rabbit Instructions

               The  following list of instructions (with explicit addressing
            modes) are available in the  Rabbit  2000/3000  assembler  mode.
            Those instructions denoted by an asterisk (*) are additional in-
            structions not available in the HD64180 or Z80 assembler mode.

             ADC A,n                 DEC IX                  LD A,EIR
             ADC A,r                 DEC IY                  LD A,IIR
             ADC A,(HL)              DEC r                  *LD A,XPC
             ADC A,(IX+d)            DEC ss                  LD A,(BC)
             ADC A,(IY+d)            DEC (HL)                LD A,(DE)
             ADC HL,ss               DEC (IX+d)              LD A,(mn)
             ADD A,n                 DEC (IY+d)             *LD dd,BC
             ADD A,r                 DJNZ e                 *LD dd,DE
             ADD A,(HL)                                      LD dd,mn
             ADD A,(IX+d)            EX AF,AF                LD dd,(mn)
             ADD A,(IY+d)            EX DE,HL                LD EIR,A
             ADD HL,ss               EX DE,HL               *LD HL,IX
             ADD IX,xx               EX (SP),HL             *LD HL,IY
             ADD IY,yy               EX (SP),IX             *LD HL,(HL+d)
            *ADD SP,d                EX (SP),IY             *LD HL,(IX+d)
            *ALTD                    EXX                    *LD HL,(IY+d)
            *AND HL,DE                                       LD HL,(mn)
            *AND IX,DE               INC IX                 *LD HL,(SP+n)
            *AND IY,DE               INC IY                  LD IIR,A
             AND n                   INC r                  *LD IX,HL
             AND r                   INC ss                  LD IX,mn
             AND (HL)                INC (HL)                LD IX,(mn)
             AND (IX+d)              INC (IX+d)             *LD IX,(SP+n)
             AND (IY+d)              INC (IY+d)             *LD IY,HL
                                    *IOE                     LD IY,mn
             BIT b,r                *IOI                     LD IY,(mn)
             BIT b,(HL)             *IPRES                  *LD IY,(SP+n)
             BIT b,(IX+d)           *IPSET 0                 LD r,g
             BIT b,(IY+d)           *IPSET 1                 LD r,n
            *BOOL HL                *IPSET 2                 LD r,(HL)
            *BOOL IX                *IPSET 3                 LD r,(IX+d)
            *BOOL IY                                         LD r,(IY+d)
                                     JP f,mn                 LD SP,HL
             CALL mn                 JP mn                   LD SP,IX
             CCF                     JP (HL)                 LD SP,IY
             CP n                    JP (IX)                *LD XPC,A
             CP r                    JP (IY)                 LD (BC),A
             CP (HL)                 JR cc,e                 LD (DE),A
             CP (IX+d)               JR e                    LD (HL),n
             CP (IY+d)                                       LD (HL),r
             CPL                    *LCALL x,mn

            ASRAB ASSEMBLER                                         PAGE C-6
            RABBIT 2000/3000 ADDRESSING AND INSTRUCTIONS

            *LD (HL+d),HL           *POP IP                  SBC A,n
            *LD (IX+d),HL            POP IX                  SBC A,r
             LD (IX+d),n             POP IY                  SBC A,(HL)
             LD (IX+d),r             POP zz                  SBC HL,ss
            *LD (IY+d),HL           *PUSH IP                 SBC (IX+d)
             LD (IY+d),n             PUSH IX                 SBC (IY+d)
             LD (IY+d),r             PUSH IY                 SCF
             LD (mn),A               PUSH zz                 SET b,r
             LD (mn),HL                                      SET b,(HL)
             LD (mn),IX              RA                      SET b,(IX+d)
             LD (mn),IY              RES b,r                 SET b,(IY+d)
             LD (mn),ss              RES b,(HL)              SLA r
            *LD (SP+n),HL            RES b,(IX+d)            SLA (HL)
            *LD (SP+n),IX            RES b,(IY+d)            SLA (IX+d)
            *LD (SP+n),IY            RET                     SLA (IY+d)
             LDD                     RET f                   SRA r
             LDDR                   *RETI                    SRA (HL)
             LDI                    *RL DE                   SRA (IX+d)
             LDIR                    RL r                    SRA (IY+d)
            *LDP HL,(HL)             RL (HL)                 SRL r
            *LDP HL,(IX)             RL (IX+d)               SRL (HL)
            *LDP HL,(IY)             RL (IY+d)               SRL (IX+d)
            *LDP HL,(mn)             RLA                     SRL (IY+d)
            *LDP IX,(mn)             RLC r                   SUB n
            *LDP IY,(mn)             RLC (HL)                SUB r
            *LDP (HL),HL             RLC (IX+d)              SUB (HL)
            *LDP (IX),HL             RLC (IY+d)              SUB (IX+d)
            *LDP (IY),HL             RLCA                    SUB (IY+d)
            *LDP (mn),HL            *RR DE
            *LDP (mn),IX            *RR HL                   XOR n
            *LDP (mn),IY            *RR IX                   XOR r
             LJP x,mn               *RR IY                   XOR (HL)
             LRET                    RR r                    XOR (IX+d)
                                     RR (HL)                 XOR (IY+d)
            *MUL                     RR (IX+d)
                                     RR (IY+d)
             NEG                     RRC r
             NOP                     RRC (HL)
                                     RRC (IX+d)
            *OR HL,DE                RRC (IY+d)
            *OR IX,DE                RRCA
            *OR IY,DE                RST v
             OR n
             OR r
             OR (HL)
             OR (IX+d)
             OR (IY+d)

            ASRAB ASSEMBLER                                         PAGE C-7
            Z80/HD64180 ADDRESSING AND INSTRUCTIONS

            C.4  Z80/HD64180 ADDRESSING AND INSTRUCTIONS

            The following list specifies the format for each Z80/HD64180 ad-
            dressing mode supported by ASZ80:

                    #data           immediate data
                                    byte or word data

                    n               byte value

                    rg              a byte register
                                    a,b,c,d,e,h,l

                    rp              a register pair
                                    bc,de,hl

                    (hl)            implied addressing or
                                    register indirect addressing

                    (label)         direct addressing

                    (ix+offset)     indexed addressing with
                     offset(ix)     an offset

                    label           call/jmp/jr label

            The  terms  data,  n, label, and offset, may all be expressions.
            The terms dir and offset are not allowed to be  external  refer-
            ences.

               The  following  tables  list all Z80/HD64180 mnemonics recog-
            nized by the ASRAB assembler.  The designation []  refers  to  a
            required addressing mode argument.  Note that not all addressing
            modes are valid with every instruction, refer to the Z80/HD64180
            technical data for valid modes.

            ASRAB ASSEMBLER                                         PAGE C-8
            Z80/HD64180 ADDRESSING AND INSTRUCTIONS

            C.4.1  Inherent Instructions

                    ccf             cpd
                    cpdr            cpi
                    cpir            cpl
                    daa             di
                    ei              exx
                    halt            neg
                    nop             reti
                    retn            rla
                    rlca            rld
                    rra             rrca
                    rrd             scf

            C.4.2  Implicit Operand Instructions

                    adc     a,[]            adc     []
                    add     a,[]            add     []
                    and     a,[]            and     []
                    cp      a,[]            cp      []
                    dec     a,[]            dec     []
                    inc     a,[]            inc     []
                    or      a,[]            or      []
                    rl      a,[]            rl      []
                    rlc     a,[]            rlc     []
                    rr      a,[]            rr      []
                    rrc     a,[]            rrc     []
                    sbc     a,[]            sbc     []
                    sla     a,[]            sla     []
                    sra     a,[]            sra     []
                    srl     a,[]            srl     []
                    sub     a,[]            sub     []
                    xor     a,[]            xor     []

            ASRAB ASSEMBLER                                         PAGE C-9
            Z80/HD64180 ADDRESSING AND INSTRUCTIONS

            C.4.3  Load Instruction

                    ld      rg,[]           ld      [],rg
                    ld      (bc),a          ld      a,(bc)
                    ld      (de),a          ld      a,(de)
                    ld      (label),a       ld      a,(label)
                    ld      (label),rp      ld      rp,(label)
                    ld      i,a             ld      r,a
                    ld      a,i             ld      a,r
                    ld      sp,hl           ld      sp,ix
                    ld      sp,iy           ld      rp,#data
                    ldd                     lddr
                    ldi                     ldir

            C.4.4  Call/Return Instructions

                    call    C,label         ret     C
                    call    M,label         ret     M
                    call    NC,label        ret     NC
                    call    NZ,label        ret     NZ
                    call    P,label         ret     P
                    call    PE,label        ret     PE
                    call    PO,label        ret     PO
                    call    Z,label         ret     Z
                    call    label           ret

            C.4.5  Jump and Jump to Subroutine Instructions

                    jp      C,label         jp      M,label
                    jp      NC,label        jp      NZ,label
                    jp      P,label         jp      PE,label
                    jp      PO,label        jp      Z,label
                    jp      (hl)            jp      (ix)
                    jp      (iy)            jp      label
                    djnz    label
                    jr      C,label         jr      NC,label
                    jr      NZ,label        jr      Z,label
                    jr      label

            ASRAB ASSEMBLER                                        PAGE C-10
            Z80/HD64180 ADDRESSING AND INSTRUCTIONS

            C.4.6  Bit Manipulation Instructions

                    bit     n,[]
                    res     n,[]
                    set     n,[]

            C.4.7  Interrupt Mode and Reset Instructions

                    im      n
                    im      n
                    im      n
                    rst     n

            C.4.8  Input and Output Instructions

                    in      a,(n)           in      rg,(c)
                    ind                     indr
                    ini                     inir
                    out     (n),a           out     (c),rg
                    outd                    otdr
                    outi                    otir

            C.4.9  Register Pair Instructions

                    add     hl,rp           add     ix,rp
                    add     iy,rp
                    adc     hl,rp           sbc     hl,rp
                    ex      (sp),hl         ex      (sp),ix
                    ex      (sp),iy
                    ex      de,hl
                    ex      af,af'
                    push    rp              pop     rp

            ASRAB ASSEMBLER                                        PAGE C-11
            Z80/HD64180 ADDRESSING AND INSTRUCTIONS

            C.4.10  HD64180 Specific Instructions

                    in0     rg,(n)
                    out0    (n),rg
                    otdm                    otdmr
                    otim                    otimr
                    mlt     bc              mlt     de
                    mlt     hl              mlt     sp
                    slp
                    tst     a
                    tstio   #data

                                       APPENDIX D

                                   AS8XCXXX ASSEMBLER

            D.1  ACKNOWLEDGMENTS

               Thanks to Bill McKinnon for his contributions to the AS8XCXXX
            cross assembler.

                    Bill McKinnon
                    w_mckinnon at conknet dot com

               This  assembler  was  derived from the AS8051 cross assembler
            contributed by John Hartman.

                    John L. Hartman
                    jhartman at compuserve dot com
                    noice at noicedebugger dot com

            D.2  DS8XCXXX ASSEMBLER DIRECTIVES

               The  AS8XCXXX  assembler  contains  directives to specify the
            particular SFR (Special Function Registers) to be enabled during
            the assembly process.  The following directives are supported:

                    .DS8XCXXX               ;80C32 core
                    .DS80C310               ;Dallas Semiconductor
                    .DS80C320               ;Microprocessors
                    .DS80C323
                    .DS80C390
                    .DS83C520
                    .DS83C530
                    .DS83C550
                    .DS87C520
                    .DS87C530
                    .DS87C550

            AS8XCXXX ASSEMBLER                                      PAGE D-2
            DS8XCXXX ASSEMBLER DIRECTIVES

            If  the  microprocessor  selector  directive  is  followed  by a
            non-zero argument then the SFR register bit values will also  be
            defined.

               If  a microprocessor selector directive is not specified then
            no SFR or SFR register bit values will be  defined.   This  mode
            allows  the  SFR  to  be  defined by an external assembly source
            file.  The file DS8XCXXX.SFR contains the SFR and  SFR  register
            bit values for all the microprocessor selector directives.  This
            file may be modified to create a new SFR for other  microproces-
            sor types.

               Also, if a microprocessor selector directive is not specified
            then the  following  address  length  assembler  directives  are
            accepted:

                    .16bit                  ;16-Bit Addressing
                    .24bit                  ;24-Bit Addressing
                    .32bit                  ;32-Bit Addressing

            These  directives specify the assembler addressing space and ef-
            fect the output format for the .lst, .sym, and .rel files.

               The  default  addressing space for defined microprocessors is
            16-Bit except for the DS80C390 microprocessor which is 24-Bit.

            D.2.1  DS80C390 Addressing Mode Directive

               The  DS80C390  microprocessor  supports 16-Bit and 24-Bit ad-
            dressing modes.   The  .amode  assembler  directive  provides  a
            method  to  select  the addressing mode used by the ajmp, acall,
            ljmp, and lcall instructions.  These four  instructions  support
            16  and  24 bit addressing modes selected by bits AM0 and AM1 in
            the ACON register.  The assembler is 'informed'  about  the  ad-
            dressing mode selected by using the .amode directive:

                    .amode  2       ;mode 2 is 24-bit addressing

            If  a  second  argument  is specified and its value is non-zero,
            then a three instruction sequence is inserted at the .amode  lo-
            cation loading the mode bits into the ACON register:

                    .amode  2,1     ;mode 2 is 24-bit addressing, load ACON
                    ;mov    ta,#0xAA
                    ;mov    ta,#0x55
                    ;mov    acon,#amode

            AS8XCXXX ASSEMBLER                                      PAGE D-3
            DS8XCXXX ASSEMBLER DIRECTIVES

            D.3  DS8XCXXX REGISTER SET

            The  AS8XCXXX  cross assembler supports the Dallas Semiconductor
            DS8XCXXX series of 8051-compatible devices.  These  microproces-
            sors  retain  instruction set and object code compatability with
            the 8051 microprocessor.  The DS8XCXXX family  is  updated  with
            several   new  peripherals  while  providing  all  the  standard
            features of the 80C32 microprocessor.

               The following is a list of the registers used by AS8XCXXX:

                    a,b             -       8-bit accumulators
                    r0,r1,r2,r3     -       8-bit registers
                    r4,r5,r6,r7
                    dptr            -       data pointer
                    sp              -       stack pointer
                    pc              -       program counter
                    psw             -       status word
                    c               -       carry (bit in status word)

            D.4  DS8XCXXX INSTRUCTION SET

               The  following  tables list all DS8XCXXX mnemonics recognized
            by the AS8XCXXX assembler.  The  following  list  specifies  the
            format for each addressing mode supported by AS8XCXXX:

                    #data           immediate data
                                    byte or word data

                    r,r1,r2         register r0,r1,r2,r3,r4,r5,r6, or r7

                    @r              indirect on register r0 or r1
                    @dptr           indirect on data pointer
                    @a+dptr         indirect on accumulator
                                    plus data pointer
                    @a+pc           indirect on accumulator
                                    plus program counter

                    addr            direct memory address

                    bitaddr         bit address

                    label           call or jump label

            The terms data, addr, bitaddr, and label may all be expressions.

               Note  that  not all addressing modes are valid with every in-
            struction.  Refer to  the  DS8XCXXX  technical  data  for  valid
            modes.

            AS8XCXXX ASSEMBLER                                      PAGE D-4
            DS8XCXXX INSTRUCTION SET

            D.4.1  Inherent Instructions

                    nop

            D.4.2  Move Instructions

                    mov     a,#data         mov     a,addr
                    mov     a,r             mov     a,@r

                    mov     r,#data         mov     r,addr
                    mov     r,a

                    mov     addr,a          mov     addr,#data
                    mov     addr,r          mov     addr,@r
                    mov     addr1,addr2     mov     bitaddr,c

                    mov     @r,#data        mov     @r,addr
                    mov     @r,a

                    mov     c,bitaddr
                    mov     dptr,#data

                    movc    a,@a+dptr       movc    a,@a+pc
                    movx    a,@dptr         movx    a,@r
                    movx    @dptr,a         movx    @r,a

            D.4.3  Single Operand Instructions

                    clr     a               clr     c
                    clr     bitaddr
                    cpl     a               cpl     c
                    cpl     bitaddr
                    setb    c               setb    bitaddr

                    da      a
                    rr      a               rrc     a
                    rl      a               rlc     a
                    swap    a

                    dec     a               dec     r
                    dec     @r
                    inc     a               inc     r
                    inc     dptr            inc     @r

                    div     ab              mul     ab

                    pop     addr            push    addr

            AS8XCXXX ASSEMBLER                                      PAGE D-5
            DS8XCXXX INSTRUCTION SET

            D.4.4  Two Operand Instructions

                    add     a,#data         add     a,addr
                    add     a,r             add     a,@r
                    addc    a,#data         addc    a,addr
                    addc    a,r             addc    a,@r
                    subb    a,#data         subb    a,addr
                    subb    a,r             subb    a,@r
                    orl     a,#data         orl     a,addr
                    orl     a,r             orl     a,@r
                    orl     addr,a          orl     addr,#data
                    orl     c,bitaddr       orl     c,/bitaddr
                    anl     a,#data         anl     a,addr
                    anl     a,r             anl     a,@r
                    anl     addr,a          anl     addr,#data
                    anl     c,bitaddr       anl     c,/bitaddr
                    xrl     a,#data         xrl     a,addr
                    xrl     a,r             xrl     a,@r
                    xrl     addr,a          xrl     addr,#data
                    xrl     c,bitaddr       xrl     c,/bitaddr
                    xch     a,addr          xch     a,r
                    xch     a,@r            xchd    a,@r

            D.4.5  Call and Return Instructions

                    acall   label           lcall   label
                    ret                     reti
                    in      data
                    out     data
                    rst     data

            D.4.6  Jump Instructions

                    ajmp    label
                    cjne    a,#data,label   cjne    a,addr,label
                    cjne    r,#data,label   cjne    @r,#data,label
                    djnz    r,label         djnz    addr,label
                    jbc     bitadr,label
                    jb      bitadr,label    jnb     bitadr,label
                    jc      label           jnc     label
                    jz      label           jnz     label
                    jmp     @a+dptr
                    ljmp    label           sjmp    label

            AS8XCXXX ASSEMBLER                                      PAGE D-6
            DS8XCXXX INSTRUCTION SET

            D.5  DS8XCXXX SPECIAL FUNCTION REGISTERS

               The  80C32 core Special Function Registers are selected using
            the .DS8xCxxx assembler directive.

            D.5.1  SFR Map

                            --------- 4 Bytes ----------
                            ----    ----    ----    ----
                    80              SP      DPL     DPH         83
                    84                              PCON        87
                    88      TCON    TMOD    TL0     TL1         8B
                    8C      TH0     TH1                         8F
                    90      P1                                  93
                    94                                          97
                    98      SCON    SBUF                        9B
                    9C                                          9F
                    A0      P2                                  A3
                    A4                                          A7
                    A8      IE      SADDR0                      AB
                    AC                                          AF
                    B0      P3                                  B3
                    B4                                          B7
                    B8      IP      SADEN0                      BB
                    BC                                          BF
                    C0                                          C3
                    C4              STATUS                      C7
                    C8      T2CON   T2MOD   RCAP2L  RCAP2H      CB
                    CC      TL2     TH2                         CF
                    D0      PSW                                 D3
                    D4                                          D7
                    D8                                          DB
                    DC                                          DF
                    E0      ACC                                 E3
                    E4                                          E7
                    E8                                          EB
                    EC                                          EF
                    F0      B                                   F3
                    F4                                          F7
                    F8                                          FB
                    FC                                          FF

            AS8XCXXX ASSEMBLER                                      PAGE D-7
            DS8XCXXX SPECIAL FUNCTION REGISTERS

            D.5.2  Bit Addressable Registers:  Generic

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                    80                                          83
                    84                                          87
            TCON    88      TCON.0  TCON.1  TCON.2  TCON.3      8B
                    8C      TCON.4  TCON.5  TCON.6  TCON.7      8F
            P1      90      P1.0    P1.1    P1.2    P1.3        93
                    94      P1.4    P1.5    P1.6    P1.7        97
            SCON    98      SCON.0  SCON.1  SCON.2  SCON.3      9B
                    9C      SCON.4  SCON.5  SCON.6  SCON.7      9F
            P2      A0      P2.0    P2.1    P2.2    P2.3        A3
                    A4      P2.4    P2.5    P2.6    P2.7        A7
            IE      A8      IE.0    IE.1    IE.2    IE.3        AB
                    AC      IE.4    IE.5    EI.6    IE.7        AF
            P3      B0      P3.0    P3.1    P3.2    P3.3        B3
                    B4      P3.4    P3.5    P3.6    P3.7        B7
            IP      B8      IP.0    IP.1    IP.2    IP.3        BB
                    BC      IP.4    IP.5    IP.6    IP.7        BF
                    C0                                          C3
                    C4                                          C7
            T2CON   C8      T2CON.0 T2CON.1 T2CON.2 T2CON.3     CB
                    CC      T2CON.4 T2CON.5 T2CON.6 T2CON.7     CF
            PSW     D0      PSW.0   PSW.1   PSW.2   PSW.3       D3
                    D4      PSW.4   PSW.5   PSW.6   PSW.7       D7
                    D8                                          DB
                    DC                                          DF
            ACC     E0      ACC.0   ACC.1   ACC.2   ACC.3       E3
                    E4      ACC.4   ACC.5   ACC.6   ACC.7       E7
                    E8                                          EB
                    EC                                          EF
            B       F0      B.0     B.1     B.2     B.3         F3
                    F4      B.4     B.5     B.6     B.7         F7
                    F8                                          FB
                    FC                                          FF

            AS8XCXXX ASSEMBLER                                      PAGE D-8
            DS8XCXXX SPECIAL FUNCTION REGISTERS

            D.5.3  Bit Addressable Registers:  Specific

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                    80                                          83
                    84                                          87
            TCON    88      IT0     IE0     IT1     IE1         8B
                    8C      TR0     TF0     TR1     TF1         8F
                    90                                          93
                    94                                          97
            SCON    98      RI      TI      RB8     TB8         9B
                    9C      REN     SM2     SM1     SMO         9F
                    A0                                          A3
                    A4                                          A7
            IE      A8      EX0     ET0     EX1     ET1         AB
                    AC      ES0     ET2             EA          AF
                    B0                                          B3
                    B4                                          B7
            IP      B8      PX0     PT0     PX1     PT1         BB
                    BC      PS0     PT2                         BF
                    C0                                          C3
                    C4                                          C7
            T2CON   C8      CPRL2   CT2     TR2     EXEN2       CB
                    CC      TCLK    RCLK    EXF2    TF2         CF
            PSW     D0      P       FL      OV      RS0         D3
                    D4      RS1     F0      AC      CY          D7
                    D8                                          DB
                    DC                                          DF
                    E0                                          E3
                    E4                                          E7
                    E8                                          EB
                    EC                                          EF
                    F0                                          F3
                    F4                                          F7
                    F8                                          FB
                    FC                                          FF

                    Alternates:

            SCON    98                                          9B
                    9C                              FE          9F
            T2CON   C8      CP_RL2  C_T2                        CB
                    CC                                          CF

            AS8XCXXX ASSEMBLER                                      PAGE D-9
            DS8XCXXX SPECIAL FUNCTION REGISTERS

            D.5.4  Optional Symbols:  Control Bits

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                            0x80    0x40    0x20    0x10
                            0x08    0x04    0x02    0x10
                            ----    ----    ----    ----
            PCON    0x80    SMOD    SMOD0                       0x10
                    0x08    GF1     GF0     STOP    IDLE        0x01
            TMOD    0x80    T1GATE  T1C_T   T1M1    T1M0        0x10
                    0x08    T0GATE  T0C_T   T0M1    T0M0        0x01
            STATUS  0x80            HIP     LIP                 0x10
                    0x08                                        0x01
            T2MOD   0x80                                        0x10
                    0x08                    T2OE    DCEN        0x01

            AS8XCXXX ASSEMBLER                                     PAGE D-10
            DS8XCXXX SPECIAL FUNCTION REGISTERS

            D.6  DS80C310 SPECIAL FUNCTION REGISTERS

               The  DS80C310  Special  Function Registers are selected using
            the .DS80C310 assembler directive.

            D.6.1  SFR Map

                            --------- 4 Bytes ----------
                            ----    ----    ----    ----
                    80              SP      DPL     DPH         83
                    84      DPL1    DPH1    DPS     PCON        87
                    88      TCON    TMOD    TL0     TL1         8B
                    8C      TH0     TH1     CKCON               8F
                    90      P1      EXIF                        93
                    94                                          97
                    98      SCON    SBUF                        9B
                    9C                                          9F
                    A0      P2                                  A3
                    A4                                          A7
                    A8      IE      SADDR0                      AB
                    AC                                          AF
                    B0      P3                                  B3
                    B4                                          B7
                    B8      IP      SADEN0                      BB
                    BC                                          BF
                    C0                                          C3
                    C4              STATUS                      C7
                    C8      T2CON   T2MOD   RCAP2L  RCAP2H      CB
                    CC      TL2     TH2                         CF
                    D0      PSW                                 D3
                    D4                                          D7
                    D8      WDCON                               DB
                    DC                                          DF
                    E0      ACC                                 E3
                    E4                                          E7
                    E8      EIE                                 EB
                    EC                                          EF
                    F0      B                                   F3
                    F4                                          F7
                    F8      EIP                                 FB
                    FC                                          FF

            AS8XCXXX ASSEMBLER                                     PAGE D-11
            DS80C310 SPECIAL FUNCTION REGISTERS

            D.6.2  Bit Addressable Registers:  Generic

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                    80                                          83
                    84                                          87
            TCON    88      TCON.0  TCON.1  TCON.2  TCON.3      8B
                    8C      TCON.4  TCON.5  TCON.6  TCON.7      8F
            P1      90      P1.0    P1.1    P1.2    P1.3        93
                    94      P1.4    P1.5    P1.6    P1.7        97
            SCON    98      SCON.0  SCON.1  SCON.2  SCON.3      9B
                    9C      SCON.4  SCON.5  SCON.6  SCON.7      9F
            P2      A0      P2.0    P2.1    P2.2    P2.3        A3
                    A4      P2.4    P2.5    P2.6    P2.7        A7
            IE      A8      IE.0    IE.1    IE.2    IE.3        AB
                    AC      IE.4    IE.5    EI.6    IE.7        AF
            P3      B0      P3.0    P3.1    P3.2    P3.3        B3
                    B4      P3.4    P3.5    P3.6    P3.7        B7
            IP      B8      IP.0    IP.1    IP.2    IP.3        BB
                    BC      IP.4    IP.5    IP.6    IP.7        BF
                    C0                                          C3
                    C4                                          C7
            T2CON   C8      T2CON.0 T2CON.1 T2CON.2 T2CON.3     CB
                    CC      T2CON.4 T2CON.5 T2CON.6 T2CON.7     CF
            PSW     D0      PSW.0   PSW.1   PSW.2   PSW.3       D3
                    D4      PSW.4   PSW.5   PSW.6   PSW.7       D7
            WDCON   D8      WDCON.0 WDCON.1 WDCON.2 WDCON.3     DB
                    DC      WDCON.4 WDCON.5 WDCON.6 WDCON.7     DF
            ACC     E0      ACC.0   ACC.1   ACC.2   ACC.3       E3
                    E4      ACC.4   ACC.5   ACC.6   ACC.7       E7
            EIE     E8      EIE.0   EIE.1   EIE.2   EIE.3       EB
                    EC      EIE.4   EIE.5   EIE.6   EIE.7       EF
            B       F0      B.0     B.1     B.2     B.3         F3
                    F4      B.4     B.5     B.6     B.7         F7
            EIP     F8      EIP.0   EIP.1   EIP.2   EIP.3       FB
                    FC      EIP.4   EIP.5   EIP.6   EIP.7       FF

            AS8XCXXX ASSEMBLER                                     PAGE D-12
            DS80C310 SPECIAL FUNCTION REGISTERS

            D.6.3  Bit Addressable Registers:  Specific

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                    80                                          83
                    84                                          87
            TCON    88      IT0     IE0     IT1     IE1         8B
                    8C      TR0     TF0     TR1     TF1         8F
                    90                                          93
                    94                                          97
            SCON    98      RI      TI      RB8     TB8         9B
                    9C      REN     SM2     SM1     SMO         9F
                    A0                                          A3
                    A4                                          A7
            IE      A8      EX0     ET0     EX1     ET1         AB
                    AC      ES0     ET2             EA          AF
                    B0                                          B3
                    B4                                          B7
            IP      B8      PX0     PT0     PX1     PT1         BB
                    BC      PS0     PT2                         BF
                    C0                                          C3
                    C4                                          C7
            T2CON   C8      CPRL2   CT2     TR2     EXEN2       CB
                    CC      TCLK    RCLK    EXF2    TF2         CF
            PSW     D0      P       FL      OV      RS0         D3
                    D4      RS1     F0      AC      CY          D7
            WDCON   D8                                          DB
                    DC                      POR                 DF
                    E0                                          E3
                    E4                                          E7
            EIE     E8      EX2     EX3     EX4     EX5         EB
                    EC                                          EF
                    F0                                          F3
                    F4                                          F7
            EIP     F8      PX2     PX3     PX4     PX5         FB
                    FC                                          FF

                    Alternates:

            SCON    98                                          9B
                    9C                              FE          9F
            T2CON   C8      CP_RL2  C_T2                        CB
                    CC                                          CF

            AS8XCXXX ASSEMBLER                                     PAGE D-13
            DS80C310 SPECIAL FUNCTION REGISTERS

            D.6.4  Optional Symbols:  Control Bits

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                            0x80    0x40    0x20    0x10
                            0x08    0x04    0x02    0x10
                            ----    ----    ----    ----
            DPS     0x80                                        0x10
                    0x08                            SEL         0x01
            PCON    0x80    SMOD    SMOD0                       0x10
                    0x08    GF1     GF0     STOP    IDLE        0x01
            TMOD    0x80    T1GATE  T1C_T   T1M1    T1M0        0x10
                    0x08    T0GATE  T0C_T   T0M1    T0M0        0x01
            CKCON   0x80                    T2M     T1M         0x10
                    0x08    T0M     MD2     MD1     MD0         0x01
            EXIF    0x80    IE5     IE4     IE3     IE2         0x10
                    0x08                                        0x01
            STATUS  0x80            HIP     LIP                 0x10
                    0x08                                        0x01
            T2MOD   0x80                                        0x10
                    0x08                    T2OE    DCEN        0x01

                    Alternates:

            PCON    0x80    SMOD_0                              0x10
                    0x08                                        0x01

            AS8XCXXX ASSEMBLER                                     PAGE D-14
            DS80C310 SPECIAL FUNCTION REGISTERS

            D.7  DS80C320/DS80C323 SPECIAL FUNCTION REGISTERS

               The DS80C320/DS80C323 Special Function Registers are selected
            using the .DS80C320 or DS80C323 assembler directives.

            D.7.1  SFR Map

                            --------- 4 Bytes ----------
                            ----    ----    ----    ----
                    80              SP      DPL     DPH         83
                    84      DPL1    DPH1    DPS     PCON        87
                    88      TCON    TMOD    TL0     TL1         8B
                    8C      TH0     TH1     CKCON               8F
                    90      P1      EXIF                        93
                    94                                          97
                    98      SCON0   SBUF0                       9B
                    9C                                          9F
                    A0      P2                                  A3
                    A4                                          A7
                    A8      IE      SADDR0                      AB
                    AC                                          AF
                    B0      P3                                  B3
                    B4                                          B7
                    B8      IP      SADEN0                      BB
                    BC                                          BF
                    C0      SCON1   SBUF1                       C3
                    C4              STATUS          TA          C7
                    C8      T2CON   T2MOD   RCAP2L  RCAP2H      CB
                    CC      TL2     TH2                         CF
                    D0      PSW                                 D3
                    D4                                          D7
                    D8      WDCON                               DB
                    DC                                          DF
                    E0      ACC                                 E3
                    E4                                          E7
                    E8      EIE                                 EB
                    EC                                          EF
                    F0      B                                   F3
                    F4                                          F7
                    F8      EIP                                 FB
                    FC                                          FF

                    Alternates:

                    98      SCON    SBUF                        9B

            AS8XCXXX ASSEMBLER                                     PAGE D-15
            DS80C320/DS80C323 SPECIAL FUNCTION REGISTERS

            D.7.2  Bit Addressable Registers:  Generic

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                    80                                          83
                    84                                          87
            TCON    88      TCON.0  TCON.1  TCON.2  TCON.3      8B
                    8C      TCON.4  TCON.5  TCON.6  TCON.7      8F
            P1      90      P1.0    P1.1    P1.2    P1.3        93
                    94      P1.4    P1.5    P1.6    P1.7        97
            SCON0   98      SCON0.0 SCON0.1 SCON0.2 SCON0.3     9B
                    9C      SCON0.4 SCON0.5 SCON0.6 SCON0.7     9F
            P2      A0      P2.0    P2.1    P2.2    P2.3        A3
                    A4      P2.4    P2.5    P2.6    P2.7        A7
            IE      A8      IE.0    IE.1    IE.2    IE.3        AB
                    AC      IE.4    IE.5    EI.6    IE.7        AF
            P3      B0      P3.0    P3.1    P3.2    P3.3        B3
                    B4      P3.4    P3.5    P3.6    P3.7        B7
            IP      B8      IP.0    IP.1    IP.2    IP.3        BB
                    BC      IP.4    IP.5    IP.6    IP.7        BF
            SCON1   C0      SCON1.0 SCON1.1 SCON1.2 SCON1.3     C3
                    C4      SCON1.4 SCON1.5 SCON1.6 SCON1.7     C7
            T2CON   C8      T2CON.0 T2CON.1 T2CON.2 T2CON.3     CB
                    CC      T2CON.4 T2CON.5 T2CON.6 T2CON.7     CF
            PSW     D0      PSW.0   PSW.1   PSW.2   PSW.3       D3
                    D4      PSW.4   PSW.5   PSW.6   PSW.7       D7
            WDCON   D8      WDCON.0 WDCON.1 WDCON.2 WDCON.3     DB
                    DC      WDCON.4 WDCON.5 WDCON.6 WDCON.7     DF
            ACC     E0      ACC.0   ACC.1   ACC.2   ACC.3       E3
                    E4      ACC.4   ACC.5   ACC.6   ACC.7       E7
            EIE     E8      EIE.0   EIE.1   EIE.2   EIE.3       EB
                    EC      EIE.4   EIE.5   EIE.6   EIE.7       EF
            B       F0      B.0     B.1     B.2     B.3         F3
                    F4      B.4     B.5     B.6     B.7         F7
            EIP     F8      EIP.0   EIP.1   EIP.2   EIP.3       FB
                    FC      EIP.4   EIP.5   EIP.6   EIP.7       FF

                            Alternates:

            SCON    98      SCON.0  SCON.1  SCON.2  SCON.3      9B
                    9C      SCON.4  SCON.5  SCON.6  SCON.7      9F

            AS8XCXXX ASSEMBLER                                     PAGE D-16
            DS80C320/DS80C323 SPECIAL FUNCTION REGISTERS

            D.7.3  Bit Addressable Registers:  Specific

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                    80                                          83
                    84                                          87
            TCON    88      IT0     IE0     IT1     IE1         8B
                    8C      TR0     TF0     TR1     TF1         8F
                    90                                          93
                    94                                          97
            SCON0   98      RI_0    TI_0    RB8_0   TB8_0       9B
                    9C      REN_0   SM2_0   SM1_0   SMO_0       9F
                    A0                                          A3
                    A4                                          A7
            IE      A8      EX0     ET0     EX1     ET1         AB
                    AC      ES0     ET2             EA          AF
                    B0                                          B3
                    B4                                          B7
            IP      B8      PX0     PT0     PX1     PT1         BB
                    BC      PS0     PT2                         BF
            SCON1   C0      RI_1    TI_1    RB8_1   TB8_1       C3
                    C4      REN_1   SM2_1   SM1_1   SMO_1       C7
            T2CON   C8      CPRL2   CT2     TR2     EXEN2       CB
                    CC      TCLK    RCLK    EXF2    TF2         CF
            PSW     D0      P       FL      OV      RS0         D3
                    D4      RS1     F0      AC      CY          D7
            WDCON   D8      RWT     EWT     WTRF    WDIF        DB
                    DC      PFI     EPFI    POR     SMOD_1      DF
                    E0                                          E3
                    E4                                          E7
            EIE     E8      EX2     EX3     EX4     EX5         EB
                    EC      EWDI                                EF
                    F0                                          F3
                    F4                                          F7
            EIP     F8      PX2     PX3     PX4     PX5         FB
                    FC      PWDI                                FF

                    Alternates:

            SCON    98      RI      TI      RB8     TB8         9B
                    9C      REN     SM2     SM1     SMO         9F
            SCON    98                                          9B
                    9C                              FE          9F
            SCON0   98                                          9B
                    9C                              FE_0        9F
            SCON1   C0                                          C3
                    C4                              FE_1        C7
            T2CON   C8      CP_RL2  C_T2                        CB
                    CC                                          CF

            AS8XCXXX ASSEMBLER                                     PAGE D-17
            DS80C320/DS80C323 SPECIAL FUNCTION REGISTERS

            D.7.4  Optional Symbols:  Control Bits

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                            0x80    0x40    0x20    0x10
                            0x08    0x04    0x02    0x10
                            ----    ----    ----    ----
            DPS     0x80                                        0x10
                    0x08                            SEL         0x01
            PCON    0x80    SMOD_0  SMOD0                       0x10
                    0x08    GF1     GF0     STOP    IDLE        0x01
            TMOD    0x80    T1GATE  T1C_T   T1M1    T1M0        0x10
                    0x08    T0GATE  T0C_T   T0M1    T0M0        0x01
            CKCON   0x80    WD1     WD0     T2M     T1M         0x10
                    0x08    T0M     MD2     MD1     MD0         0x01
            EXIF    0x80    IE5     IE4     IE3     IE2         0x10
                    0x08            RGMD    RGSL    BGS         0x01
            STATUS  0x80    PIP     HIP     LIP                 0x10
                    0x08                                        0x01
            T2MOD   0x80                                        0x10
                    0x08                    T2OE    DCEN        0x01

                    Alternates:

            PCON    0x80    SMOD                                0x10
                    0x08                                        0x01

            AS8XCXXX ASSEMBLER                                     PAGE D-18
            DS80C320/DS80C323 SPECIAL FUNCTION REGISTERS

            D.8  DS80C390 SPECIAL FUNCTION REGISTERS

               The  DS80C390  Special  Function Registers are selected using
            the .DS80C390 assembler directive.

            D.8.1  SFR Map

                            --------- 4 Bytes ----------
                            ----    ----    ----    ----
                    80      P4      SP      DPL     DPH         83
                    84      DPL1    DPH1    DPS     PCON        87
                    88      TCON    TMOD    TL0     TL1         8B
                    8C      TH0     TH1     CKCON               8F
                    90      P1      EXIF    P4CNT   DPX         93
                    94              DPX1    C0RMS0  C0RMS1      97
                    98      SCON0   SBUF0           ESP         9B
                    9C      AP      ACON    C0TMA0  C0TMA1      9F
                    A0      P2      P5      P5CNT   C0C         A3
                    A4      C0S     C0IR    C0TE    C0RE        A7
                    A8      IE      SADDR0  SADDR1  C0M1C       AB
                    AC      C0M2C   C0M3C   C0M4C   C0M5C       AF
                    B0      P3                      C0M6C       B3
                    B4      C0M7C   C0M8C   C0M9C   C0M10C      B7
                    B8      IP      SADEN0  SADEN1  C0M11C      BB
                    BC      C0M12C  C0M13C  C0M14C  C0M15C      BF
                    C0      SCON1   SBUF1                       C3
                    C4      PMR     STATUS  MCON    TA          C7
                    C8      T2CON   T2MOD   RCAP2L  RCAP2H      CB
                    CC      TL2     TH2     COR                 CF
                    D0      PSW     MCNT0   MCNT1   MA          D3
                    D4      MB      MC      C1RMS0  C1RMS1      D7
                    D8      WDCON                               DB
                    DC                      C1TMA0  C1TMA1      DF
                    E0      ACC                     C1C         E3
                    E4      C1S     C1IR    C1TE    C1RE        E7
                    E8      EIE             MXAX    C1M1C       EB
                    EC      C1M2C   C1M3C   C1M4C   C1M5C       EF
                    F0      B                       C1M6C       F3
                    F4      C1M7C   C1M8C   C1M9C   C1M10C      F7
                    F8      EIP                     C1M11C      FB
                    FC      C1M12C  C1M13C  C1M14C  C1M15C      FF

                    Alternates:

                    98      SCON    SBUF                        9B

            AS8XCXXX ASSEMBLER                                     PAGE D-19
            DS80C390 SPECIAL FUNCTION REGISTERS

            D.8.2  Bit Addressable Registers:  Generic

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
            P4      80      P4.0    P4.1    P4.2    P4.3        83
                    84      P4.4    P4.5    P4.6    P4.7        87
            TCON    88      TCON.0  TCON.1  TCON.2  TCON.3      8B
                    8C      TCON.4  TCON.5  TCON.6  TCON.7      8F
            P1      90      P1.0    P1.1    P1.2    P1.3        93
                    94      P1.4    P1.5    P1.6    P1.7        97
            SCON0   98      SCON0.0 SCON0.1 SCON0.2 SCON0.3     9B
                    9C      SCON0.4 SCON0.5 SCON0.6 SCON0.7     9F
            P2      A0      P2.0    P2.1    P2.2    P2.3        A3
                    A4      P2.4    P2.5    P2.6    P2.7        A7
            IE      A8      IE.0    IE.1    IE.2    IE.3        AB
                    AC      IE.4    IE.5    EI.6    IE.7        AF
            P3      B0      P3.0    P3.1    P3.2    P3.3        B3
                    B4      P3.4    P3.5    P3.6    P3.7        B7
            IP      B8      IP.0    IP.1    IP.2    IP.3        BB
                    BC      IP.4    IP.5    IP.6    IP.7        BF
            SCON1   C0      SCON1.0 SCON1.1 SCON1.2 SCON1.3     C3
                    C4      SCON1.4 SCON1.5 SCON1.6 SCON1.7     C7
            T2CON   C8      T2CON.0 T2CON.1 T2CON.2 T2CON.3     CB
                    CC      T2CON.4 T2CON.5 T2CON.6 T2CON.7     CF
            PSW     D0      PSW.0   PSW.1   PSW.2   PSW.3       D3
                    D4      PSW.4   PSW.5   PSW.6   PSW.7       D7
            WDCON   D8      WDCON.0 WDCON.1 WDCON.2 WDCON.3     DB
                    DC      WDCON.4 WDCON.5 WDCON.6 WDCON.7     DF
            ACC     E0      ACC.0   ACC.1   ACC.2   ACC.3       E3
                    E4      ACC.4   ACC.5   ACC.6   ACC.7       E7
            EIE     E8      EIE.0   EIE.1   EIE.2   EIE.3       EB
                    EC      EIE.4   EIE.5   EIE.6   EIE.7       EF
            B       F0      B.0     B.1     B.2     B.3         F3
                    F4      B.4     B.5     B.6     B.7         F7
            EIP     F8      EIP.0   EIP.1   EIP.2   EIP.3       FB
                    FC      EIP.4   EIP.5   EIP.6   EIP.7       FF

                            Alternates:

            SCON    98      SCON.0  SCON.1  SCON.2  SCON.3      9B
                    9C      SCON.4  SCON.5  SCON.6  SCON.7      9F

            AS8XCXXX ASSEMBLER                                     PAGE D-20
            DS80C390 SPECIAL FUNCTION REGISTERS

            D.8.3  Bit Addressable Registers:  Specific

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                    80                                          83
                    84                                          87
            TCON    88      IT0     IE0     IT1     IE1         8B
                    8C      TR0     TF0     TR1     TF1         8F
            P1      90      T2      T2EX    RXD1    TXD1        93
                    94      INT2    INT3    INT4    INT5        97
            SCON0   98      RI_0    TI_0    RB8_0   TB8_0       9B
                    9C      REN_0   SM2_0   SM1_0   SMO_0       9F
                    A0                                          A3
                    A4                                          A7
            IE      A8      EX0     ET0     EX1     ET1         AB
                    AC      ES0     ET2     ES1     EA          AF
            P3      B0      RXD0    TXD0    INT0    INT1        B3
                    B4      T0      T1                          B7
            IP      B8      PX0     PT0     PX1     PT1         BB
                    BC      PS0     PT2     PS1                 BF
            SCON1   C0      RI_1    TI_1    RB8_1   TB8_1       C3
                    C4      REN_1   SM2_1   SM1_1   SMO_1       C7
            T2CON   C8      CPRL2   CT2     TR2     EXEN2       CB
                    CC      TCLK    RCLK    EXF2    TF2         CF
            PSW     D0      P       FL      OV      RS0         D3
                    D4      RS1     F0      AC      CY          D7
            WDCON   D8      RWT     EWT     WTRF    WDIF        DB
                    DC      PFI     EPFI    POR     SMOD_1      DF
                    E0                                          E3
                    E4                                          E7
            EIE     E8      EX2     EX3     EX4     EX5         EB
                    EC      EWDI    C1IE    C0IE    CANBIE      EF
                    F0                                          F3
                    F4                                          F7
            EIP     F8      PX2     PX3     PX4     PX5         FB
                    FC      PWDI    C1IP    C0IP    CANBIP      FF

                    Alternates:

            SCON    98      RI      TI      RB8     TB8         9B
                    9C      REN     SM2     SM1     SMO         9F
            SCON    98                                          9B
                    9C                              FE          9F
            SCON0   98                                          9B
                    9C                              FE_0        9F
            SCON1   C0                                          C3
                    C4                              FE_1        C7
            T2CON   C8      CP_RL2  C_T2                        CB
                    CC                                          CF

            AS8XCXXX ASSEMBLER                                     PAGE D-21
            DS80C390 SPECIAL FUNCTION REGISTERS

            D.8.4  Optional Symbols:  Control Bits

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                            0x80    0x40    0x20    0x10
                            0x08    0x04    0x02    0x10
                            ----    ----    ----    ----
            DPS     0x80    ID1     ID0     TSL                 0x10
                    0x08                            SEL         0x01
            PCON    0x80    SMOD_0  SMOD0   OFDF    OFDE        0x10
                    0x08    GF1     GF0     STOP    IDLE        0x01
            TMOD    0x80    T1GATE  T1C_T   T1M1    T1M0        0x10
                    0x08    T0GATE  T0C_T   T0M1    T0M0        0x01
            CKCON   0x80    WD1     WD0     T2M     T1M         0x10
                    0x08    T0M     MD2     MD1     MD0         0x01
            EXIF    0x80    IE5     IE4     IE3     IE2         0x10
                    0x08    CKRY    RGMD    RGSL    BGS         0x01
            P4CNT   0x80            SBCAN                       0x10
                    0x08                                        0x01
            ESP     0x80                                        0x10
                    0x08                    ESP.1   ESP.0       0x01
            ACON    0x80                                        0x10
                    0x08            SA      AM1     AM0         0x01
            P5      0x80    P5.7    P5.6    P5.5    P5.4        0x10
                    0x08    P5.3    P5.2    P5.1    P5.0        0x01
            P5CNT   0x80    CAN1BA  CAN0BA  SP1EC   C1_IO       0x10
                    0x08    C0_IO   P5CNT.2 P5CNT.1 P5CNT.0     0x01
            CxC     0x80    ERIE    STIE    PDE     SIESTA      0x10
                    0x08    CRST    AUTOB   ERCS    SWINT       0x01
            CxS     0x80    BSS   EC96_128  WKS     RXS         0x10
                    0x08    TXS     ER2     ER1     ER0         0x01
            CxIR    0x80    INTIN7  INTIN6  INTIN5  INTIN4      0x10
                    0x08    INTIN3  INTIN2  INTIN1  INTIN0      0x01
            CxCxxC  0x80    MSRDY   ET1     ER1     INTRQ       0x10
                    0x08    EXTRQ   MTRQ    ROW_TIH DTUP        0x01
            PMR     0x80    CD1     CD0     SWB     CTM         0x10
                    0x08    4X_2X   ALEOFF                      0x01
            STATUS  0x80    PIP     HIP     LIP                 0x10
                    0x08    SPTA1   SPRA1   SPTA0   SPRA0       0x01
            MCON    0x80    IDM1    IDM0    CMA                 0x10
                    0x08    PDCE3   PDCE2   PDCE1   PDCE0       0x01
            T2MOD   0x80                            D13T1       0x10
                    0x08    D13T2           T2OE    DCEN        0x01
            COR     0x80    IRDACK  C1BPR7  C1BPR6  C0BPR7      0x10
                    0x08    C0BPR6  COD1    COD0    CLKOE       0x01
            MCNT0   0x80    _LSHIFT CSE     SCB     MAS4        0x10
                    0x08    MAS3    MAS2    MAS1    MAS0        0x01
            MCNT1   0x80    MST     MOF             CLM         0x10
                    0x08                                        0x01

                    Alternates:

            AS8XCXXX ASSEMBLER                                     PAGE D-22
            DS80C390 SPECIAL FUNCTION REGISTERS

            PCON    0x80    SMOD                                0x10
                    0x08                                        0x01

            AS8XCXXX ASSEMBLER                                     PAGE D-23
            DS80C390 SPECIAL FUNCTION REGISTERS

            D.9  DS83C520/DS87C520 SPECIAL FUNCTION REGISTERS

               The DS83C520/DS87C520 Special Function Registers are selected
            using the .DS83C520 or DS87C520 assembler directives.

            D.9.1  SFR Map

                            --------- 4 Bytes ----------
                            ----    ----    ----    ----
                    80      P0      SP      DPL     DPH         83
                    84      DPL1    DPH1    DPS     PCON        87
                    88      TCON    TMOD    TL0     TL1         8B
                    8C      TH0     TH1     CKCON               8F
                    90      PORT1   EXIF                        93
                    94                                          97
                    98      SCON0   SBUF0                       9B
                    9C                                          9F
                    A0      P2                                  A3
                    A4                                          A7
                    A8      IE      SADDR0  SADDR1              AB
                    AC                                          AF
                    B0      P3                                  B3
                    B4                                          B7
                    B8      IP      SADEN0  SADEN1              BB
                    BC                                          BF
                    C0      SCON1   SBUF1   ROMSIZE             C3
                    C4      PMR     STATUS          TA          C7
                    C8      T2CON   T2MOD   RCAP2L  RCAP2H      CB
                    CC      TL2     TH2                         CF
                    D0      PSW                                 D3
                    D4                                          D7
                    D8      WDCON                               DB
                    DC                                          DF
                    E0      ACC                                 E3
                    E4                                          E7
                    E8      EIE                                 EB
                    EC                                          EF
                    F0      B                                   F3
                    F4                                          F7
                    F8      EIP                                 FB
                    FC                                          FF

                    Alternates:

                    98      SCON    SBUF                        9B

            AS8XCXXX ASSEMBLER                                     PAGE D-24
            DS83C520/DS87C520 SPECIAL FUNCTION REGISTERS

            D.9.2  Bit Addressable Registers:  Generic

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
            P0      80      P0.7    P0.6    P0.5    P0.4        83
                    84      P0.3    P0.2    P0.1    P0.0        87
            TCON    88      TCON.0  TCON.1  TCON.2  TCON.3      8B
                    8C      TCON.4  TCON.5  TCON.6  TCON.7      8F
            PORT1   90      P1.0    P1.1    P1.2    P1.3        93
                    94      P1.4    P1.5    P1.6    P1.7        97
            SCON0   98      SCON0.0 SCON0.1 SCON0.2 SCON0.3     9B
                    9C      SCON0.4 SCON0.5 SCON0.6 SCON0.7     9F
            P2      A0      P2.0    P2.1    P2.2    P2.3        A3
                    A4      P2.4    P2.5    P2.6    P2.7        A7
            IE      A8      IE.0    IE.1    IE.2    IE.3        AB
                    AC      IE.4    IE.5    EI.6    IE.7        AF
            P3      B0      P3.0    P3.1    P3.2    P3.3        B3
                    B4      P3.4    P3.5    P3.6    P3.7        B7
            IP      B8      IP.0    IP.1    IP.2    IP.3        BB
                    BC      IP.4    IP.5    IP.6    IP.7        BF
            SCON1   C0      SCON1.0 SCON1.1 SCON1.2 SCON1.3     C3
                    C4      SCON1.4 SCON1.5 SCON1.6 SCON1.7     C7
            T2CON   C8      T2CON.0 T2CON.1 T2CON.2 T2CON.3     CB
                    CC      T2CON.4 T2CON.5 T2CON.6 T2CON.7     CF
            PSW     D0      PSW.0   PSW.1   PSW.2   PSW.3       D3
                    D4      PSW.4   PSW.5   PSW.6   PSW.7       D7
            WDCON   D8      WDCON.0 WDCON.1 WDCON.2 WDCON.3     DB
                    DC      WDCON.4 WDCON.5 WDCON.6 WDCON.7     DF
            ACC     E0      ACC.0   ACC.1   ACC.2   ACC.3       E3
                    E4      ACC.4   ACC.5   ACC.6   ACC.7       E7
            EIE     E8      EIE.0   EIE.1   EIE.2   EIE.3       EB
                    EC      EIE.4   EIE.5   EIE.6   EIE.7       EF
            B       F0      B.0     B.1     B.2     B.3         F3
                    F4      B.4     B.5     B.6     B.7         F7
            EIP     F8      EIP.0   EIP.1   EIP.2   EIP.3       FB
                    FC      EIP.4   EIP.5   EIP.6   EIP.7       FF

                            Alternates:

            PORT1   90      PORT1.0 PORT1.1 PORT1.2 PORT1.3     93
                    94      PORT1.4 PORT1.5 PORT1.6 PORT1.7     97
            SCON    98      SCON.0  SCON.1  SCON.2  SCON.3      9B
                    9C      SCON.4  SCON.5  SCON.6  SCON.7      9F

            AS8XCXXX ASSEMBLER                                     PAGE D-25
            DS83C520/DS87C520 SPECIAL FUNCTION REGISTERS

            D.9.3  Bit Addressable Registers:  Specific

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                    80                                          83
                    84                                          87
            TCON    88      IT0     IE0     IT1     IE1         8B
                    8C      TR0     TF0     TR1     TF1         8F
                    90                                          93
                    94                                          97
            SCON0   98      RI_0    TI_0    RB8_0   TB8_0       9B
                    9C      REN_0   SM2_0   SM1_0   SMO_0       9F
                    A0                                          A3
                    A4                                          A7
            IE      A8      EX0     ET0     EX1     ET1         AB
                    AC      ES0     ET2     ES1     EA          AF
                    B0                                          B3
                    B4                                          B7
            IP      B8      PX0     PT0     PX1     PT1         BB
                    BC      PS0     PT2     PS1                 BF
            SCON1   C0      RI_1    TI_1    RB8_1   TB8_1       C3
                    C4      REN_1   SM2_1   SM1_1   SMO_1       C7
            T2CON   C8      CPRL2   CT2     TR2     EXEN2       CB
                    CC      TCLK    RCLK    EXF2    TF2         CF
            PSW     D0      P       FL      OV      RS0         D3
                    D4      RS1     F0      AC      CY          D7
            WDCON   D8      RWT     EWT     WTRF    WDIF        DB
                    DC      PFI     EPFI    POR     SMOD_1      DF
                    E0                                          E3
                    E4                                          E7
            EIE     E8      EX2     EX3     EX4     EX5         EB
                    EC      EWDI                                EF
                    F0                                          F3
                    F4                                          F7
            EIP     F8      PX2     PX3     PX4     PX5         FB
                    FC      PWDI                                FF

                    Alternates:

            SCON    98      RI      TI      RB8     TB8         9B
                    9C      REN     SM2     SM1     SMO         9F
            SCON    98                                          9B
                    9C                              FE          9F
            SCON0   98                                          9B
                    9C                              FE_0        9F
            SCON1   C0                                          C3
                    C4                              FE_1        C7
            T2CON   C8      CP_RL2  C_T2                        CB
                    CC                                          CF

            AS8XCXXX ASSEMBLER                                     PAGE D-26
            DS83C520/DS87C520 SPECIAL FUNCTION REGISTERS

            D.9.4  Optional Symbols:  Control Bits

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                            0x80    0x40    0x20    0x10
                            0x08    0x04    0x02    0x10
                            ----    ----    ----    ----
            DPS     0x80                                        0x10
                    0x08                            SEL         0x01
            PCON    0x80    SMOD_0  SMOD0                       0x10
                    0x08    GF1     GF0     STOP    IDLE        0x01
            TMOD    0x80    T1GATE  T1C_T   T1M1    T1M0        0x10
                    0x08    T0GATE  T0C_T   T0M1    T0M0        0x01
            CKCON   0x80    WD1     WD0     T2M     T1M         0x10
                    0x08    T0M     MD2     MD1     MD0         0x01
            EXIF    0x80    IE5     IE4     IE3     IE          0x10
                    0x08    XT_RG   RGMD    RGSL    BGS         0x01
            SBUF1   0x80    SB7     SB6     SB5     SB4         0x10
                    0x08    SB3     SB2     SB1     SB0         0x01
            ROMSIZE 0x80                                        0x10
                    0x08            RMS2    RMS1    RMS0        0x01
            PMR     0x80    CD1     CD0     SWB                 0x10
                    0x08    XTOFF   ALEOFF  DME1    DME0        0x01
            STATUS  0x80    PIP     HIP     LIP     XTUP        0x10
                    0x08    SPTA1   SPRA1   SPTA0   SPRA0       0x01
            T2MOD   0x80                                        0x10
                    0x08                    T2OE    DCEN        0x01

                    Alternates:

            PCON    0x80    SMOD                                0x10
                    0x08                                        0x01

            AS8XCXXX ASSEMBLER                                     PAGE D-27
            DS83C520/DS87C520 SPECIAL FUNCTION REGISTERS

            D.10  DS83C530/DS87C530 SPECIAL FUNCTION REGISTERS

               The DS83C530/DS87C530 Special Function Registers are selected
            using the .DS83C530 or DS87C530 assembler directives.

            D.10.1  SFR Map

                            --------- 4 Bytes ----------
                            ----    ----    ----    ----
                    80      P0      SP      DPL     DPH         83
                    84      DPL1    DPH1    DPS     PCON        87
                    88      TCON    TMOD    TL0     TL1         8B
                    8C      TH0     TH1     CKCON               8F
                    90      P1      EXIF                        93
                    94                      TRIM                97
                    98      SCON0   SBUF0                       9B
                    9C                                          9F
                    A0      P2                                  A3
                    A4                                          A7
                    A8      IE      SADDR0  SADDR1              AB
                    AC                                          AF
                    B0      P3                                  B3
                    B4                                          B7
                    B8      IP      SADEN0  SADEN1              BB
                    BC                                          BF
                    C0      SCON1   SBUF1   ROMSIZE             C3
                    C4      PMR     STATUS          TA          C7
                    C8      T2CON   T2MOD   RCAP2L  RCAP2H      CB
                    CC      TL2     TH2                         CF
                    D0      PSW                                 D3
                    D4                                          D7
                    D8      WDCON                               DB
                    DC                                          DF
                    E0      ACC                                 E3
                    E4                                          E7
                    E8      EIE                                 EB
                    EC                                          EF
                    F0      B               RTASS   RTAS        F3
                    F4      RTAM    RTAH                        F7
                    F8      EIP     RTCC    RTCSS   RTCS        FB
                    FC      RTCM    RTCH    RTCD0   RTCD1       FF

                    Alternates:

                    98      SCON    SBUF                        9B

            AS8XCXXX ASSEMBLER                                     PAGE D-28
            DS83C530/DS87C530 SPECIAL FUNCTION REGISTERS

            D.10.2  Bit Addressable Registers:  Generic

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
            P0      80      P0.7    P0.6    P0.5    P0.4        83
                    84      P0.3    P0.2    P0.1    P0.0        87
            TCON    88      TCON.0  TCON.1  TCON.2  TCON.3      8B
                    8C      TCON.4  TCON.5  TCON.6  TCON.7      8F
            P1      90      P1.0    P1.1    P1.2    P1.3        93
                    94      P1.4    P1.5    P1.6    P1.7        97
            SCON0   98      SCON0.0 SCON0.1 SCON0.2 SCON0.3     9B
                    9C      SCON0.4 SCON0.5 SCON0.6 SCON0.7     9F
            P2      A0      P2.0    P2.1    P2.2    P2.3        A3
                    A4      P2.4    P2.5    P2.6    P2.7        A7
            IE      A8      IE.0    IE.1    IE.2    IE.3        AB
                    AC      IE.4    IE.5    EI.6    IE.7        AF
            P3      B0      P3.0    P3.1    P3.2    P3.3        B3
                    B4      P3.4    P3.5    P3.6    P3.7        B7
            IP      B8      IP.0    IP.1    IP.2    IP.3        BB
                    BC      IP.4    IP.5    IP.6    IP.7        BF
            SCON1   C0      SCON1.0 SCON1.1 SCON1.2 SCON1.3     C3
                    C4      SCON1.4 SCON1.5 SCON1.6 SCON1.7     C7
            T2CON   C8      T2CON.0 T2CON.1 T2CON.2 T2CON.3     CB
                    CC      T2CON.4 T2CON.5 T2CON.6 T2CON.7     CF
            PSW     D0      PSW.0   PSW.1   PSW.2   PSW.3       D3
                    D4      PSW.4   PSW.5   PSW.6   PSW.7       D7
            WDCON   D8      WDCON.0 WDCON.1 WDCON.2 WDCON.3     DB
                    DC      WDCON.4 WDCON.5 WDCON.6 WDCON.7     DF
            ACC     E0      ACC.0   ACC.1   ACC.2   ACC.3       E3
                    E4      ACC.4   ACC.5   ACC.6   ACC.7       E7
            EIE     E8      EIE.0   EIE.1   EIE.2   EIE.3       EB
                    EC      EIE.4   EIE.5   EIE.6   EIE.7       EF
            B       F0      B.0     B.1     B.2     B.3         F3
                    F4      B.4     B.5     B.6     B.7         F7
            EIP     F8      EIP.0   EIP.1   EIP.2   EIP.3       FB
                    FC      EIP.4   EIP.5   EIP.6   EIP.7       FF

                            Alternates:

            SCON    98      SCON.0  SCON.1  SCON.2  SCON.3      9B
                    9C      SCON.4  SCON.5  SCON.6  SCON.7      9F

            AS8XCXXX ASSEMBLER                                     PAGE D-29
            DS83C530/DS87C530 SPECIAL FUNCTION REGISTERS

            D.10.3  Bit Addressable Registers:  Specific

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                    80                                          83
                    84                                          87
            TCON    88      IT0     IE0     IT1     IE1         8B
                    8C      TR0     TF0     TR1     TF1         8F
                    90                                          93
                    94                                          97
            SCON0   98      RI_0    TI_0    RB8_0   TB8_0       9B
                    9C      REN_0   SM2_0   SM1_0   SMO_0       9F
                    A0                                          A3
                    A4                                          A7
            IE      A8      EX0     ET0     EX1     ET1         AB
                    AC      ES0     ET2     ES1     EA          AF
                    B0                                          B3
                    B4                                          B7
            IP      B8      PX0     PT0     PX1     PT1         BB
                    BC      PS0     PT2     PS1                 BF
            SCON1   C0      RI_1    TI_1    RB8_1   TB8_1       C3
                    C4      REN_1   SM2_1   SM1_1   SMO_1       C7
            T2CON   C8      CPRL2   CT2     TR2     EXEN2       CB
                    CC      TCLK    RCLK    EXF2    TF2         CF
            PSW     D0      P       FL      OV      RS0         D3
                    D4      RS1     F0      AC      CY          D7
            WDCON   D8      RWT     EWT     WTRF    WDIF        DB
                    DC      PFI     EPFI    POR     SMOD_1      DF
                    E0                                          E3
                    E4                                          E7
            EIE     E8      EX2     EX3     EX4     EX5         EB
                    EC      EWDI    ERTCI                       EF
                    F0                                          F3
                    F4                                          F7
            EIP     F8      PX2     PX3     PX4     PX5         FB
                    FC      PWDI    PRTCI                       FF

                    Alternates:

            SCON    98      RI      TI      RB8     TB8         9B
                    9C      REN     SM2     SM1     SMO         9F
            SCON    98                                          9B
                    9C                              FE          9F
            SCON0   98                                          9B
                    9C                              FE_0        9F
            SCON1   C0                                          C3
                    C4                              FE_1        C7
            T2CON   C8      CP_RL2  C_T2                        CB
                    CC                                          CF

            AS8XCXXX ASSEMBLER                                     PAGE D-30
            DS83C530/DS87C530 SPECIAL FUNCTION REGISTERS

            D.10.4  Optional Symbols:  Control Bits

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                            0x80    0x40    0x20    0x10
                            0x08    0x04    0x02    0x10
                            ----    ----    ----    ----
            DPS     0x80                                        0x10
                    0x08                            SEL         0x01
            PCON    0x80    SMOD_0  SMOD0                       0x10
                    0x08    GF1     GF0     STOP    IDLE        0x01
            TMOD    0x80    T1GATE  T1C_T   T1M1    T1M0        0x10
                    0x08    T0GATE  T0C_T   T0M1    T0M0        0x01
            CKCON   0x80    WD1     WD0     T2M     T1M         0x10
                    0x08    T0M     MD2     MD1     MD0         0x01
            EXIF    0x80    IE5     IE4     IE3     IE          0x10
                    0x08    XT_RG   RGMD    RGSL    BGS         0x01
            TRIM    0x80    E4K     X12_6   TRM2    _TRM2       0x10
                    0x08    TRM1    _TRM1   TRM0    _TRM0       0x01
            SBUF1   0x80    SB7     SB6     SB5     SB4         0x10
                    0x08    SB3     SB2     SB1     SB0         0x01
            ROMSIZE 0x80                                        0x10
                    0x08            RMS2    RMS1    RMS0        0x01
            PMR     0x80    CD1     CD0     SWB                 0x10
                    0x08    XTOFF   ALEOFF  DME1    DME0        0x01
            STATUS  0x80    PIP     HIP     LIP     XTUP        0x10
                    0x08    SPTA1   SPRA1   SPTA0   SPRA0       0x01
            T2MOD   0x80                                        0x10
                    0x08                    T2OE    DCEN        0x01
            RTCC    0x80    SSCE    SCE     MCE     HCE         0x10
                    0x08    RTCRE   RTCWE   RTCIF   RTCE        0x01

                    Alternates:

            PCON    0x80    SMOD                                0x10
                    0x08                                        0x01

            AS8XCXXX ASSEMBLER                                     PAGE D-31
            DS83C530/DS87C530 SPECIAL FUNCTION REGISTERS

            D.11  DS83C550/DS87C550 SPECIAL FUNCTION REGISTERS

               The DS83C550/DS87C550 Special Function Registers are selected
            using the .DS83C550 or DS87C550 assembler directives.

            D.11.1  SFR Map

                            --------- 4 Bytes ----------
                            ----    ----    ----    ----
                    80      PORT0   SP      DPL     DPH         83
                    84      DPL1    DPH1    DPS     PCON        87
                    88      TCON    TMOD    TL0     TL1         8B
                    8C      TH0     TH1     CKCON               8F
                    90      PORT1   RCON                        93
                    94                                          97
                    98      SCON0   SBUF0                       9B
                    9C                              PMR         9F
                    A0      PORT2   SADDR0  SADDR1              A3
                    A4                                          A7
                    A8      IE      CMPL0   CMPL1   CMPL2       AB
                    AC      CPTL0   CPTL1   CPTL2   CPTL3       AF
                    B0      PORT3           ADCON1  ADCON2      B3
                    B4      ADMSB   ADLSD   WINHI   WINLO       B7
                    B8      IP      SADEN0  SADEN1              BB
                    BC                      T2CON   T2MOD       BF
                    C0      PORT4           ROMSIZE             C3
                    C4      PORT5   STATUS          TA          C7
                    C8      T2IR    CMPH0   CMPH1   CMPH2       CB
                    CC      CPTH0   CPTH1   CPTH2   CPTH3       CF
                    D0      PSW             PW0FG   PW1FG       D3
                    D4      PW2FG   PW3FG   PWMADR              D7
                    D8      SCON1   SBUF1                       DB
                    DC      PWM0    PWM1    PWM2    PWM3        DF
                    E0      ACC     PW01CS  PW23CS  PW01CON     E3
                    E4      PW23CON         RLOADL  RLOADH      E7
                    E8      EIE             T2SEL   CTCON       EB
                    EC      TL2     TH2     SETR    RSTR        EF
                    F0      B       PORT6                       F3
                    F4                                          F7
                    F8      EIP                                 FB
                    FC                              WDCON       FF

                    Alternates:

                    80      P0                                  83
                    90      P1                                  93
                    98      SCON    SBUF                        9B
                    A0      P2                                  A3
                    B0      P3                                  B3
                    C0      P4                                  C3

            AS8XCXXX ASSEMBLER                                     PAGE D-32
            DS83C550/DS87C550 SPECIAL FUNCTION REGISTERS

                    C4      P5                                  C7
                    F0              PORT6                       F3

            AS8XCXXX ASSEMBLER                                     PAGE D-33
            DS83C550/DS87C550 SPECIAL FUNCTION REGISTERS

            D.11.2  Bit Addressable Registers:  Generic

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
            PORT0   80      P0.7    P0.6    P0.5    P0.4        83
                    84      P0.3    P0.2    P0.1    P0.0        87
            TCON    88      TCON.0  TCON.1  TCON.2  TCON.3      8B
                    8C      TCON.4  TCON.5  TCON.6  TCON.7      8F
            PORT1   90      P1.0    P1.1    P1.2    P1.3        93
                    94      P1.4    P1.5    P1.6    P1.7        97
            SCON0   98      SCON0.0 SCON0.1 SCON0.2 SCON0.3     9B
                    9C      SCON0.4 SCON0.5 SCON0.6 SCON0.7     9F
            PORT2   A0      P2.0    P2.1    P2.2    P2.3        A3
                    A4      P2.4    P2.5    P2.6    P2.7        A7
            IE      A8      IE.0    IE.1    IE.2    IE.3        AB
                    AC      IE.4    IE.5    EI.6    IE.7        AF
            PORT3   B0      P3.0    P3.1    P3.2    P3.3        B3
                    B4      P3.4    P3.5    P3.6    P3.7        B7
            IP      B8      IP.0    IP.1    IP.2    IP.3        BB
                    BC      IP.4    IP.5    IP.6    IP.7        BF
            PORT4   C0      P4.0    P4.1    P4.2    P4.3        C3
                    C4      P4.4    P4.5    P4.6    P4.7        C7
            T2IR    C8      T2IR.0  T2IR.1  T2IR.2  T2IR.3      CB
                    CC      T2IR.4  T2IR.5  T2IR.6  T2IR.7      CF
            PSW     D0      PSW.0   PSW.1   PSW.2   PSW.3       D3
                    D4      PSW.4   PSW.5   PSW.6   PSW.7       D7
            SCON1   D8      SCON1.0 SCON1.1 SCON1.2 SCON1.3     DB
                    DC      SCON1.4 SCON1.5 SCON1.6 SCON1.7     DF
            ACC     E0      ACC.0   ACC.1   ACC.2   ACC.3       E3
                    E4      ACC.4   ACC.5   ACC.6   ACC.7       E7
            EIE     E8      EIE.0   EIE.1   EIE.2   EIE.3       EB
                    EC      EIE.4   EIE.5   EIE.6   EIE.7       EF
            B       F0      B.0     B.1     B.2     B.3         F3
                    F4      B.4     B.5     B.6     B.7         F7
            EIP     F8      EIP.0   EIP.1   EIP.2   EIP.3       FB
                    FC      EIP.4   EIP.5   EIP.6   EIP.7       FF

                            Alternates:

            PORT0   80      PORT0.7 PORT0.6 PORT0.5 PORT0.4     83
                    84      PORT0.3 PORT0.2 PORT0.1 PORT0.0     87
            PORT1   90      PORT1.0 PORT1.1 PORT1.2 PORT1.3     93
                    94      PORT1.4 PORT1.5 PORT1.6 PORT1.7     97
            SCON    98      SCON.0  SCON.1  SCON.2  SCON.3      9B
                    9C      SCON.4  SCON.5  SCON.6  SCON.7      9F
            PORT2   A0      PORT2.0 PORT2.1 PORT2.2 PORT2.3     A3
                    A4      PORT2.4 PORT2.5 PORT2.6 PORT2.7     A7
            PORT3   B0      PORT3.0 PORT3.1 PORT3.2 PORT3.3     B3
                    B4      PORT3.4 PORT3.5 PORT3.6 PORT3.7     B7
            PORT4   C0      PORT4.0 PORT4.1 PORT4.2 PORT4.3     C3
                    C4      PORT4.4 PORT4.5 PORT4.6 PORT4.7     C7

            AS8XCXXX ASSEMBLER                                     PAGE D-34
            DS83C550/DS87C550 SPECIAL FUNCTION REGISTERS

            D.11.3  Bit Addressable Registers:  Specific

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                    80                                          83
                    84                                          87
            TCON    88      IT0     IE0     IT1     IE1         8B
                    8C      TR0     TF0     TR1     TF1         8F
                    90                                          93
                    94                                          97
            SCON0   98      RI_0    TI_0    RB8_0   TB8_0       9B
                    9C      REN_0   SM2_0   SM1_0   SMO_0       9F
                    A0                                          A3
                    A4                                          A7
            IE      A8      EX0     ET0     EX1     ET1         AB
                    AC      ES0     ET2     ES1     EA          AF
                    B0                                          B3
                    B4                                          B7
            IP      B8      PX0     PT0     PX1     PT1         BB
                    BC      PS0     PS1     PAD                 BF
            PORT4   C0      CMSR0   CMSR1   CMSR2   CMSR3       C3
                    C4      CMSR4   CMSR5   CMT0    CMT1        C7
            T2IR    C8      CF0     CF1     CF2     CF3         CB
                    CC      CM0F    CM1F    CM2F                CF
            PSW     D0      P       FL      OV      RS0         D3
                    D4      RS1     F0      AC      CY          D7
            SCON1   D8      RI_1    TI_1    RB8_1   TB8_1       DB
                    DC      REN_1   SM2_1   SM1_1   SMO_1       DF
                    E0                                          E3
                    E4                                          E7
            EIE     E8      EX2     EX3     EX4     EX5         EB
                    EC      ECM0    ECM1    ECM2    ET2         EF
                    F0                                          F3
                    F4                                          F7
            EIP     F8      PX2     PX3     PX4     PX5         FB
                    FC      PCM0    PCM1    PCM2    PT2         FF

                    Alternates:

            SCON    98      RI      TI      RB8     TB8         9B
                    9C      REN     SM2     SM1     SMO         9F
            SCON    98                                          9B
                    9C                              FE          9F
            SCON0   98                                          9B
                    9C                              FE_0        9F
            T2IR    C8      IE2     IE3     IE4     IE5         CB
                    CC                                          CF
            SCON1   D8                                          DB
                    DC                              FE_1        DF
            EIE     E8      EC0     EC1     EC2     EC3         EB
                    EC                                          EF
            EIP     F8      PC0     PC1     PC2     PC3         FB

            AS8XCXXX ASSEMBLER                                     PAGE D-35
            DS83C550/DS87C550 SPECIAL FUNCTION REGISTERS

                    FC                                          FF

            AS8XCXXX ASSEMBLER                                     PAGE D-36
            DS83C550/DS87C550 SPECIAL FUNCTION REGISTERS

            D.11.4  Optional Symbols:  Control Bits

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                            0x80    0x40    0x20    0x10
                            0x08    0x04    0x02    0x10
                            ----    ----    ----    ----
            DPS     0x80    ID1     ID0     TSL                 0x10
                    0x08                            SEL         0x01
            PCON    0x80    SMOD_0  SMOD0                       0x10
                    0x08    GF1     GF0     STOP    IDLE        0x01
            TMOD    0x80    T1GATE  T1C_T   T1M1    T1M0        0x10
                    0x08    T0GATE  T0C_T   T0M1    T0M0        0x01
            CKCON   0x80    WD1     WD0     T2M     T1M         0x10
                    0x08    T0M     MD2     MD1     MD0         0x01
            RCON    0x80                                        0x10
                    0x08    CKRDY   RGMD    RGSL    BGS         0x01
            PMR     0x80    CD1     CD0     SWB     CTM         0x10
                    0x08    4X_2X   ALEOFF  DEM1    DEM0        0x01
            ADCON1  0x80   STRT_BSY EOC     CONT_SS ADEX        0x10
                    0x08    WCQ     WCM     ADON    WCIO        0x01
            ADCON2  0x80    OUTCF   MUX2    MUX1    MUX0        0x10
                    0x08    APS3    APS2    APS1    APS0        0x01
            T2CON   0x80    TF2     EXF2    RCLK    TCLK        0x10
                    0x08    EXEN2   TR2     CT2     CPRL2       0x01
            T2MOD   0x80                                        0x10
                    0x08                    T2OE    DCEN        0x01
            PORT5   0x80    ADC7    ADC6    ADC5    ADC4        0x10
                    0x08    ADC3    ADC2    ADC1    ADC0        0x01
            ROMSIZE 0x80                                        0x10
                    0x08            RMS2    RMS1    RMS0        0x01
            STATUS  0x80    PIP     HIP     LIP     XTUP        0x10
                    0x08    SPTA1   SPRA1   SPTA0   SPRA0       0x01
            PWMADR  0x80    ADRS                                0x10
                    0x08                    PWE1    PWE0        0x01
            PW01CS  0x80    PW0S2   PW0S1   PW0S0   PW0EN       0x10
                    0x08    PW1S2   PW1S1   PW1S0   PW1EN       0x01
            PW23CS  0x80    PW2S2   PW2S1   PW2S0   PW2EN       0x10
                    0x08    PW3S2   PW3S1   PW3S0   PW3EN       0x01
            PW01CON 0x80    PW0F    PW0DC   PW0OE   PW0T_C      0x10
                    0x08    PW1F    PW1DC   PW1OE   PW1T_C      0x01
            PW23CON 0x80    PW2F    PW2DC   PW2OE   PW2T_C      0x10
                    0x08    PW3F    PW3DC   PW3OE   PW3T_C      0x01
            T2SEL   0x80    TF2S    TF2BS           TF2B        0x10
                    0x08                    T2P1    T2P0        0x01
            CTCON   0x80    _CT3    CT3     _CT2    CT2         0x10
                    0x08    _CT1    CT1     _CT0    CT0         0x01
            SETR    0x80    TGFF1   TGFF0   CMS5    CMS4       0x10
                    0x08    CMS3    CMS2    CMS1    CMS0        0x01
            RSTR    0x80    CMTE1   CMTE0   CMR5    CMR4        0x10
                    0x08    CMR3    CMR2    CMR1    CMR0        0x01
            PORT6   0x80    STADC           PWMC1   PWMC0       0x10

            AS8XCXXX ASSEMBLER                                     PAGE D-37
            DS83C550/DS87C550 SPECIAL FUNCTION REGISTERS

                    0x08    PWMO3   PWMO2   PWMO1   PWMO0       0x01
            WDCON   0x80    SMOD_1  POR     EPF1    PF1         0x10
                    0x08    WDIF    WTRF    EWT     RWT         0x01

                    Alternates:

            PCON    0x80    SMOD                                0x10
                    0x08                                        0x01
            T2CON   0x80                                        0x10
                    0x08                    C_T2    _RL2        0x01

                                       APPENDIX E

                                     ASZ80 ASSEMBLER

            E.1  .hd64 DIRECTIVE

            Format:

                    .hd64

            The  .hd64  directive enables processing of the HD64180 specific
            mnemonics not included in  the  Z80  instruction  set.   HD64180
            mnemonics  encountered  without  the  .hd64  directive  will  be
            flagged with an 'o' error.

            E.2  Z80 REGISTER SET AND CONDITIONS

               The following is a complete list of register designations and
            condition mnemonics:

                    byte registers  -       a,b,c,d,e,h,l,i,r
                    register pairs  -       af,af',bc,de,hl
                    word registers  -       pc,sp,ix,iy

                    C -     carry bit set
                    M -     sign bit set
                    NC -    carry bit clear
                    NZ -    zero bit clear
                    P -     sign bit clear
                    PE -    parity even
                    PO -    parity odd
                    Z -     zero bit set

            ASZ80 ASSEMBLER                                         PAGE E-2
            Z80 INSTRUCTION SET

            E.3  Z80 INSTRUCTION SET

               The  following  list specifies the format for each addressing
            mode supported by ASZ80:

                    #data           immediate data
                                    byte or word data

                    n               byte value

                    rg              a byte register
                                    a,b,c,d,e,h,l

                    rp              a register pair
                                    bc,de,hl

                    (hl)            implied addressing or
                                    register indirect addressing

                    (label)         direct addressing

                    offset(ix)      indexed addressing with
                                    an offset

                    label           call/jmp/jr label

            The terms data, n, label, and offset may all be expressions.

               Note  that  not all addressing modes are valid with every in-
            struction, refer to the Z80/HD64180  technical  data  for  valid
            modes.

               The  following  tables  list all Z80/HD64180 mnemonics recog-
            nized by the ASZ80 assembler.  The designation []  refers  to  a
            required addressing mode argument.

            ASZ80 ASSEMBLER                                         PAGE E-3
            Z80 INSTRUCTION SET

            E.3.1  Inherent Instructions

                    ccf             cpd
                    cpdr            cpi
                    cpir            cpl
                    daa             di
                    ei              exx
                    halt            neg
                    nop             reti
                    retn            rla
                    rlca            rld
                    rra             rrca
                    rrd             scf

            E.3.2  Implicit Operand Instructions

                    adc     a,[]            adc     []
                    add     a,[]            add     []
                    and     a,[]            and     []
                    cp      a,[]            cp      []
                    dec     a,[]            dec     []
                    inc     a,[]            inc     []
                    or      a,[]            or      []
                    rl      a,[]            rl      []
                    rlc     a,[]            rlc     []
                    rr      a,[]            rr      []
                    rrc     a,[]            rrc     []
                    sbc     a,[]            sbc     []
                    sla     a,[]            sla     []
                    sra     a,[]            sra     []
                    srl     a,[]            srl     []
                    sub     a,[]            sub     []
                    xor     a,[]            xor     []

            ASZ80 ASSEMBLER                                         PAGE E-4
            Z80 INSTRUCTION SET

            E.3.3  Load Instruction

                    ld      rg,[]           ld      [],rg
                    ld      (bc),a          ld      a,(bc)
                    ld      (de),a          ld      a,(de)
                    ld      (label),a       ld      a,(label)
                    ld      (label),rp      ld      rp,(label)
                    ld      i,a             ld      r,a
                    ld      a,i             ld      a,r
                    ld      sp,hl           ld      sp,ix
                    ld      sp,iy           ld      rp,#data

                    ldd                     lddr
                    ldi                     ldir

            E.3.4  Call/Return Instructions

                    call    C,label         ret     C
                    call    M,label         ret     M
                    call    NC,label        ret     NC
                    call    NZ,label        ret     NZ
                    call    P,label         ret     P
                    call    PE,label        ret     PE
                    call    PO,label        ret     PO
                    call    Z,label         ret     Z
                    call    label           ret

            E.3.5  Jump and Jump to Subroutine Instructions

                    jp      C,label         jp      M,label
                    jp      NC,label        jp      NZ,label
                    jp      P,label         jp      PE,label
                    jp      PO,label        jp      Z,label

                    jp      (hl)            jp      (ix)
                    jp      (iy)            jp      label

                    djnz    label

                    jr      C,label         jr      NC,label
                    jr      NZ,label        jr      Z,label
                    jr      label

            ASZ80 ASSEMBLER                                         PAGE E-5
            Z80 INSTRUCTION SET

            E.3.6  Bit Manipulation Instructions

                    bit     n,[]
                    res     n,[]
                    set     n,[]

            E.3.7  Interrupt Mode and Reset Instructions

                    im      n
                    im      n
                    im      n
                    rst     n

            E.3.8  Input and Output Instructions

                    in      a,(n)           in      rg,(c)
                    ind                     indr
                    ini                     inir

                    out     (n),a           out     (c),rg
                    outd                    otdr
                    outi                    otir

            E.3.9  Register Pair Instructions

                    add     hl,rp           add     ix,rp
                    add     iy,rp

                    adc     hl,rp           sbc     hl,rp

                    ex      (sp),hl         ex      (sp),ix
                    ex      (sp),iy
                    ex      de,hl
                    ex      af,af'

                    push    rp              pop     rp

            ASZ80 ASSEMBLER                                         PAGE E-6
            Z80 INSTRUCTION SET

            E.3.10  HD64180 Specific Instructions

                    in0     rg,(n)
                    out0    (n),rg

                    otdm                    otdmr
                    otim                    otimr

                    mlt     bc              mlt     de
                    mlt     hl              mlt     sp

                    slp

                    tst     a
                    tstio   #data

                                       APPENDIX F

                                     ASGB ASSEMBLER

            F.1  ACKNOWLEDGEMENT

               Thanks  to  Roger Ivie for his contribution of the ASGB cross
            assembler.

                    Roger Ivie
                    ivie at cc dot usu dot edu

            F.2  INTRODUCTION

               The  Gameboy uses an 8-bit processor which is closely related
            to the 8080.  It is usually described as a modified Z80, but may
            be more closely understood as an enhanced 8080;  it has the 8080
            register set and many, but not all, enhanced  Z80  instructions.
            However,  even  this is not accurate, for the Gameboy also lacks
            some basic 8080 instructions (most annoyingly  SHLD  and  LHLD).
            ASGB is based on ASZ80 and therefore uses the Z80 mnemonic set.

            F.3  GAMEBOY REGISTER SET AND CONDITIONS

               The following is a complete list of register designations and
            condition mnemonics:

                    byte registers - a,b,c,d,e,h,l
                    register pairs - af, bc, de, hl
                    word registers - pc, sp

                    C  - carry bit set
                    NC - carry bit clear
                    NZ - zero bit clear
                    Z  - zero bit set

            ASGB ASSEMBLER                                          PAGE F-2
            GAMEBOY INSTRUCTION SET

            F.4  GAMEBOY INSTRUCTION SET

               The following tables list all Gameboy mnemnoics recognized by
            the ASGB assembler.  The designation [] refers to a required ad-
            dressing mode argument.  The following list specifies the format
            for each addressing mode supported by ASGB:

                    #data           immediate data
                                    byte or word data

                    n               byte value

                    rg              a byte register
                                    a,b,c,d,e,h,l

                    rp              a register pair or 16-bit register
                                    bc,de,hl

                    (hl)            implied addressing or
                                    register indirect addressing

                    (label)         direct addressing

                    label           call/jmp/jr label

               The terms data, dir, and ext may all be expression.  The term
            dir is not allowed to be an external reference.

               Note  that  not all addressing modes are valid with every in-
            struction.  Although official information is not, as  far  as  I
            know, publically available for the Gameboy processor, many unof-
            ficial sources are available on the internet.

            F.4.1  .tile Directive

            Format: .tile /string/

            where:  string  is  a  string of ascii characters taken from the
                            set ' ', '.', '+', '*', '0', '1', '2', and  '3'.
                            The   string   must   be  a  multiple  of  eight
                            characters long.

                    /  /     represent  the  delimiting  characters.   These
                            delimiters   may   be   any   paired    printing
                            characters,  as  long  as the characters are not
                            contained within  the  string  itself.   If  the
                            delimiting  characters  do  not match, the .tile
                            directive will give the (q) error.

            ASGB ASSEMBLER                                          PAGE F-3
            GAMEBOY INSTRUCTION SET

                 The Gameboy displays information on the screen using a pro-
            grammable character set (referred to as  "tiles"  among  Gameboy
            developers).   The ASGB cross assembler has a processor-specific
            assembler directive  to  aid  in  the  creation  of  the  game's
            character set.

                 Each  character is created from an 8x8 grid of pixels, each
            pixel of which is composed of two bits.  The .tile directive ac-
            cepts  a single string argument which is processed to create the
            byte  values  corresponding  to  the  lines  of  pixels  in  the
            character.   The  string  argument  must  be  some multiple of 8
            characters long, and be one of these characters:

                    ' ' or '0' - for the pixel value 00
                    '.' or '1' - for the pixel value 01
                    '+' or '2' - for the pixel value 10
                    '*' or '3' - for the pixel value 11

                 The .tile directive processes each 8-character group of its
            string argument to create the two-byte  value  corresponding  to
            that  line of pixels.  The example in the popular extant litera-
            ture could be done using ASGB like this:

               0000 7C 7C                 1         .tile " *****  "
               0002 00 C6                 2         .tile "++   ++ "
               0004 C6 00                 3         .tile "..   .. "
               0006 00 FE                 4         .tile "+++++++ "
               0008 C6 C6                 5         .tile "**   ** "
               000A 00 C6                 6         .tile "++   ++ "
               000C C6 00                 7         .tile "..   .. "
               000E 00 00                 8         .tile "        "

                 Or, using the synonym character set, as:

               0010 7C 7C                10         .tile "03333300"
               0012 00 C6                11         .tile "22000220"
               0014 C6 00                12         .tile "11000110"
               0016 00 FE                13         .tile "22222220"
               0018 C6 C6                14         .tile "33000330"
               001A 00 C6                15         .tile "22000220"
               001C C6 00                16         .tile "11000110"
               001E 00 00                17         .tile "00000000"

                 Since .tile is perfectly willing to assemble multiple lines
            of a character at once (as long as it is given complete rows  of
            pixels), it could even be done as:

                    .tile " *****  ++   ++ ..   .. +++++++ "
                    .tile "**   ** ++   ++ ..   ..         "

            ASGB ASSEMBLER                                          PAGE F-4
            GAMEBOY INSTRUCTION SET

            F.4.2  Potentially Controversial Mnemonic Selection

                 Although the Gameboy processor is based on the Z80, it does
            include some features which are not present in the Z80.  The Z80
            mnemonic  set  is  not  sufficient  to describe these additional
            operations;  mnemonics must be created for the  new  operations.
            The  mnemonics ASGB uses are not the same as those used by other
            publically-available Gameboy assemblers.

            F.4.2.1  Auto-Indexing Loads  -

                 The  Gameboy provides instructions to load or store the ac-
            cumulator indirectly via HL and then subsequently  increment  or
            decrement HL.  ASGB uses the mnemonic 'ldd' for the instructions
            which decrement HL and 'ldi' for the instructions  which  incre-
            ment  HL.   Because the Gameboy lacks the Z80's block moves, the
            mnemonics are not otherwise needed by ASGB.

                    ldd a,(hl)      ldd (hl),a
                    ldi a,(hl)      ldi (hl),a

            F.4.2.2  Input and Output Operations  -

                 The  Gameboy  replaces the Z80's separate address space for
            I/O with a mechanism similar to the zero page addressing of pro-
            cessors  such  as  the  6800  or 6502.  All I/O registers in the
            Gameboy reside in the address range between 0xff00  and  0xffff.
            The  Gameboy adds special instructions to load and store the ac-
            cumulator from and into this page of memory.   The  instructions
            are  analogous to the Z80's in and out instructions and ASGB re-
            tains the 'in' and 'out' mnemonics for them.

                    in a,(n)        out (n),a
                    in a,(c)        out (c),a

                 From  ASGB's  perspective,  the  RAM  available from 0xff80
            through 0xffff is composed of unused I/O locations  rather  than
            direct-page RAM.

            ASGB ASSEMBLER                                          PAGE F-5
            GAMEBOY INSTRUCTION SET

            F.4.2.3  The 'stop' Instruction  -

                 The  publically-available  documentation  for  the  Gameboy
            lists the 'stop' instruction as the two-byte instruction 10  00,
            and the other freely-available Gameboy assemblers assemble it in
            that manner.  As far as I can tell, the only rationale for  this
            is  that  the  corresponding Z80 instruction ('djnz label') is a
            two-byte instruction.  ASGB assembles 'stop' as the one-byte in-
            struction 10.

            F.4.3  Inherent Instructions

                    ccf             cpl
                    daa             di
                    ei              nop
                    halt            rla
                    rlca            rra
                    rrca            scf
                    reti            stop
                    swap

            F.4.4  Implicit Operand Instructions

                    adc a,[]        adc []
                    add a,[]        add []
                    and a,[]        and []
                    cp a,[]         cp []
                    dec a,[]        dec []
                    inc a,[]        inc []
                    or a,[]         or []
                    rl a,[]         rl []
                    rlc a,[]        rlc []
                    rr a,[]         rr []
                    rrc a,[]        rrc []
                    sbc a,[]        sbc []
                    sla a,[]        sla []
                    sra a,[]        sra []
                    srl a,[]        srl []
                    sub a,[]        sub []
                    xor a,[]        xor []

            ASGB ASSEMBLER                                          PAGE F-6
            GAMEBOY INSTRUCTION SET

            F.4.5  Load Instructions

                    ld rg,[]        ld [],rg
                    ld (bc),a       ld a,(bc)
                    ld (de),a       ld a,(de)
                    ld (label),a    ld a,(label)
                    ld (label),sp   ld rp,#data
                    ld sp,hl        ld hl,sp

                    ldd a,(hl)      ldd (hl),a
                    ldi a,(hl)      ldi (hl),a

            F.4.6  Call/Return Instructions

                    call C,label    ret C
                    call NC,label   ret NC
                    call Z,label    ret Z
                    call NZ,label   ret NZ
                    call label      ret

                    rst n

            F.4.7  Jump Instructions

                    jp C,label      jp NC,label
                    jp Z,label      jp NZ,label

                    jp (hl)         jp label

                    jr C,label      jr NC,label
                    jr Z,label      jr NZ,label
                    jr label

            F.4.8  Bit Manipulation Instructions

                    bit n,[]
                    res n,[]
                    set n,[]

            ASGB ASSEMBLER                                          PAGE F-7
            GAMEBOY INSTRUCTION SET

            F.4.9  Input and Output Instructions

                    in a,(n)        in a,(c)
                    out (n),a       out (c),a

            F.4.10  Register Pair Instructions

                    add hl,rp       add hl,sp
                    add sp,#data

                    push rp         pop rp

                                       APPENDIX G

                                     AS430 ASSEMBLER

            G.1  MPS430 REGISTER SET

            The following is a list of the MPS430 registers used by AS430:

            Sixteen 16-bit registers provide adddress, data, and
            special functions:
                    pc  /   r0      -       program counter
                    sp  /   r1      -       stack pointer
                    sr  /   r2      -       status register
                    cg1 /   r2      -       constant generator 1
                    cg2 /   r3      -       constant generator 2
                            r4      -       working register r4
                            r5      -       working register r5
                            ...
                            r14     -       working register r14
                            r15     -       working register r15

            AS430 ASSEMBLER                                         PAGE G-2
            MPS430 REGISTER SET

            G.2  MPS430 ADDRESSING MODES

            The following list specifies the format for each addressing mode
            supported by AS430:

            Source/Destination Operand Addressing Modes
            As/Ad   Addressing Mode Syntax  Description
            -----   --------------- ------  -----------
            00/0    Register mode   Rn      Register contents are operand.
            01/1    Indexed mode    X(Rn)   (Rn + X) points to the operand,
                                            X is stored in the next word.
            01/1    Symbolic mode   ADDR    (PC + X) points to the operand,
                                            X is stored in the next word,
                                            Indexed mode X(PC) is used.
            01/1    Absolute mode   &ADDR   The word following the
                                            instruction, contains the
                                            absolute address.
            10/-    Indirect        @Rn     Rn is used as a pointer to the
                    register mode           operand.
            11/-    Indirect        @Rn+    Rn is used as a pointer to the
                    autoincrement           operand. Rn is incremented
                                            afterwards.
            11/-    Immediate mode  #N      The word following the
                                            instruction contains the
                                            immediate constant N. Indirect
                                            autoincrement mode @PC+ is used.

            The  terms  ADDR, X and N may all be expressions.  Note that not
            all addressing modes are valid with every instruction, refer  to
            the MPS430 technical data for valid modes.

            AS430 ASSEMBLER                                         PAGE G-3
            MPS430 ADDRESSING MODES

            G.2.1  MPS430 Instruction Mnemonics

            The following table lists all MPS430 family mnemonics recognized
            by the AS430 assembler.  The designations src and dst  refer  to
            required source and/or destination addressing mode arguments.

            * ADC[.W];ADC.B  dst        dst + C -> dst
              ADD[.W];ADD.B  src,dst    src + dst -> dst
              ADDC[.W];ADDC.B           src,dst src + dst + C -> dst
              AND[.W];AND.B  src,dst    src .and. dst -> dst
              BIC[.W];BIC.B src,dst     .not.src .and. dst -> dst
              BIS[.W];BIS.B src,dst     src .or. dst -> dst
              BIT[.W];BIT.B src,dst     src .and. dst
            * BR dst                Branch to .......
            * BRANCH dst            Branch to .......
              CALL dst              PC+2 -> stack, dst -> PC
            * CLR[.W];CLR.B dst     Clear destination
            * CLRC                  Clear carry bit
            * CLRN                  Clear negative bit
            * CLRZ                  Clear zero bit
              CMP[.W];CMP.B src,dst     dst - src
            * DADC[.W];DADC.B dst       dst + C -> dst (decimal)
              DADD[.W];DADD.B src,dst   src + dst + C -> dst (decimal)
            * DEC[.W];DEC.B dst     dst - 1 -> dst
            * DECD[.W];DECD.B dst   dst - 2 -> dst
            * DINT                  Disable interrupt
            * EINT                  Enable interrupt
            * INC[.W];INC.B dst     dst + 1 -> dst
            * INCD[.W];INCD.B dst   dst + 2 -> dst
            * INV[.W];INV.B dst     Invert destination
              JC/JHS Label          Jump to Label if Carry-bit is set
              JEQ/JZ Label          Jump to Label if Zero-bit is set
              JGE Label             Jump to Label if (N .XOR. V) = 0
              JL Label              Jump to Label if (N .XOR. V) = 1
              JMP Label             Jump to Label unconditionally
              JN Label              Jump to Label if Negative-bit is set
              JNC/JLO Label         Jump to Label if Carry-bit is reset
              JNE/JNZ Label         Jump to Label if Zero-bit is reset
              MOV[.W];MOV.B src,dst     src -> dst
            * NOP                   No operation

            AS430 ASSEMBLER                                         PAGE G-4
            MPS430 ADDRESSING MODES

            * POP[.W];POP.B dst     Item from stack, SP+2 -> SP
              PUSH[.W];PUSH.B src   SP - 2 -> SP, src -> @SP
              RETI                  Return from interrupt
                                        TOS -> SR, SP + 2 -> SP
                                        TOS -> PC, SP + 2 -> SZP
            * RET                   Return from subroutine
                                        TOS -> PC, SP + 2 -> SP
            * RLA[.W];RLA.B dst     Rotate left arithmetically
            * RLC[.W];RLC.B dst     Rotate left through carry
              RRA[.W];RRA.B dst     MSB -> MSB . ....LSB -> C
              RRC[.W];RRC.B dst     C -> MSB . ......LSB -> C
            * SBC[.W];SBC.B dst     Subtract carry from destination
            * SETC                  Set carry bit
            * SETN                  Set negative bit
            * SETZ                  Set zero bit
              SUB[.W];SUB.B src,dst     dst + .not.src + 1 -> dst
              SUBC[.W];SUBC.B src,dst   dst + .not.src + C -> dst
              SBB[.W];SBB.B src,dst     dst + .not.src + C -> dst
              SWPB dst              swap bytes
              SXT dst               Bit7 -> Bit8 ........ Bit15
            * TST[.W];TST.B dst     Test destination
              XOR[.W];XOR.B src,dst     src .xor. dst -> dst
                    Note: Asterisked Instructions
                    Asterisked (*) instructions are emulated.
                    They are replaced with coreinstructions
                    by the assembler.

                                       APPENDIX H

                                     ASH8 ASSEMBLER

            H.1  H8/3XX REGISTER SET

            The following is a list of the H8 registers used by ASH8:

                    r0  -  r7,sp            16-bit accumulators
                    r0L -  r7L,spL          8-bit accumulators
                    r0H -  r7H,spH          8-bit accumulators
                    spL,spH,sp              stack pointers
                    ccr                     condition code

            H.2  H8/3XX INSTRUCTION SET

                 The  following  tables list all H8/3xx mnemonics recognized
            by the ASH8 assembler.  The designation [] refers to a  required
            addressing  mode  argument.   The  following  list specifies the
            format for each addressing mode supported by ASH8:

                    #xx:3           immediate data (3  bit)
                    #xx:8           immediate data (8  bit)
                    #xx:16          immediate data (16 bit)

                    *dir            direct page addressing
                                    (see .setdp directive)
                                    0xFF00 <= dir <= 0xFFFF

                    label           branch label

                    rn              registers (16 bit)
                                    r0-r7,sp

                    rnB             registers (8 bit)
                                    r0H-r7H,r0L-r7L,spH,spL

            ASH8 ASSEMBLER                                          PAGE H-2
            H8/3XX INSTRUCTION SET

                    ccr             condition code register

                    @rn             register indirect

                    @-rn            register indirect (auto pre-decrement)

                    @rn+            register indirect (auto post-increment)

                    @[offset,rn]    register indirect, 16-bit displacement

                    @@offset        memory indirect, (8-bit address)

                    ext             extended addressing (16-bit)

            The  terms  data, dir, label, offset, and ext may all be expres-
            sions.

                 Note that not all addressing modes are valid with every in-
            struction, refer to the H8/3xx technical data for valid modes.

            H.2.1  Inherent Instructions

                    eepmov
                    nop
                    sleep
                    rte
                    rts

            H.2.2  Branch Instructions

                    bcc     label                   bcs     label
                    beq     label                   bf      label
                    bge     label                   bgt     label
                    bhi     label                   bhis    label
                    bhs     label                   ble     label
                    blo     label                   blos    label
                    bls     label                   blt     label
                    bmi     label                   bne     label
                    bpl     label                   bra     label
                    brn     label                   bt      label
                    bvc     label                   bvs     label
                    bsr     label

            ASH8 ASSEMBLER                                          PAGE H-3
            H8/3XX INSTRUCTION SET

            H.2.3  Single Operand Instructions

                    Free Form

                    daa     rnB                     das     rnB

                    dec     rnB                     inc     rnB

                    neg     rnB                     not     rnB

                    rotxl   rnB                     rotxr   rnB

                    rotl    rnB                     rotr    rnB

                    shal    rnB                     shar    rnB

                    shll    rnB                     shlr    rnB

                    push    rn                      pop     rn

                    Byte / Word Form

                    daa.b   rnB                     das.b   rnB

                    dec.b   rnB                     inc.b   rnB

                    neg.b   rnB                     not.b   rnB

                    rotxl.b rnB                     rotxr.b rnB

                    rotl.b  rnB                     rotr.b  rnB

                    shal.b  rnB                     shar.b  rnB

                    shll.b  rnB                     shlr.b  rnB

                    push.w  rn                      pop.w   rn

            ASH8 ASSEMBLER                                          PAGE H-4
            H8/3XX INSTRUCTION SET

            H.2.4  Double Operand Instructions

                    Free Form

                    add     rnB,rnB                 add     #xx:8,rnB
                    add     rn,rn
                    adds    #1,rn                   adds    #2,rn
                    addx    rnB,rnB                 addx    #xx:8,rnB

                    cmp     rnB,rnB                 cmp     #xx:8,rnB
                    cmp     rn,rn

                    sub     rnB,rnB
                    sub     rn,rn
                    subs    #1,rn                   subs    #2,rn
                    subx    rnB,rnB                 subx    #xx:8,rnB

                    and     rnB,rnB                 and     #xx:8,rnB
                                                    and     #xx:8,ccr

                    or      rnB,rnB                 or      #xx:8,rnB
                                                    or      #xx:8,ccr

                    xor     rnB,rnB                 xor     #xx:8,rnB
                                                    xor     #xx:8,ccr

                    Byte / Word Form

                    add.b   rnB,rnB                 add.b   #xx:8,rnB
                    add.w   rn,rn

                    cmp.b   rnB,rnB                 cmp.b   #xx:8,rnB
                    cmp.w   rn,rn

                    sub.b   rnB,rnB
                    sub.w   rn,rn

                    addx.b  rnB,rnB                 addx.b  #xx:8,rnB

                    and.b   rnB,rnB                 and.b   #xx:8,rnB
                                                    and.b   #xx:8,ccr

                    or.b    rnB,rnB                 or.b    #xx:8,rnB
                                                    or.b    #xx:8,ccr

                    subx.b  rnB,rnB                 subx.b  #xx:8,rnB

                    xor.b   rnB,rnB                 xor.b   #xx:8,rnB
                                                    xor.b   #xx:8,ccr

            ASH8 ASSEMBLER                                          PAGE H-5
            H8/3XX INSTRUCTION SET

            H.2.5  Mov Instructions

                    Free Form

                    mov     rnB,rnB                 mov     rn,rn
                    mov     #xx:8,rnB               mov     #xx:16,rn
                    mov     @rn,rnB                 mov     @rn,rn
                    mov     @[offset,rn],rnB        mov     @[offset,rn],rn
                    mov     @rn+,rnB                mov     @rn+,rn
                    mov     @dir,rnB
                    mov     dir,rnB
                    mov     *@dir,rnB
                    mov     *dir,rnB
                    mov     @label,rnB              mov     @label,rn
                    mov     label,rnB               mov     label,rn
                    mov     rnB,@rn                 mov     rn,@rn
                    mov     rnB,@[offset,rn]        mov     rn,@[offset,rn]
                    mov     rnB,@-rn                mov     rn,@-rn
                    mov     rnB,@dir
                    mov     rnB,dir
                    mov     rnB,*@dir
                    mov     rnB,*dir
                    mov     rnB,@label              mov     rn,@label
                    mov     rnB,label               mov     rn,label

                    Byte / Word Form

                    mov.b   rnB,rnB                 mov.w   rn,rn
                    mov.b   #xx:8,rnB               mov.w   #xx:16,rn
                    mov.b   @rn,rnB                 mov.w   @rn,rn
                    mov.b   @[offset,rn],rnB        mov.w   @[offset,rn],rn
                    mov.b   @rn+,rnB                mov.w   @rn+,rn
                    mov.b   @dir,rnB
                    mov.b   dir,rnB
                    mov.b   *@dir,rnB
                    mov.b   *dir,rnB
                    mov.b   @label,rnB              mov.w   @label,rn
                    mov.b   label,rnB               mov.w   label,rn
                    mov.b   rnB,@rn                 mov.w   rn,@rn
                    mov.b   rnB,@[offset,rn]        mov.w   rn,@[offset,rn]
                    mov.b   rnB,@-rn                mov.w   rn,@-rn
                    mov.b   rnB,@dir
                    mov.b   rnB,dir
                    mov.b   rnB,*@dir
                    mov.b   rnB,*dir
                    mov.b   rnB,@label              mov.w   rn,@label
                    mov.b   rnB,label               mov.w   rn,label

            ASH8 ASSEMBLER                                          PAGE H-6
            H8/3XX INSTRUCTION SET

            H.2.6  Bit Manipulation Instructions

                    bld     #xx:3,rnB               bld     #xx:3,@rn
                    bld     #xx:3,@dir              bld     #xx:3,dir
                    bld     #xx:3,*@dir             bld     #xx:3,*dir

                    bild    #xx:3,rnB               bild    #xx:3,@rn
                    bild    #xx:3,@dir              bild    #xx:3,dir
                    bild    #xx:3,*@dir             bild    #xx:3,*dir

                    bst     #xx:3,rnB               bst     #xx:3,@rn
                    bst     #xx:3,@dir              bst     #xx:3,dir
                    bst     #xx:3,*@dir             bst     #xx:3,*dir

                    bist    #xx:3,rnB               bist    #xx:3,@rn
                    bist    #xx:3,@dir              bist    #xx:3,dir
                    bist    #xx:3,*@dir             bist    #xx:3,*dir

                    band    #xx:3,rnB               band    #xx:3,@rn
                    band    #xx:3,@dir              band    #xx:3,dir
                    band    #xx:3,*@dir             band    #xx:3,*dir

                    biand   #xx:3,rnB               biand   #xx:3,@rn
                    biand   #xx:3,@dir              biand   #xx:3,dir
                    biand   #xx:3,*@dir             biand   #xx:3,*dir

                    bor     #xx:3,rnB               bor     #xx:3,@rn
                    bor     #xx:3,@dir              bor     #xx:3,dir
                    bor     #xx:3,*@dir             bor     #xx:3,*dir

                    bior    #xx:3,rnB               bior    #xx:3,@rn
                    bior    #xx:3,@dir              bior    #xx:3,dir
                    bior    #xx:3,*@dir             bior    #xx:3,*dir

                    bxor    #xx:3,rnB               bxor    #xx:3,@rn
                    bxor    #xx:3,@dir              bxor    #xx:3,dir
                    bxor    #xx:3,*@dir             bxor    #xx:3,*dir

                    bixor   #xx:3,rnB               bixor   #xx:3,@rn
                    bixor   #xx:3,@dir              bixor   #xx:3,dir
                    bixor   #xx:3,*@dir             bixor   #xx:3,*dir

            ASH8 ASSEMBLER                                          PAGE H-7
            H8/3XX INSTRUCTION SET

            H.2.7  Extended Bit Manipulation Instructions

                    bset    #xx:3,rnB               bset    #xx:3,@rn
                    bset    #xx:3,@dir              bset    #xx:3,dir
                    bset    #xx:3,*@dir             bset    #xx:3,*dir
                    bset    rnB,rnB                 bset    rnB,@rn
                    bset    rnB,@dir                bset    rnB,dir
                    bset    rnB,*@dir               bset    rnB,*dir

                    bclr    #xx:3,rnB               bclr    #xx:3,@rn
                    bclr    #xx:3,@dir              bclr    #xx:3,dir
                    bclr    #xx:3,*@dir             bclr    #xx:3,*dir
                    bclr    rnB,rnB                 bclr    rnB,@rn
                    bclr    rnB,@dir                bclr    rnB,dir
                    bclr    rnB,*@dir               bclr    rnB,*dir

                    bnot    #xx:3,rnB               bnot    #xx:3,@rn
                    bnot    #xx:3,@dir              bnot    #xx:3,dir
                    bnot    #xx:3,*@dir             bnot    #xx:3,*dir
                    bnot    rnB,rnB                 bnot    rnB,@rn
                    bnot    rnB,@dir                bnot    rnB,dir
                    bnot    rnB,*@dir               bnot    rnB,*dir

                    btst    #xx:3,rnB               btst    #xx:3,@rn
                    btst    #xx:3,@dir              btst    #xx:3,dir
                    btst    #xx:3,*@dir             btst    #xx:3,*dir
                    btst    rnB,rnB                 btst    rnB,@rn
                    btst    rnB,@dir                btst    rnB,dir
                    btst    rnB,*@dir               btst    rnB,*dir

            H.2.8  Condition Code Instructions

                    andc    #xx:8,ccr               andc    #xx:8
                    and     #xx:8,ccr               and.b   #xx:8,ccr

                    ldc     #xx:8,ccr               ldc     #xx:8
                    ldc     rnB,ccr                 ldc     rnB

                    orc     #xx:8,ccr               orc     #xx:8
                    or      #xx:8,ccr               or.b    #xx:8,ccr

                    xorc    #xx:8,ccr               xorc    #xx:8
                    xor     #xx:8,ccr               xor.b   #xx:8,ccr

                    stc     ccr,rnB                 stc     rnB

            ASH8 ASSEMBLER                                          PAGE H-8
            H8/3XX INSTRUCTION SET

            H.2.9  Other Instructions

                    divxu   rnB,rn                  divxu.b rnB,rn

                    mulxu   rnB,rn                  mulxu.b rnB,rn

                    movfpe  @label,rnB              movfpe  label,rnB
                    movfpe.b  @label,rnB            movfpe.b  label,rnB

                    movtpe  @label,rnB              movtpe  label,rnB
                    movtpe.b  @label,rnB            movtpe.b  label,rnB

            H.2.10  Jump and Jump to Subroutine Instructions

                    jmp     @rn                     jmp     @@dir
                    jmp     @label                  jmp     label

                    jsr     @rn                     jsr     @@dir
                    jsr     @label                  jsr     label

                                       APPENDIX I

                                    AS6800 ASSEMBLER

            I.1  6800 REGISTER SET

            The following is a list of the 6800 registers used by AS6800:

                    a,b     -       8-bit accumulators
                    x       -       index register

            I.2  6800 INSTRUCTION SET

                 The  following  tables  list  all  6800/6802/6808 mnemonics
            recognized by the AS6800 assembler.  The designation  []  refers
            to  a  required  addressing  mode  argument.  The following list
            specifies the format  for  each  addressing  mode  supported  by
            AS6800:

                    #data           immediate data
                                    byte or word data

                    *dir            direct page addressing
                                    (see .setdp directive)
                                    0 <= dir <= 255

                    ,x              register indirect addressing
                                    zero offset

                    offset,x        register indirect addressing
                                    0 <= offset <= 255

                    ext             extended addressing

                    label           branch label

            The  terms  data, dir, offset, ext, and label may all be expres-
            sions.

            AS6800 ASSEMBLER                                        PAGE I-2
            6800 INSTRUCTION SET

                 Note that not all addressing modes are valid with every in-
            struction, refer to the 6800 technical data for valid modes.

            I.2.1  Inherent Instructions

                    aba                     cba
                    clc                     cli
                    clv                     daa
                    des                     dex
                    ins                     inx
                    nop                     rti
                    rts                     sba
                    sec                     sei
                    sev                     swi
                    tab                     tap
                    tba                     tpa
                    tsx                     txs
                    wai

                    psha                    pshb
                    psh a                   psh b
                    pula                    pulb
                    pul a                   pul b

            I.2.2  Branch Instructions

                    bra     label           bhi     label
                    bls     label           bcc     label
                    bhs     label           bcs     label
                    blo     label           bne     label
                    beq     label           bvc     label
                    bvs     label           bpl     label
                    bmi     label           bge     label
                    blt     label           bgt     label
                    ble     label           bsr     label

            AS6800 ASSEMBLER                                        PAGE I-3
            6800 INSTRUCTION SET

            I.2.3  Single Operand Instructions

                    asla                    aslb
                    asl a                   asl b
                    asl     []

                    asra                    asrb
                    asr a                   asr b
                    asr     []

                    clra                    clrb
                    clr a                   clr b
                    clr     []

                    coma                    comb
                    com a                   com b
                    com     []

                    deca                    decb
                    dec a                   dec b
                    dec     []

                    inca                    incb
                    inc a                   inc b
                    inc     []

                    lsla                    lslb
                    lsl a                   lsl b
                    lsl     []

                    lsra                    lsrb
                    lsr a                   lsr b
                    lsr     []

                    nega                    negb
                    neg a                   neg b
                    neg     []

                    rola                    rolb
                    rol a                   rol b
                    rol     []

                    rora                    rorb
                    ror a                   ror b
                    ror     []

                    tsta                    tstb
                    tst a                   tst b
                    tst     []

            AS6800 ASSEMBLER                                        PAGE I-4
            6800 INSTRUCTION SET

            I.2.4  Double Operand Instructions

                    adca    []              adcb    []
                    adc a   []              adc b   []

                    adda    []              addb    []
                    add a   []              add b   []

                    anda    []              andb    []
                    and a   []              and b   []

                    bita    []              bitb    []
                    bit a   []              bit b   []

                    cmpa    []              cmpb    []
                    cmp a   []              cmp b   []

                    eora    []              eorb    []
                    eor a   []              eor b   []

                    ldaa    []              ldab    []
                    lda a   []              lda b   []

                    oraa    []              orab    []
                    ora a   []              ora b   []

                    sbca    []              sbcb    []
                    sbc a   []              sbc b   []

                    staa    []              stab    []
                    sta a   []              sta b   []

                    suba    []              subb    []
                    sub a   []              sub b   []

            I.2.5  Jump and Jump to Subroutine Instructions

                    jmp     []              jsr     []

            AS6800 ASSEMBLER                                        PAGE I-5
            6800 INSTRUCTION SET

            I.2.6  Long Register Instructions

                    cpx     []
                    lds     []              sts     []
                    ldx     []              stx     []

                                       APPENDIX J

                                    AS6801 ASSEMBLER

            J.1  .hd6303 DIRECTIVE

            Format:

                    .hd6303

            The  .hd6303 directive enables processing of the HD6303 specific
            mnemonics not included in  the  6801  instruction  set.   HD6303
            mnemonics  encountered  without  the  .hd6303  directive will be
            flagged with an 'o' error.

            J.2  6801 REGISTER SET

            The following is a list of the 6801 registers used by AS6801:

                    a,b     -       8-bit accumulators
                    d       -       16-bit accumulator
                    x       -       index register

            J.3  6801 INSTRUCTION SET

                 The  following  tables  list all 6801/6303 mnemonics recog-
            nized by the AS6801 assembler.  The designation [] refers  to  a
            required addressing mode argument.  The following list specifies
            the format for each addressing mode supported by AS6801:

                    #data           immediate data
                                    byte or word data

                    *dir            direct page addressing
                                    (see .setdp directive)
                                    0 <= dir <= 255

            AS6801 ASSEMBLER                                        PAGE J-2
            6801 INSTRUCTION SET

                    ,x              register indirect addressing
                                    zero offset

                    offset,x        register indirect addressing
                                    0 <= offset <= 255

                    ext             extended addressing

                    label           branch label

            The  terms  data, dir, offset, ext, and label may all be expres-
            sions.

                 Note that not all addressing modes are valid with every in-
            struction, refer to  the  6801/6303  technical  data  for  valid
            modes.

            J.3.1  Inherent Instructions

                    aba             abx
                    cba             clc
                    cli             clv
                    daa             des
                    dex             ins
                    inx             mul
                    nop             rti
                    rts             sba
                    sec             sei
                    sev             swi
                    tab             tap
                    tba             tpa
                    tsx             txs
                    wai

            J.3.2  Branch Instructions

                    bra     label           brn     label
                    bhi     label           bls     label
                    bcc     label           bhs     label
                    bcs     label           blo     label
                    bne     label           beq     label
                    bvc     label           bvs     label
                    bpl     label           bmi     label
                    bge     label           blt     label
                    bgt     label           ble     label
                    bsr     label

            AS6801 ASSEMBLER                                        PAGE J-3
            6801 INSTRUCTION SET

            J.3.3  Single Operand Instructions

                    asla            aslb            asld
                    asl a           asl b           asl d
                    asl     []

                    asra            asrb
                    asr a           asr b
                    asr     []

                    clra            clrb
                    clr a           clr b
                    clr     []

                    coma            comb
                    com a           com b
                    com     []

                    deca            decb
                    dec a           dec b
                    dec     []

                    eora            eorb
                    eor a           eor b
                    eor     []

                    inca            incb
                    inc a           inc b
                    inc     []

                    lsla            lslb            lsld
                    lsl a           lsl b           lsl d
                    lsl     []

                    lsra            lsrb            lsrd
                    lsr a           lsr b           lsr d
                    lsr     []

                    nega            negb
                    neg a           neg b
                    neg     []

                    psha            pshb            pshx
                    psh a           psh b           psh x

                    pula            pulb            pulx
                    pul a           pul b           pul x

                    rola            rolb
                    rol a           rol b
                    rol     []

            AS6801 ASSEMBLER                                        PAGE J-4
            6801 INSTRUCTION SET

                    rora            rorb
                    ror a           ror b
                    ror     []

                    tsta            tstb
                    tst a           tst b
                    tst     []

            J.3.4  Double Operand Instructions

                    adca    []      adcb    []
                    adc a   []      adc b   []

                    adda    []      addb    []      addd    []
                    add a   []      add b   []      add d   []

                    anda    []      andb    []
                    and a   []      and b   []

                    bita    []      bitb    []
                    bit a   []      bit b   []

                    cmpa    []      cmpb    []
                    cmp a   []      cmp b   []

                    ldaa    []      ldab    []
                    lda a   []      lda b   []

                    oraa    []      orab    []
                    ora a   []      ora b   []

                    sbca    []      sbcb    []
                    sbc a   []      sbc b   []

                    staa    []      stab    []
                    sta a   []      sta b   []

                    suba    []      subb    []      subd    []
                    sub a   []      sub b   []      sub d   []

            AS6801 ASSEMBLER                                        PAGE J-5
            6801 INSTRUCTION SET

            J.3.5  Jump and Jump to Subroutine Instructions

                    jmp     []      jsr     []

            J.3.6  Long Register Instructions

                    cpx     []      ldd     []
                    lds     []      ldx     []
                    std     []      sts     []
                    stx     []

            J.3.7  6303 Specific Instructions

                    aim     #data, []       eim     #data, []
                    oim     #data, []       tim     #data, []

                    xgdx            slp

                                       APPENDIX K

                                    AS6804 ASSEMBLER

                 Requires the .setdp directive to specify the ram area.

            K.1  6804 REGISTER SET

            The following is a list of the 6804 registers used by AS6804:

                    x,y     -       index registers

            K.2  6804 INSTRUCTION SET

                 The  following tables list all 6804 mnemonics recognized by
            the AS6804 assembler.  The designation [] refers to  a  required
            addressing  mode  argument.   The  following  list specifies the
            format for each addressing mode supported by AS6804:

                    #data           immediate data
                                    byte or word data

                    ,x              register indirect addressing

                    dir             direct addressing
                                    (see .setdp directive)
                                    0 <= dir <= 255

                    ext             extended addressing

                    label           branch label

            The  terms data, dir, and ext may be expressions.  The label for
            the short branchs beq, bne, bcc, and bcs must not be external.

                 Note that not all addressing modes are valid with every in-
            struction, refer to the 6804 technical data for valid modes.

            AS6804 ASSEMBLER                                        PAGE K-2
            6804 INSTRUCTION SET

            K.2.1  Inherent Instructions

                    coma            decx
                    decy            incx
                    incy            rola
                    rti             rts
                    stop            tax
                    tay             txa
                    tya             wait

            K.2.2  Branch Instructions

                    bne     label           beq     label
                    bcc     label           bcs     label

            K.2.3  Single Operand Instructions

                    add     []
                    and     []
                    cmp     []
                    dec     []
                    inc     []
                    lda     []
                    sta     []
                    sub     []

            K.2.4  Jump and Jump to Subroutine Instructions

                    jsr     []
                    jmp     []

            K.2.5  Bit Test Instructions

                    brclr   #data,[],label
                    brset   #data,[],label

                    bclr    #label,[]
                    bset    #label,[]

            AS6804 ASSEMBLER                                        PAGE K-3
            6804 INSTRUCTION SET

            K.2.6  Load Immediate data Instruction

                    mvi     [],#data

            K.2.7  6804 Derived Instructions

                    asla
                    bam     label
                    bap     label
                    bxmi    label
                    bxpl    label
                    bymi    label
                    bypl    label
                    clra
                    clrx
                    clry
                    deca
                    decx
                    decy
                    inca
                    incx
                    incy
                    ldxi    #data
                    ldyi    #data
                    nop
                    tax
                    tay
                    txa
                    tya

                                       APPENDIX L

                                    AS6805 ASSEMBLER

            L.1  6805 REGISTER SET

            The following is a list of the 6805 registers used by AS6805:

                    a       -       8-bit accumulator
                    x       -       index register

            L.2  6805 INSTRUCTION SET

                 The  following tables list all 6805 mnemonics recognized by
            the AS6805 assembler.  The designation [] refers to  a  required
            addressing  mode  argument.   The  following  list specifies the
            format for each addressing mode supported by AS6805:

                    #data           immediate data
                                    byte or word data

                    *dir            direct page addressing
                                    (see .setdp directive)
                                    0 <= dir <= 255

                    ,x              register indirect addressing
                                    zero offset

                    offset,x        register indirect addressing
                                      0 <= offset <= 255   --- byte mode
                                    256 <= offset <= 65535 --- word mode
                                    (an externally defined offset uses the
                                     word mode)

                    ext             extended addressing

                    label           branch label

            AS6805 ASSEMBLER                                        PAGE L-2
            6805 INSTRUCTION SET

            The terms data, dir, offset, and ext may all be expressions.

                 Note that not all addressing modes are valid with every in-
            struction, refer to the 6805 technical data for valid modes.

            L.2.1  Control Instructions

                    clc             cli
                    nop             rsp
                    rti             rts
                    sec             sei
                    stop            swi
                    tax             txa
                    wait

            L.2.2  Bit Manipulation Instructions

                    brset   #data,*dir,label
                    brclr   #data,*dir,label

                    bset    #data,*dir
                    bclr    #data,*dir

            L.2.3  Branch Instructions

                    bra     label           brn     label
                    bhi     label           bls     label
                    bcc     label           bcs     label
                    bne     label           beq     label
                    bhcc    label           bhcs    label
                    bpl     label           bmi     label
                    bmc     label           bms     label
                    bil     label           bih     label
                    bsr     label

            AS6805 ASSEMBLER                                        PAGE L-3
            6805 INSTRUCTION SET

            L.2.4  Read-Modify-Write Instructions

                    nega            negx
                    neg     []

                    coma            comx
                    com     []

                    lsra            lsrx
                    lsr     []

                    rora            rorx
                    ror     []

                    asra            asrx
                    asr     []

                    lsla            lslx
                    lsl     []

                    rola            rolx
                    rol     []

                    deca            decx
                    dec     []

                    inca            incx
                    inc     []

                    tsta            tstx
                    tst     []

                    clra            clrx
                    clr     []

            L.2.5  Register\Memory Instructions

                    sub     []              cmp     []
                    sbc     []              cpx     []
                    and     []              bit     []
                    lda     []              sta     []
                    eor     []              adc     []
                    ora     []              add     []
                    ldx     []              stx     []

            AS6805 ASSEMBLER                                        PAGE L-4
            6805 INSTRUCTION SET

            L.2.6  Jump and Jump to Subroutine Instructions

                    jmp     []              jsr     []

                                       APPENDIX M

                                    AS6808 ASSEMBLER

            M.1  68HC08 REGISTER SET

            The  following  is  a  list  of  the  68HC08  registers  used by
            AS68HC08:

                    a       -       8-bit accumulator
                    x       -       index register
                    s       -       stack pointer

            M.2  68HC08 INSTRUCTION SET

                 The  following  tables list all 68HC08 mnemonics recognized
            by the AS6808 assembler.  The designation []  refers  to  a  re-
            quired  addressing  mode argument.  The following list specifies
            the format for each addressing mode supported by AS6808:

                    #data           immediate data
                                    byte or word data

                    *dir            direct page addressing
                                    (see .setdp directive)
                                    0 <= dir <= 255

                    ,x              register indexed addressing
                                    zero offset

                    offset,x        register indexed addressing
                                      0 <= offset <= 255   --- byte mode
                                    256 <= offset <= 65535 --- word mode
                                    (an externally defined offset uses the
                                     word mode)

                    ,x+             register indexed addressing
                                    zero offset with post increment

            AS6808 ASSEMBLER                                        PAGE M-2
            68HC08 INSTRUCTION SET

                    offset,x+       register indexed addressing
                                    unsigned byte offset with post increment

                    offset,s        stack pointer indexed addressing
                                      0 <= offset <= 255   --- byte mode
                                    256 <= offset <= 65535 --- word mode
                                    (an externally defined offset uses the
                                     word mode)

                    ext             extended addressing

                    label           branch label

            The terms data, dir, offset, and ext may all be expressions.

                 Note that not all addressing modes are valid with every in-
            struction, refer to the 68HC08 technical data for valid modes.

            M.2.1  Control Instructions

                    clc             cli             daa             div
                    mul             nop             nsa             psha
                    pshh            pshx            pula            pulh
                    pulx            rsp             rti             rts
                    sec             sei             stop            swi
                    tap             tax             tpa             tsx
                    txa             txs             wait

            M.2.2  Bit Manipulation Instructions

                    brset   #data,*dir,label
                    brclr   #data,*dir,label

                    bset    #data,*dir
                    bclr    #data,*dir

            AS6808 ASSEMBLER                                        PAGE M-3
            68HC08 INSTRUCTION SET

            M.2.3  Branch Instructions

                    bra     label           brn     label
                    bhi     label           bls     label
                    bcc     label           bcs     label
                    bne     label           beq     label
                    bhcc    label           bhcs    label
                    bpl     label           bmi     label
                    bmc     label           bms     label
                    bil     label           bih     label
                    bsr     label           bge     label
                    blt     label           bgt     label
                    ble     label

            M.2.4  Complex Branch Instructions

                    cbeqa   [],label
                    cbeqx   [],label
                    cbeq    [],label
                    dbnza   label
                    dbnzx   label
                    dbnz    [],label

            AS6808 ASSEMBLER                                        PAGE M-4
            68HC08 INSTRUCTION SET

            M.2.5  Read-Modify-Write Instructions

                    nega                    negx
                    neg     []

                    coma                    comx
                    com     []

                    lsra                    lsrx
                    lsr     []

                    rora                    rorx
                    ror     []

                    asra                    asrx
                    asr     []

                    asla                    aslx
                    asl     []

                    lsla                    lslx
                    lsl     []

                    rola                    rolx
                    rol     []

                    deca                    decx
                    dec     []

                    inca                    incx
                    inc     []

                    tsta                    tstx
                    tst     []

                    clra                    clrx
                    clr     []              clrh

                    aix     #data

                    ais     #data

            AS6808 ASSEMBLER                                        PAGE M-5
            68HC08 INSTRUCTION SET

            M.2.6  Register\Memory Instructions

                    sub     []              cmp     []
                    sbc     []              cpx     []
                    and     []              bit     []
                    lda     []              sta     []
                    eor     []              adc     []
                    ora     []              add     []
                    ldx     []              stx     []

            M.2.7  Double Operand Move Instruction

                    mov     [],[]

            M.2.8  16-Bit  Index Register Instructions

                    cphx    []
                    ldhx    []
                    sthx    []

            M.2.9  Jump and Jump to Subroutine Instructions

                    jmp     []              jsr     []

                                       APPENDIX N

                                    AS6809 ASSEMBLER

            N.1  6809 REGISTER SET

            The following is a list of the 6809 registers used by AS6809:

                    a,b     -       8-bit accumulators
                    d       -       16-bit accumulator
                    x,y     -       index registers
                    s,u     -       stack pointers
                    pc      -       program counter
                    cc      -       condition code
                    dp      -       direct page

            N.2  6809 INSTRUCTION SET

                 The  following tables list all 6809 mnemonics recognized by
            the AS6809 assembler.  The designation [] refers to  a  required
            addressing  mode  argument.   The  following  list specifies the
            format for each addressing mode supported by AS6809:

                    #data           immediate data
                                    byte or word data

                    *dir            direct page addressing
                                    (see .setdp directive)
                                    0 <= dir <= 255

                    label           branch label

                    r,r1,r2         registers
                                    cc,a,b,d,dp,x,y,s,u,pc

                    ,-x     ,--x    register indexed
                                    autodecrement

            AS6809 ASSEMBLER                                        PAGE N-2
            6809 INSTRUCTION SET

                    ,x+     ,x++    register indexed
                                    autoincrement

                    ,x              register indexed addressing
                                    zero offset

                    offset,x        register indexed addressing
                                       -16 <= offset <= 15    ---  5-bit
                                      -128 <= offset <= -17   ---  8-bit
                                        16 <= offset <= 127   ---  8-bit
                                    -32768 <= offset <= -129  --- 16-bit
                                       128 <= offset <= 32767 --- 16-bit
                                    (external definition of offset
                                     uses 16-bit mode)

                    a,x             accumulator offset indexed addressing

                    ext             extended addressing

                    ext,pc          pc addressing ( pc <- pc + ext )

                    ext,pcr         pc relative addressing

                    [,--x]          register indexed indirect
                                    autodecrement

                    [,x++]          register indexed indirect
                                    autoincrement

                    [,x]            register indexed indirect addressing
                                    zero offset

                    [offset,x]      register indexed indirect addressing
                                      -128 <= offset <= 127   ---  8-bit
                                    -32768 <= offset <= -129  --- 16-bit
                                       128 <= offset <= 32767 --- 16-bit
                                    (external definition of offset
                                     uses 16-bit mode)

                    [a,x]           accumulator offset indexed
                                    indirect addressing

                    [ext]           extended indirect addressing

                    [ext,pc]        pc indirect addressing
                                    ( [pc <- pc + ext] )

                    [ext,pcr]       pc relative indirect addressing

            The  terms  data, dir, label, offset, and ext may all be expres-
            sions.

            AS6809 ASSEMBLER                                        PAGE N-3
            6809 INSTRUCTION SET

                 Note that not all addressing modes are valid with every in-
            struction, refer to the 6809 technical data for valid modes.

            N.2.1  Inherent Instructions

                    abx             daa
                    mul             nop
                    rti             rts
                    sex             swi
                    swi1            swi2
                    swi3            sync

            N.2.2  Short Branch Instructions

                    bcc     label           bcs     label
                    beq     label           bge     label
                    bgt     label           bhi     label
                    bhis    label           bhs     label
                    ble     label           blo     label
                    blos    label           bls     label
                    blt     label           bmi     label
                    bne     label           bpl     label
                    bra     label           brn     label
                    bvc     label           bvs     label
                    bsr     label

            N.2.3  Long Branch Instructions

                    lbcc    label           lbcs    label
                    lbeq    label           lbge    label
                    lbgt    label           lbhi    label
                    lbhis   label           lbhs    label
                    lble    label           lblo    label
                    lblos   label           lbls    label
                    lblt    label           lbmi    label
                    lbne    label           lbpl    label
                    lbra    label           lbrn    label
                    lbvc    label           lbvs    label
                    lbsr    label

            AS6809 ASSEMBLER                                        PAGE N-4
            6809 INSTRUCTION SET

            N.2.4  Single Operand Instructions

                    asla            aslb
                    asl     []

                    asra            asrb
                    asr     []

                    clra            clrb
                    clr     []

                    coma            comb
                    com     []

                    deca            decb
                    dec     []

                    inca            incb
                    inc     []

                    lsla            lslb
                    lsl     []

                    lsra            lsrb
                    lsr     []

                    nega            negb
                    neg     []

                    rola            rolb
                    rol     []

                    rora            rorb
                    ror     []

                    tsta            tstb
                    tst     []

            AS6809 ASSEMBLER                                        PAGE N-5
            6809 INSTRUCTION SET

            N.2.5  Double Operand Instructions

                    adca    []              adcb    []

                    adda    []              addb    []

                    anda    []              andb    []

                    bita    []              bitb    []

                    cmpa    []              cmpb    []

                    eora    []              eorb    []

                    lda     []              ldb     []

                    ora     []              orb     []

                    sbca    []              sbcb    []

                    sta     []              stb     []

                    suba    []              subb    []

            N.2.6  D-register Instructions

                    addd    []              subd    []
                    cmpd    []              ldd     []
                    std     []

            N.2.7  Index/Stack Register Instructions

                    cmps    []              cmpu    []
                    cmpx    []              cmpy    []

                    lds     []              ldu     []
                    ldx     []              ldy     []

                    leas    []              leau    []
                    leax    []              leay    []

                    sts     []              stu     []
                    stx     []              sty     []

                    pshs    r               pshu    r
                    puls    r               pulu    r

            AS6809 ASSEMBLER                                        PAGE N-6
            6809 INSTRUCTION SET

            N.2.8  Jump and Jump to Subroutine Instructions

                    jmp     []              jsr     []

            N.2.9  Register - Register Instructions

                    exg     r1,r2           tfr     r1,r2

            N.2.10  Condition Code Register Instructions

                    andcc   #data           orcc    #data
                    cwai    #data

            N.2.11  6800 Compatibility Instructions

                    aba             cba
                    clc             cli
                    clv             des
                    dex             ins
                    inx
                    ldaa    []      ldab    []
                    oraa    []      orab    []
                    psha            pshb
                    pula            pulb
                    sba             sec
                    sei             sev
                    staa    []      stab    []
                    tab             tap
                    tba             tpa
                    tsx             txs
                    wai

                                       APPENDIX O

                                    AS6811 ASSEMBLER

            O.1  68HC11 REGISTER SET

            The following is a list of the 68HC11 registers used by AS6811:

                    a,b     -       8-bit accumulators
                    d       -       16-bit accumulator
                    x,y     -       index registers

            O.2  68HC11 INSTRUCTION SET

                 The  following  tables list all 68HC11 mnemonics recognized
            by the AS6811 assembler.  The designation []  refers  to  a  re-
            quired  addressing  mode argument.  The following list specifies
            the format for each addressing mode supported by AS6811:

                    #data           immediate data
                                    byte or word data

                    *dir            direct page addressing
                                    (see .setdp directive)
                                    0 <= dir <= 255

                    ,x              register indirect addressing
                                    zero offset

                    offset,x        register indirect addressing
                                    0 <= offset <= 255

                    ext             extended addressing

                    label           branch label

            The terms data, dir, offset, and ext may all be expressions.

            AS6811 ASSEMBLER                                        PAGE O-2
            68HC11 INSTRUCTION SET

                 Note that not all addressing modes are valid with every in-
            struction, refer to the 68HC11 technical data for valid modes.

            O.2.1  Inherent Instructions

                    aba             abx
                    aby             cba
                    clc             cli
                    clv             daa
                    des             dex
                    dey             fdiv
                    idiv            ins
                    inx             iny
                    mul             nop
                    rti             rts
                    sba             sec
                    sei             sev
                    stop            swi
                    tab             tap
                    tba             tpa
                    tsx             txs
                    wai             xgdx
                    xgdy

                    psha            pshb
                    psh a           psh b
                    pshx            pshy
                    psh x           psh y

                    pula            pulb
                    pul a           pul b
                    pulx            puly
                    pul x           pul y

            O.2.2  Branch Instructions

                    bra     label           brn     label
                    bhi     label           bls     label
                    bcc     label           bhs     label
                    bcs     label           blo     label
                    bne     label           beq     label
                    bvc     label           bvs     label
                    bpl     label           bmi     label
                    bge     label           blt     label
                    bgt     label           ble     label
                    bsr     label

            AS6811 ASSEMBLER                                        PAGE O-3
            68HC11 INSTRUCTION SET

            O.2.3  Single Operand Instructions

                    asla            aslb            asld
                    asl a           asl b           asl d
                    asl     []

                    asra            asrb
                    asr a           asr b
                    asr     []

                    clra            clrb
                    clr a           clr b
                    clr     label

                    coma            comb
                    com a           com b
                    com     []

                    deca            decb
                    dec a           dec b
                    dec     []

                    inca            incb
                    inc a           inc b
                    inc     []

                    lsla            lslb            lsld
                    lsl a           lsl b           lsl d
                    lsl     []

                    lsra            lsrb            lsrd
                    lsr a           lsr b           lsr d
                    lsr     []

                    nega            negb
                    neg a           neg b
                    neg     []

                    rola            rolb
                    rol a           rol b
                    rol     []

                    rora            rorb
                    ror a           ror b
                    ror     []

                    tsta            tstb
                    tst a           tst b
                    tst     []

            AS6811 ASSEMBLER                                        PAGE O-4
            68HC11 INSTRUCTION SET

            O.2.4  Double Operand Instructions

                    adca    []              adcb    []
                    adc a   []              adc b   []

                    adda    []      addb    []      addd    []
                    add a   []      add b   []      add d   []

                    anda    []              andb    []
                    and a   []              and b   []

                    bita    []              bitb    []
                    bit a   []              bit b   []

                    cmpa    []              cmpb    []
                    cmp a   []              cmp b   []

                    eora    []              eorb    []
                    eor a   []              eor b   []

                    ldaa    []              ldab    []
                    lda a   []              lda b   []

                    oraa    []              orab    []
                    ora a   []              ora b   []

                    sbca    []              sbcb    []
                    sbc a   []              sbc b   []

                    staa    []              stab    []
                    sta a   []              sta b   []

                    suba    []      subb    []      subd    []
                    sub a   []      sub b   []      sub d   []

            O.2.5  Bit Manupulation Instructions

                    bclr    [],#data
                    bset    [],#data

                    brclr   [],#data,label
                    brset   [],#data,label

            AS6811 ASSEMBLER                                        PAGE O-5
            68HC11 INSTRUCTION SET

            O.2.6  Jump and Jump to Subroutine Instructions

                    jmp     []              jsr     []

            O.2.7  Long Register Instructions

                    cpx     []              cpy     []

                    ldd     []              lds     []
                    ldx     []              ldy     []

                    std     []              sts     []
                    stx     []              sty     []

                                       APPENDIX P

                                    AS6812 ASSEMBLER

            P.1  68HC12 REGISTER SET

            The following is a list of the 68HC12 registers used by AS6812:

                    a,b     -       8-bit accumulators
                    d       -       16-bit accumulator
                    x,y     -       index registers
                    sp,s    -       stack pointer
                    pc      -       program counter
                    ccr,cc  -       condition code register

            P.2  68HC12 INSTRUCTION SET

                 The  following  tables list all 68HC12 mnemonics recognized
            by the AS6812 assembler.  The designation []  refers  to  a  re-
            quired  addressing  mode argument.  The following list specifies
            the format for each addressing mode supported by AS6812:

                    #data           immediate data
                                    byte or word data

                    ext             extended addressing

                    pg              memory page number

                    *dir            direct page addressing
                                    (see .setdp directive)
                                    0 <= dir <= 255

                    label           branch label

                    r,r1,r2         registers
                                    ccr,a,b,d,x,y,sp,pc

            AS6812 ASSEMBLER                                        PAGE P-2
            68HC12 INSTRUCTION SET

                    -x      x-      register indexed, pre or
                    ,-x     ,x-     post autodecrement by 1

                    n,-x    n,x-    register indexed, pre or
                                    post autodecrement by 1 - 8

                    +x      x+      register indexed, pre or
                    ,+x     ,x+     post autoincrement by 1

                    n,+x    n,x+    register indexed, pre or
                                    post autoincrement by 1 - 8

                    offset,x        register indexed addressing
                                       -16 <= offset <= 15    ---  5-bit
                                      -256 <= offset <= -17   ---  9-bit
                                        16 <= offset <= 255   ---  9-bit
                                    -32768 <= offset <= -257  --- 16-bit
                                       256 <= offset <= 32767 --- 16-bit
                                    (external definition of offset
                                     uses 16-bit mode)

                    [offset,x]      register indexed indirect addressing
                                    -32768 <= offset <= 32767 --- 16-bit

                    [,x]            register indexed indirect addressing
                                    zero offset

                    a,x             accumulator offset indexed addressing

                    [d,x]           d accumulator offset indexed
                                    indirect addressing

            The  terms  data, dir, label, offset, and ext may all be expres-
            sions.

                 Note that not all addressing modes are valid with every in-
            struction, refer to the 68HC12 technical data for valid modes.

            AS6812 ASSEMBLER                                        PAGE P-3
            68HC12 INSTRUCTION SET

            P.2.1  Inherent Instructions

                    aba             bgnd            cba
                    daa             dex             dey
                    ediv            edivs           emul
                    emuls           fdiv            idiv
                    idivs           inx             iny
                    mem             mul             nop
                    psha            pshb            pshc
                    pshd            pshx            pshy
                    pula            pulb            pulc
                    puld            pulx            puly
                    rev             revw            rtc
                    rti             rts             sba
                    stop            swi             tab
                    tba             wai             wav
                    wavr

            P.2.2  Short Branch Instructions

                    bcc     label           bcs     label
                    beq     label           bge     label
                    bgt     label           bhi     label
                    bhis    label           bhs     label
                    ble     label           blo     label
                    blos    label           bls     label
                    blt     label           bmi     label
                    bne     label           bpl     label
                    bra     label           brn     label
                    bvc     label           bvs     label
                    bsr     label

            P.2.3  Long Branch Instructions

                    lbcc    label           lbcs    label
                    lbeq    label           lbge    label
                    lbgt    label           lbhi    label
                    lbhis   label           lbhs    label
                    lble    label           lblo    label
                    lblos   label           lbls    label
                    lblt    label           lbmi    label
                    lbne    label           lbpl    label
                    lbra    label           lbrn    label
                    lbvc    label           lbvs    label

            AS6812 ASSEMBLER                                        PAGE P-4
            68HC12 INSTRUCTION SET

            P.2.4  Branch on Decrement, Test, or Increment

                    dbeq    r,label         dbne    r,label
                    ibeq    r,label         ibne    r,label
                    tbeq    r,label         tbne    r,label

            P.2.5  Bit Clear and Set Instructions

                    bclr    [],#data
                    bset    [],#data

            P.2.6  Branch on Bit Clear or Set

                    brclr   [],#data,label
                    brset   [],#data,label

            AS6812 ASSEMBLER                                        PAGE P-5
            68HC12 INSTRUCTION SET

            P.2.7  Single Operand Instructions

                    asla            aslb
                    asl     []

                    asra            asrb
                    asr     []

                    clra            clrb
                    clr     []

                    coma            comb
                    com     []

                    deca            decb
                    dec     []

                    inca            incb
                    inc     []

                    lsla            lslb
                    lsl     []

                    lsra            lsrb
                    lsr     []

                    nega            negb
                    neg     []

                    rola            rolb
                    rol     []

                    rora            rorb
                    ror     []

                    tsta            tstb
                    tst     []

            AS6812 ASSEMBLER                                        PAGE P-6
            68HC12 INSTRUCTION SET

            P.2.8  Double Operand Instructions

                    adca    []              adcb    []

                    adda    []              addb    []

                    anda    []              andb    []

                    bita    []              bitb    []

                    cmpa    []              cmpb    []

                    eora    []              eorb    []

                    ldaa    []      <=>     lda     []

                    ldab    []      <=>     ldb     []

                    oraa    []      <=>     ora     []

                    orab    []      <=>     orb     []

                    sbca    []              sbcb    []

                    staa    []      <=>     sta     []

                    stab    []      <=>     stb     []

                    suba    []              subb    []

            P.2.9  Move Instructions

                    movb    [],[]           movw    [],[]

            P.2.10  D-register Instructions

                    addd    []              subd    []
                    cpd     []      <=>     cmpd    []
                    ldd     []              std     []

            AS6812 ASSEMBLER                                        PAGE P-7
            68HC12 INSTRUCTION SET

            P.2.11  Index/Stack Register Instructions

                    cps     []      <=>     cmps    []
                    cpx     []      <=>     cmpx    []
                    cpy     []      <=>     cmpy    []

                    lds     []
                    ldx     []              ldy     []

                    leas    []
                    leax    []              leay    []

                    sts     []
                    stx     []              sty     []

            P.2.12  Jump and Jump/Call to Subroutine Instructions

                    call    [],pg
                    jmp     []              jsr     []

            P.2.13  Other Special Instructions

                    emacs   []
                    emaxd   []              emaxm   []
                    emind   []              eminm   []
                    etbl    []
                    maxa    []              maxm    []
                    mina    []              minm    []
                    tbl     []              trap    #data

            P.2.14  Register - Register Instructions

                    exg     r1,r2           sex     r1,r2
                    tfr     r1,r2

            P.2.15  Condition Code Register Instructions

                    andcc   #data           orcc    #data

            AS6812 ASSEMBLER                                        PAGE P-8
            68HC12 INSTRUCTION SET

            P.2.16  M68HC11 Compatibility Mode Instructions

                    abx             aby             clc
                    cli             clv             des
                    ins             sec             sei
                    sev             tap             tpa
                    tsx             tsy             txs
                    tys             xgdx            xgdy

                                       APPENDIX Q

                                    AS6816 ASSEMBLER

            Q.1  68HC16 REGISTER SET

            The following is a list of the 68HC16 registers used by AS6816:

                    a,b     -       8-bit accumulators
                    d       -       16-bit accumulator
                    e       -       16-bit accumulator
                    x,y,z   -       index registers
                    k       -       address extension register
                    s       -       stack pointer
                    ccr     -       condition code

            Q.2  68HC16 INSTRUCTION SET

                 The  following  tables list all 68HC16 mnemonics recognized
            by the AS6816 assembler.  The designation []  refers  to  a  re-
            quired  addressing  mode argument.  The following list specifies
            the format for each addressing mode supported by AS6816:

                    #data           immediate data
                                    byte or word data

                    #xo,#yo         local immediate data (mac / rmac)

                    label           branch label

                    r               register
                                    ccr,a,b,d,e,x,y,z,s

                    ,x              zero offset register indexed addressing
                    ,x8
                    ,x16

                    offset,x        register indexed addressing

            AS6816 ASSEMBLER                                        PAGE Q-2
            68HC16 INSTRUCTION SET

                                         0 <= offset <= 255   ---  8-bit
                                    -32768 <= offset <= -1    --- 16-bit
                                       256 <= offset <= 32767 --- 16-bit
                                    (external definition of offset
                                     uses 16-bit mode)

                    offset,x8       unsigned 8-bit offset indexed addressing
                    offset,x16      signed 16-bit offset indexed addressing

                    e,x             accumulator offset indexed addressing

                    ext             extended addressing

                    bank            64K bank number (jmp / jsr)

            The  terms data, label, offset, bank, and ext may all be expres-
            sions.

                 Note that not all addressing modes are valid with every in-
            struction, refer to the 6816 technical data for valid modes.

            Q.2.1  Inherent Instructions

                    aba             abx             aby             abz
                    ace             aced            ade             adx
                    ady             adz             aex             aey
                    aez             bgnd            cba             daa
                    ediv            edivs           emul            emuls
                    fdiv            fmuls           idiv            ldhi
                    lpstop          mul             nop             psha
                    pshb            pshmac          pula            pulb
                    pulmac          rtr             rts             sba
                    sde             sted            swi             sxt
                    tab             tap             tba             tbek
                    tbsk            tbxk            tbyk            tbzk
                    tde             tdmsk           tdp             ted
                    tedm            tekb            tem             tmer
                    tmet            tmxed           tpa             tpd
                    tskb            tsx             tsy             tsz
                    txkb            txs             txy             txz
                    tykb            tys             tyx             tyz
                    tzkb            tzs             tzx             tzy
                    wai             xgab            xgde            xgdx
                    xgdy            xgdz            xgex            xgey
                    xgez

            AS6816 ASSEMBLER                                        PAGE Q-3
            68HC16 INSTRUCTION SET

            Q.2.2  Push/Pull Multiple Register Instructions

                    pshm    r,...           pulm    r,...

            Q.2.3  Short Branch Instructions

                    bcc     label           bcs     label
                    beq     label           bge     label
                    bgt     label           bhi     label
                    bhis    label           bhs     label
                    ble     label           blo     label
                    blos    label           bls     label
                    blt     label           bmi     label
                    bne     label           bpl     label
                    bra     label           brn     label
                    bvc     label           bvs     label
                    bsr     label

            Q.2.4  Long Branch Instructions

                    lbcc    label           lbcs    label
                    lbeq    label           lbge    label
                    lbgt    label           lbhi    label
                    lbhis   label           lbhs    label
                    lble    label           lblo    label
                    lblos   label           lbls    label
                    lblt    label           lbmi    label
                    lbne    label           lbpl    label
                    lbra    label           lbrn    label
                    lbvc    label           lbvs    label
                    lbsr    label

            Q.2.5  Bit Manipulation Instructions

                    bclr    [],#data
                    bset    [],#data

                    brclr   [],#data,label
                    brset   [],#data,label

            AS6816 ASSEMBLER                                        PAGE Q-4
            68HC16 INSTRUCTION SET

            Q.2.6  Single Operand Instructions

                    asla                    aslb
                    asld                    asle
                    aslm
                    asl     []              aslw    []

                    asra                    asrb
                    asrd                    asre
                    asrm
                    asr     []              asrw    []

                    clra                    clrb
                    clrd                    clre
                                            clrm
                    clr     []              clrw    []

                    coma                    comb
                    comd                    come
                    com     []              comw    []

                    deca                    decb
                    dec     []              decw    []

                    inca                    incb
                    inc     []              incw    []

                    lsla                    lslb
                    lsld                    lsle
                    lslm
                    lsl     []              lslw    []

                    lsra                    lsrb
                    lsrd                    lsre
                    lsr     []              lsrw    []

                    nega                    negb
                    negd                    nege
                    neg     []              negw    []

                    rola                    rolb
                    rold                    role
                    rol     []              rolw    []

                    rora                    rorb
                    rord                    rore
                    ror     []              rorw    []

                    tsta                    tstb
                    tsta                    tste
                    tst     []              tstw    []

            AS6816 ASSEMBLER                                        PAGE Q-5
            68HC16 INSTRUCTION SET

            Q.2.7  Double Operand Instructions

                    adca    []              adcb    []
                    adcd    []              adce    []

                    adda    []              addb    []
                    addd    []              adde    []

                    anda    []              andb    []
                    andd    []              ande    []

                    bita    []              bitb    []

                    cmpa    []              cmpb    []
                    cpd     []              cpe     []

                    eora    []              eorb    []
                    eord    []              eore    []

                    ldaa    []              ldab    []
                    ldd     []              lde     []

                    oraa    []              orab    []
                    ord     []              ore     []

                    sbca    []              sbcb    []
                    sbcd    []              sbce    []

                    staa    []              stab    []
                    std     []              ste     []

                    suba    []              subb    []
                    subd    []              sube    []

            Q.2.8  Index/Stack Register Instructions

                    cps     []              cpx     []
                    cpy     []              cpz     []

                    lds     []              ldx     []
                    ldy     []              ldz     []

                    sts     []              stx     []
                    sty     []              stz     []

            AS6816 ASSEMBLER                                        PAGE Q-6
            68HC16 INSTRUCTION SET

            Q.2.9  Jump and Jump to Subroutine Instructions

                    jmp     bank,[]         jsr     bank,[]

            Q.2.10  Condition Code Register Instructions

                    andp    #data           orp     #data

            Q.2.11  Multiply and Accumulate Instructions

                    mac     #data           rmac    #data
                    mac     #xo,#yo         rmac    #xo,#yo

                                       APPENDIX R

                                    AS8051 ASSEMBLER

            R.1  ACKNOWLEDGMENT

                 Thanks  to  John Hartman for his contribution of the AS8051
            cross assembler.

                    John L. Hartman
                    jhartman at compuserve dot com
                    noice at noicedebugger dot com

            R.2  8051 REGISTER SET

            The following is a list of the 8051 registers used by AS8051:

                    a,b             -       8-bit accumulators
                    r0,r1,r2,r3     -       8-bit registers
                    r4,r5,r6,r7
                    dptr            -       data pointer
                    sp              -       stack pointer
                    pc              -       program counter
                    psw             -       status word
                    c               -       carry (bit in status word)

            AS8051 ASSEMBLER                                        PAGE R-2
            8051 REGISTER SET

            R.3  8051 INSTRUCTION SET

                 The  following tables list all 8051 mnemonics recognized by
            the AS8051 assembler.  The following list specifies  the  format
            for each addressing mode supported by AS8051:

                    #data           immediate data
                                    byte or word data

                    r,r1,r2         register r0,r1,r2,r3,r4,r5,r6, or r7

                    @r              indirect on register r0 or r1
                    @dptr           indirect on data pointer
                    @a+dptr         indirect on accumulator
                                    plus data pointer
                    @a+pc           indirect on accumulator
                                    plus program counter

                    addr            direct memory address

                    bitaddr         bit address

                    label           call or jump label

            The terms data, addr, bitaddr, and label may all be expressions.

                 Note that not all addressing modes are valid with every in-
            struction.  Refer to the 8051 technical data for valid modes.

            R.3.1  Inherent Instructions

                    nop

            AS8051 ASSEMBLER                                        PAGE R-3
            8051 INSTRUCTION SET

            R.3.2  Move Instructions

                    mov     a,#data         mov     a,addr
                    mov     a,r             mov     a,@r

                    mov     r,#data         mov     r,addr
                    mov     r,a

                    mov     addr,a          mov     addr,#data
                    mov     addr,r          mov     addr,@r
                    mov     addr1,addr2     mov     bitaddr,c

                    mov     @r,#data        mov     @r,addr
                    mov     @r,a

                    mov     c,bitaddr
                    mov     dptr,#data

                    movc    a,@a+dptr       movc    a,@a+pc
                    movx    a,@dptr         movx    a,@r
                    movx    @dptr,a         movx    @r,a

            R.3.3  Single Operand Instructions

                    clr     a               clr     c
                    clr     bitaddr
                    cpl     a               cpl     c
                    cpl     bitaddr
                    setb    c               setb    bitaddr

                    da      a
                    rr      a               rrc     a
                    rl      a               rlc     a
                    swap    a

                    dec     a               dec     r
                    dec     @r
                    inc     a               inc     r
                    inc     dptr            inc     @r

                    div     ab              mul     ab

                    pop     addr            push    addr

            AS8051 ASSEMBLER                                        PAGE R-4
            8051 INSTRUCTION SET

            R.3.4  Two Operand Instructions

                    add     a,#data         add     a,addr
                    add     a,r             add     a,@r
                    addc    a,#data         addc    a,addr
                    addc    a,r             addc    a,@r
                    subb    a,#data         subb    a,addr
                    subb    a,r             subb    a,@r
                    orl     a,#data         orl     a,addr
                    orl     a,r             orl     a,@r
                    orl     addr,a          orl     addr,#data
                    orl     c,bitaddr       orl     c,/bitaddr
                    anl     a,#data         anl     a,addr
                    anl     a,r             anl     a,@r
                    anl     addr,a          anl     addr,#data
                    anl     c,bitaddr       anl     c,/bitaddr
                    xrl     a,#data         xrl     a,addr
                    xrl     a,r             xrl     a,@r
                    xrl     addr,a          xrl     addr,#data
                    xrl     c,bitaddr       xrl     c,/bitaddr
                    xch     a,addr          xch     a,r
                    xch     a,@r            xchd    a,@r

            R.3.5  Call and Return Instructions

                    acall   label           lcall   label
                    ret                     reti
                    in      data
                    out     data
                    rst     data

            R.3.6  Jump Instructions

                    ajmp    label
                    cjne    a,#data,label   cjne    a,addr,label
                    cjne    r,#data,label   cjne    @r,#data,label
                    djnz    r,label         djnz    addr,label
                    jbc     bitadr,label
                    jb      bitadr,label    jnb     bitadr,label
                    jc      label           jnc     label
                    jz      label           jnz     label
                    jmp     @a+dptr
                    ljmp    label           sjmp    label

            AS8051 ASSEMBLER                                        PAGE R-5
            8051 INSTRUCTION SET

            R.3.7  Predefined Symbols:  SFR Map

                            --------- 4 Bytes ----------
                            ----    ----    ----    ----
                    FC                                          FF
                    F8                                          FB
                    F4                                          F7
                    F0      B                                   F3
                    EC                                          EF
                    E8                                          EB
                    E4                                          E7
                    E0      ACC                                 E3
                    DC                                          DF
                    D8                                          DB
                    D4                                          D7
                    D0      PSW                                 D3
                    CC   [  TL2     TH2                     ]   CF
                    C8   [  T2CON           RCAP2L  RCAP2H  ]   CB
                    C4                                          C7
                    C0                                          C3
                    BC                                          BF
                    B8      IP                                  BB
                    B4                                          B7
                    B0      P3                                  B3
                    AC                                          AF
                    A8      IE                                  AB
                    A4                                          A7
                    A0      P2                                  A3
                    9C                                          9F
                    98      SCON    SBUF                        9B
                    94                                          97
                    90      P1                                  93
                    8C      TH0     TH1                         8F
                    88      TCON    TMOD    TL0     TL1         8B
                    84                              PCON        87
                    80      P0      SP      DPL     DPH         83

                    [...] Indicates Resident in 8052, not 8051

            AS8051 ASSEMBLER                                        PAGE R-6
            8051 INSTRUCTION SET

            R.3.8  Predefined Symbols:  SFR Bit Addresses

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                    FC                                          FF
                    F8                                          FB
                    F4      B.4     B.5     B.6     B.7         F7
                    F0      B.0     B.1     B.2     B.3         F3
                    EC                                          EF
                    E8                                          EB
                    E4      ACC.4   ACC.5   ACC.6   ACC.7       E7
                    E0      ACC.0   ACC.1   ACC.2   ACC.3       E3
                    DC                                          DF
                    D8                                          DB
                    D4      PSW.4   PSW.5   PSW.6   PSW.7       D7
                    D0      PSW.0   PSW.1   PSW.2   PSW.3       D3
                    CC   [  T2CON.4 T2CON.5 T2CON.6 T2CON.7 ]   CF
                    C8   [  T2CON.0 T2CON.1 T2CON.2 T2CON.3 ]   CB
                    C4                                          C7
                    C0                                          C3
                    BC      IP.4    IP.5    IP.6    IP.7        BF
                    B8      IP.0    IP.1    IP.2    IP.3        BB
                    B4      P3.4    P3.5    P3.6    P3.7        B7
                    B0      P3.0    P3.1    P3.2    P3.3        B3
                    AC      IE.4    IE.5    EI.6    IE.7        AF
                    A8      IE.0    IE.1    IE.2    IE.3        AB
                    A4      P2.4    P2.5    P2.6    P2.7        A7
                    A0      P2.0    P2.1    P2.2    P2.3        A3
                    9C      SCON.4  SCON.5  SCON.6  SCON.7      9F
                    98      SCON.0  SCON.1  SCON.2  SCON.3      9B
                    94      P1.4    P1.5    P1.6    P1.7        97
                    90      P1.0    P1.1    P1.2    P1.3        93
                    8C      TCON.4  TCON.5  TCON.6  TCON.7      8F
                    88      TCON.0  TCON.1  TCON.2  TCON.3      8B
                    84      P0.4    P0.5    P0.6    P0.7        87
                    80      P0.0    P0.1    P0.2    P0.3        83

                    [...] Indicates Resident in 8052, not 8051

            AS8051 ASSEMBLER                                        PAGE R-7
            8051 INSTRUCTION SET

            R.3.9  Predefined Symbols:  Control Bits

                            ---------- 4 BITS ----------
                            ----    ----    ----    ----
                    FC                                          FF
                    F8                                          FB
                    F4                                          F7
                    F0                                          F3
                    EC                                          EF
                    E8                                          EB
                    E4                                          E7
                    E0                                          E3
                    DC                                          DF
                    D8                                          DB
                    D4      RS1     F0      AC      CY          D7
                    D0      P               OV      RS0         D3
                    CC   [  TLCK    RCLK    EXF2    TF2     ]   CF
                    C8   [  CPRL2   CT2     TR2     EXEN2   ]   CB
                    C4                                          C7
                    C0                                          C3
                    BC      PS      PT2                         BF
                    B8      PX0     PT0     PX1     PT1         BB
                    B4                                          B7
                    B0      RXD     TXD     INT0    INT1        B3
                    AC      ES      ET2             EA          AF
                    A8      EX0     ET0     EX1     ET1         AB
                    A4                                          A7
                    A0                                          A3
                    9C      REN     SM2     SM1     SM0         9F
                    98      RI      TI      RB8     TB8         9B
                    94                                          97
                    90                                          93
                    8C      TR0     TF0     TR1     TF1         8F
                    88      IT0     IE0     IT1     IE1         8B
                    84                                          87
                    80                                          83

                    [...] Indicates Resident in 8052, not 8051

                                       APPENDIX S

                                    AS8085 ASSEMBLER

            S.1  8085 REGISTER SET

            The  following  is  a  list  of  the 8080/8085 registers used by
            AS8085:

                    a,b,c,d,e,h,l   -       8-bit accumulators
                    m               -       memory through (hl)
                    sp              -       stack pointer
                    psw             -       status word

            S.2  8085 INSTRUCTION SET

                 The  following  tables  list all 8080/8085 mnemonics recog-
            nized by the AS8085 assembler.  The following list specifies the
            format for each addressing mode supported by AS8085:

                    #data           immediate data
                                    byte or word data

                    r,r1,r2         register or register pair
                                    psw,a,b,c,d,e,h,l
                                    bc,de,hl,sp,pc

                    m               memory address using (hl)

                    addr            direct memory addressing

                    label           call or jump label

            The terms data, m, addr, and label may be expressions.

                 Note that not all addressing modes are valid with every in-
            struction, refer to  the  8080/8085  technical  data  for  valid
            modes.

            AS8085 ASSEMBLER                                        PAGE S-2
            8085 INSTRUCTION SET

            S.2.1  Inherent Instructions

                    cma             cmc
                    daa             di
                    ei              hlt
                    nop             pchl
                    ral             rar
                    ret             rim
                    rrc             rlc
                    sim             sphl
                    stc             xchg
                    xthl

            S.2.2  Register/Memory/Immediate Instructions

                    adc     r       adc     m       aci     #data
                    add     r       add     m       adi     #data
                    ana     r       ana     m       ani     #data
                    cmp     r       cmp     m       cpi     #data
                    ora     r       ora     m       ori     #data
                    sbb     r       sbb     m       sbi     #data
                    sub     r       sub     m       sui     #data
                    xra     r       xra     m       xri     #data

            S.2.3  Call and Return Instructions

                    cc      label           rc
                    cm      label           rm
                    cnc     label           rnc
                    cnz     label           rnz
                    cp      label           rp
                    cpe     label           rpe
                    cpo     label           rpo
                    cz      label           rz
                    call    label

            S.2.4  Jump Instructions

                    jc      label
                    jm      label
                    jnc     label
                    jnz     label
                    jp      label
                    jpe     label
                    jpo     label
                    jz      label
                    jmp     label

            AS8085 ASSEMBLER                                        PAGE S-3
            8085 INSTRUCTION SET

            S.2.5  Input/Output/Reset Instructions

                    in      data
                    out     data
                    rst     data

            S.2.6  Move Instructions

                    mov     r1,r2
                    mov     r,m
                    mov     m,r

                    mvi     r,#data
                    mvi     m,#data

            S.2.7  Other Instructions

                    dcr     r               dcr     m
                    inr     r               inr     m

                    dad     r               dcx     r
                    inx     r               ldax    r
                    pop     r               push    r
                    stax    r

                    lda     addr            lhld    addr
                    shld    addr            sta     addr

                    lxi     r,#data

                                       APPENDIX T

                                    AS6500 ASSEMBLER

            T.1  ACKNOWLEDGMENT

                 Thanks  to  Marko Makela for his contribution of the AS6500
            cross assembler.

                    Marko Makela
                    Sillitie 10 A
                    01480 Vantaa
                    Finland
                    Internet: Marko dot Makela at Helsinki dot Fi
                    EARN/BitNet: msmakela at finuh

                 Several  additions  and modifications were made to his code
            to support the following families of 6500 processors:

                    (1)     650X and 651X processor family
                    (2)     65F11 and 65F12 processor family
                    (3)     65C00/21 and 65C29 processor family
                    (4)     65C02, 65C102, and 65C112 processor family

                 The instruction syntax of this cross assembler contains two
            peculiarities:  (1) the addressing indirection is denoted by the
            square  brackets  []  and (2) the `bbrx' and `bbsx' instructions
            are written `bbr0 memory,label'.

            AS6500 ASSEMBLER                                        PAGE T-2
            6500 REGISTER SET

            T.2  6500 REGISTER SET

            The following is a list of the 6500 registers used by AS6500:

                    a       -       8-bit accumulator
                    x,y     -       index registers

            T.3  6500 INSTRUCTION SET

                 The  following tables list all 6500 family mnemonics recog-
            nized by the AS6500 assembler.  The designation [] refers  to  a
            required addressing mode argument.  The following list specifies
            the format for each addressing mode supported by AS6500:

                    #data           immediate data
                                    byte or word data

                    *dir            direct page addressing
                                    (see .setdp directive)
                                    0 <= dir <= 255

                    offset,x        indexed addressing
                    offset,y        indexed addressing
                                    address = (offset + (x or y))

                    [offset,x]      pre-indexed indirect addressing
                                    0 <= offset <= 255
                                    address = contents of location
                                        (offset + (x or y)) mod 256

                    [offset],y      post-indexed indirect addressing
                                    address = contents of location at offset
                                        plus the value of the y register

                    [address]       indirect addressing

                    ext             extended addressing

                    label           branch label

                    address,label   direct page memory location
                                    branch label
                                    bbrx and bbsx instruction addressing

            The  terms data, dir, offset, address, ext, and label may all be
            expressions.

                 Note that not all addressing modes are valid with every in-
            struction, refer to the 65xx technical data for valid modes.

            AS6500 ASSEMBLER                                        PAGE T-3
            6500 INSTRUCTION SET

            T.3.1  Processor Specific Directives

                 The  AS6500 cross assembler has four (4) processor specific
            assembler directives which  define  the  target  65xx  processor
            family:

                    .r6500          Core 650X and 651X family (default)
                    .r65f11         Core plus 65F11 and 65F12
                    .r65c00         Core plus 65C00/21 and 65C29
                    .r65c02         Core plus 65C02, 65C102, and 65C112

            T.3.2  65xx Core Inherent Instructions

                    brk                     clc
                    cld                     cli
                    clv                     dex
                    dey                     inx
                    iny                     nop
                    pha                     php
                    pla                     plp
                    rti                     rts
                    sec                     sed
                    sei                     tax
                    tay                     tsx
                    txa                     txs
                    tya

            T.3.3  65xx Core Branch Instructions

                    bcc     label           bhs     label
                    bcs     label           blo     label
                    beq     label           bmi     label
                    bne     label           bpl     label
                    bvc     label           bvs     label

            T.3.4  65xx Core Single Operand Instructions

                    asl     []
                    dec     []
                    inc     []
                    lsr     []
                    rol     []
                    ror     []

            AS6500 ASSEMBLER                                        PAGE T-4
            6500 INSTRUCTION SET

            T.3.5  65xx Core Double Operand Instructions

                    adc     []
                    and     []
                    bit     []
                    cmp     []
                    eor     []
                    lda     []
                    ora     []
                    sbc     []
                    sta     []

            T.3.6  65xx Core Jump and Jump to Subroutine Instructions

                    jmp     []              jsr     []

            T.3.7  65xx Core Miscellaneous X and Y Register Instructions

                    cpx     []
                    cpy     []
                    ldx     []
                    stx     []
                    ldy     []
                    sty     []

            AS6500 ASSEMBLER                                        PAGE T-5
            6500 INSTRUCTION SET

            T.3.8  65F11 and 65F12 Specific Instructions

                    bbr0    [],label                bbr1    [],label
                    bbr2    [],label                bbr3    [],label
                    bbr4    [],label                bbr5    [],label
                    bbr6    [],label                bbr7    [],label

                    bbs0    [],label                bbs1    [],label
                    bbs2    [],label                bbs3    [],label
                    bbs4    [],label                bbs5    [],label
                    bbs6    [],label                bbs7    [],label

                    rmb0    []                      rmb1    []
                    rmb2    []                      rmb3    []
                    rmb4    []                      rmb5    []
                    rmb6    []                      rmb7    []

                    smb0    []                      smb1    []
                    smb2    []                      smb3    []
                    smb4    []                      smb5    []
                    smb6    []                      smb7    []

            T.3.9  65C00/21 and 65C29 Specific Instructions

                    bbr0    [],label                bbr1    [],label
                    bbr2    [],label                bbr3    [],label
                    bbr4    [],label                bbr5    [],label
                    bbr6    [],label                bbr7    [],label

                    bbs0    [],label                bbs1    [],label
                    bbs2    [],label                bbs3    [],label
                    bbs4    [],label                bbs5    [],label
                    bbs6    [],label                bbs7    [],label

                    bra     label

                    phx                             phy
                    plx                             ply

                    rmb0    []                      rmb1    []
                    rmb2    []                      rmb3    []
                    rmb4    []                      rmb5    []
                    rmb6    []                      rmb7    []

                    smb0    []                      smb1    []
                    smb2    []                      smb3    []
                    smb4    []                      smb5    []
                    smb6    []                      smb7    []

            AS6500 ASSEMBLER                                        PAGE T-6
            6500 INSTRUCTION SET

            T.3.10  65C02, 65C102, and 65C112 Specific Instructions

                    bbr0    [],label                bbr1    [],label
                    bbr2    [],label                bbr3    [],label
                    bbr4    [],label                bbr5    [],label
                    bbr6    [],label                bbr7    [],label

                    bbs0    [],label                bbs1    [],label
                    bbs2    [],label                bbs3    [],label
                    bbs4    [],label                bbs5    [],label
                    bbs6    [],label                bbs7    [],label

                    bra     label

                    phx                             phy
                    plx                             ply

                    rmb0    []                      rmb1    []
                    rmb2    []                      rmb3    []
                    rmb4    []                      rmb5    []
                    rmb6    []                      rmb7    []

                    smb0    []                      smb1    []
                    smb2    []                      smb3    []
                    smb4    []                      smb5    []
                    smb6    []                      smb7    []

                    stz     []
                    trb     []
                    tsb     []

                 Additional addressing modes for the following core instruc-
            tions are also available with the 65C02, 65C102, and 65C112 pro-
            cessors.

                    adc     []                      and     []
                    cmp     []                      eor     []
                    lda     []                      ora     []
                    sbc     []                      sta     []

                    bit     []                      jmp     []

                    dec                             inc

                                       APPENDIX U

                                     AS740 ASSEMBLER

            U.1  ACKNOWLEDGMENT

                 Thanks  to  Uwe  Steller  for his contribution of the AS740
            cross assembler.

                    Uwe Stellar
                    Uwe dot Steller at t-online dot de

                 The  instruction  syntax  of  this cross assembler uses the
            square brackets [] to denote addressing indirection.

            U.2  740 REGISTER SET

            The following is a list of the 740 registers used by AS740:

                    a       -       8-bit accumulator
                    x,y     -       index registers

            U.3  740 INSTRUCTION SET

                 The  following  tables list all 740 family mnemonics recog-
            nized by the AS740 assembler.  The designation []  refers  to  a
            required addressing mode argument.  The following list specifies
            the format for each addressing mode supported by AS740:

                    #data           immediate data byte

                    #data,*zp       immediate data to zero page

                    a               accumulator addressing

            AS740 ASSEMBLER                                         PAGE U-2
            740 INSTRUCTION SET

                    *zp             zero page addressing
                                    (see .setdp directive)
                                    0 <= dir <= 255

                    *zp,x           zero page x addressing
                    *zp,y           zero page y addressing
                                    address = (offset + (x or y))

                    [*zp,x]         indirect x addressing
                                    0 <= offset <= 255
                                    address = 2 bytes at location
                                        [(offset + (x or y)) mod 256]

                    [*zp],y         indirect y addressing
                                    address = 2 byte value at offset
                                        plus the value of the y register

                    abs             absolute addressing (2 byte)
                    abs,x           absolute x addressing (2 byte + x)
                    abs,y           absolute y addressing (2 byte + y)

                    [abs]           indirect addressing (2 byte)

                    label           branch label

                    \special        low order byte of address 0xFFnn

                    BIT#,*zp        bit set/clear zero page
                    BIT#,A          bit set/clear accumulator

                    BIT#,*zp,label  branch on bit set/clear in zero page
                    BIT#,A,label    branch on bit set/clear in accumulator

            The terms data, zp, abs, BIT , special, and label may all be ex-
            pressions.

                 Note that not all addressing modes are valid with every in-
            struction, refer to the 740 technical data for valid modes.

            AS740 ASSEMBLER                                         PAGE U-3
            740 INSTRUCTION SET

            U.3.1  Inherent Instructions

                    brk                     clc
                    cld                     cli
                    clt                     clv
                    dex                     dey
                    inx                     iny
                    nop                     pha
                    php                     pla
                    plp                     rti
                    rts                     sec
                    sed                     sei
                    set                     stp
                    tax                     tay
                    tsx                     txa
                    txs                     tya
                    wit

            U.3.2  Branch Instructions

                    bcc     label           bhs     label
                    bcs     label           blo     label
                    beq     label           bmi     label
                    bne     label           bpl     label
                    bvc     label           bvs     label
                    bra     label

            U.3.3  Single Operand Instructions

                    asl     []
                    dec     []
                    inc     []
                    lsr     []
                    rol     []
                    ror     []

            AS740 ASSEMBLER                                         PAGE U-4
            740 INSTRUCTION SET

            U.3.4  Double Operand Instructions

                    adc     []
                    and     []
                    bit     []
                    cmp     []
                    eor     []
                    lda     []
                    ora     []
                    sbc     []
                    sta     []

            U.3.5  Jump and Jump to Subroutine Instructions

                    jmp     []              jsr     []

            U.3.6  Miscellaneous X and Y Register Instructions

                    cpx     []
                    cpy     []
                    ldx     []
                    stx     []
                    ldy     []
                    sty     []

            U.3.7  Bit Instructions

                    bit     []
                    bbc     BIT#,[],label           bbs     BIT#,[],label
                    clb     BIT#,[]                 seb     BIT#,[]

            U.3.8  Other Instructions

                    div     []                      mul     []
                    ldm     #imm,[]                 com     []
                    tst     []                      rrf     []

                                       APPENDIX V

                                    AS1802 ASSEMBLER

            V.1  ACKNOWLEDGMENT

                 Thanks  to  Shujen  Chen for his contribution of the AS1802
            cross assembler.

                    Shujen Chen
                    DeVry University
                    Tinley Park, IL
                    schen at tp dot devry dot edu

            V.2  1802 REGISTER SET

            The following is a list of the 1802 registers used by AS1802:

                    r0-r15  -       8-bit registers
                    sp      -       register r2
                    pc      -       register r3
                    call    -       register r4
                    return  -       register r5
                    argr    -       register r6

            V.3  1802 INSTRUCTION SET

                 The  following tables list all 1802 mnemonics recognized by
            the AS1802 assembler.  The designation [] refers to  a  required
            addressing  mode  argument.   The  following  list specifies the
            format for each addressing mode supported by AS1802:

                    #data           immediate data
                                    byte or word data

                    expr            expression

            AS1802 ASSEMBLER                                        PAGE V-2
            1802 INSTRUCTION SET

                    Rn              register addressing

                    label           branch label

            The terms data, expr, and label may be expressions.

                 Note that not all addressing modes are valid with every in-
            struction, refer to the 1802 technical data for valid modes.

            V.3.1  1802 Inherent Instructions

                    adc             add             and
                    dis             idl             irx
                    ldx             ldxa            lsdf
                    lsie            lskp            lsnf
                    lsnq            lsnz            lsq
                    lsz             mark            nop
                    or              req             ret
                    rshl            rshr            sav
                    sd              sdb             seq
                    shl             shlc            shr
                    shrc            skp             sm
                    smb             stxd            xor

            V.3.2  1802 Short Branch Instructions

                    b1      label           b2      label
                    b3      label           b4      label
                    bdf     label           bge     label
                    bl      label           bm      label
                    bn1     label           bn2     label
                    bn3     label           bn4     label
                    bnf     label           bnq     label
                    bnz     label           bpz     label
                    bq      label           br      label
                    bz      label           nbr     label

            AS1802 ASSEMBLER                                        PAGE V-3
            1802 INSTRUCTION SET

            V.3.3  1802 Long Branch Instructions

                    lbdf    label           lbnf    label
                    lbnq    label           lbnz    label
                    lbq     label           lbr     label
                    lbz     label           nlbr    label

            V.3.4  1802 Immediate Instructions

                    adci    #data           adi     #data
                    ani     #data           ldi     #data
                    ori     #data           sdbi    #data
                    sdi     #data           smbi    #data
                    smi     #data           xri     #data

            V.3.5  1802 Register Instructions

                    dec     Rn              ghi     Rn
                    glo     Rn              inc     Rn
                    lda     Rn              ldn     Rn
                    phi     Rn              plo     Rn
                    sep     Rn              sex     Rn
                    str     Rn

            V.3.6  1802 Input and Output Instructions

                    inp     expr
                    out     expr

            AS1802 ASSEMBLER                                        PAGE V-4
            1802 INSTRUCTION SET

            V.3.7  CDP1802 COSMAC Microprocessor Instruction Set Summary

            ----------------------------------------------------------------
            |                                                              |
            |                                                              |
            |                             RCA                              |
            |                                                              |
            |               1     88888      000      22222                |
            |              11    8     8    0   0    2     2               |
            |               1    8     8   0   0 0        2                |
            |               1     88888    0  0  0     222                 |
            |               1    8     8   0 0   0    2                    |
            |               1    8     8    0   0    2                     |
            |              111    88888      000     2222222               |
            |                                                              |
            |    CDP1802 COSMAC Microprocessor Instruction Set Summary     |
            |                                                              |
            |                                                              |
            |                                                              |
            |                                                              |
            |Written by     Jonathan Bowen                                 |
            |               Programming Research Group                     |
            |               Oxford University Computing Laboratory         |
            |               8-11 Keble Road                                |
            |               Oxford OX1 3QD                                 |
            |               England                                        |
            |                                                              |
            |               Tel +44-865-273840                             |
            |                                                              |
            |Created        August 1981                                    |
            |Updated        April 1985                                     |
            |Issue          1.3                Copyright (C) J.P.Bowen 1985|
            ----------------------------------------------------------------

            AS1802 ASSEMBLER                                        PAGE V-5
            1802 INSTRUCTION SET

            ----------------------------------------------------------------
            |                                                              |
            |             CDP1802 COSMAC Microprocessor Pinout             |
            |                                                              |
            |                    _________    _________                    |
            |                  _|         \__/         |_                  |
            |       --> CLOCK |_|1                   40|_| Vdd             |
            |            ____  _|                      |_  ____            |
            |        --> WAIT |_|2                   39|_| XTAL -->        |
            |           _____  _|                      |_  ______          |
            |       --> CLEAR |_|3                   38|_| DMA IN <--      |
            |                  _|                      |_  _______         |
            |           <-- Q |_|4                   37|_| DMA OUT <--     |
            |                  _|                      |_  _________       |
            |         <-- SC1 |_|5                   36|_| INTERRUPT <--   |
            |                  _|                      |_  ___             |
            |         <-- SC0 |_|6                   35|_| MWR <--         |
            |             ___  _|                      |_                  |
            |         <-- MRD |_|7                   34|_| TPA -->         |
            |                  _|                      |_                  |
            |      <--> BUS 7 |_|8                   33|_| TPB -->         |
            |                  _|                      |_                  |
            |      <--> BUS 6 |_|9                   32|_| MA7 -->         |
            |                  _|                      |_                  |
            |      <--> BUS 5 |_|10       1802       31|_| MA6 -->         |
            |                  _|                      |_                  |
            |      <--> BUS 4 |_|11                  30|_| MA5 -->         |
            |                  _|                      |_                  |
            |      <--> BUS 3 |_|12                  29|_| MA4 -->         |
            |                  _|                      |_                  |
            |      <--> BUS 2 |_|13                  28|_| MA3 -->         |
            |                  _|                      |_                  |
            |      <--> BUS 1 |_|14                  27|_| MA2 -->         |
            |                  _|                      |_                  |
            |      <--> BUS 0 |_|15                  26|_| MA1 -->         |
            |                  _|                      |_                  |
            |             Vcc |_|16                  25|_| MA0 -->         |
            |                  _|                      |_  ___             |
            |          <-- N2 |_|17                  24|_| EF1 <--         |
            |                  _|                      |_  ___             |
            |          <-- N1 |_|18                  23|_| EF2 <--         |
            |                  _|                      |_  ___             |
            |          <-- N0 |_|19                  22|_| EF3 <--         |
            |                  _|                      |_  ___             |
            |             Vss |_|20                  21|_| EF4 <--         |
            |                   |______________________|                   |
            |                                                              |
            |                                                              |
            ----------------------------------------------------------------

            AS1802 ASSEMBLER                                        PAGE V-6
            1802 INSTRUCTION SET

            ----------------------------------------------------------------
            |Mnem. |Op|F|Description                 |Notes                |
            |------+--+-+----------------------------+---------------------|
            |ADC   |74|*|Add with Carry              |{DF,D}=mx+D+DF       |
            |ADCI i|7C|*|Add with Carry Immediate    |{DF,D}=mp+D+DF,p=p+1 |
            |ADD   |F4|*|Add                         |{DF,D}=mx+D          |
            |ADI  i|FC|*|Add Immediate               |{DF,D}=mp+D,p=p+1    |
            |AND   |F2|*|Logical AND                 |D={mx}&D             |
            |ANI  i|FA|*|Logical AND Immediate       |D={mp}&D,p=p+1       |
            |B1   a|34|-|Branch if EF1               |If EF1=1 BR else NBR |
            |B2   a|35|-|Branch if EF2               |If EF2=1 BR else NBR |
            |B3   a|36|-|Branch if EF3               |If EF3=1 BR else NBR |
            |B4   a|37|-|Branch if EF4               |If EF4=1 BR else NBR |
            |BDF  a|33|-|Branch if DF                |If DF=1 BR else NBR  |
            |BGE  a|33|-|Branch if Greater or Equal  |See BDF              |
            |BL   a|38|-|Branch if Less              |See BNF BR else NBR  |
            |BM   a|38|-|Branch if Minus             |See BNF              |
            |BN1  a|3C|-|Branch if Not EF1           |If EF1=0 BR else NBR |
            |BN2  a|3D|-|Branch if Not EF2           |If EF2=0 BR else NBR |
            |BN3  a|3E|-|Branch if Not EF3           |If EF3=0 BR else NBR |
            |BN4  a|3F|-|Branch if Not EF4           |If EF4=0 BR else NBR |
            |BNF  a|38|-|Branch if Not DF            |If DF=0 BR else NBR  |
            |BNQ  a|39|-|Branch if Not Q             |If Q=0 BR else NBR   |
            |BNZ  a|3A|-|Branch if D Not Zero        |If D=1 BR else NBR   |
            |BPZ  a|33|-|Branch if Positive or Zero  |See BDF              |
            |BQ   a|31|-|Branch if Q                 |If Q=1 BR else NBR   |
            |BR   a|30|-|Branch                      |pl=mp                |
            |BZ   a|32|-|Branch if D Zero            |If D=0 BR else NBR   |
            |DEC  r|2N|-|Decrement register N        |n=n-1                |
            |DIS   |71|-|Disable                     |{X,P}=mx,x=x+1,IE=0  |
            |GHI  r|9N|-|Get High register N         |D=nh                 |
            |GLO  r|8N|-|Get Low register N          |D=nl                 |
            |IDL   |00|-|Idle (wait for DMA or int.) |Bus=m0               |
            |INC  r|1N|-|Increment register N        |n=n+1                |
            |INP  d|6N|-|Input (N=d+8=9-F)           |mx=Bus,D=Bus,Nlines=d|
            |IRX   |60|-|Increment register X        |x=x+1                |
            |LBDF a|C3|-|Long Branch if DF           |If DF=1 LBR else LNBR|
            |LBNF a|C8|-|Long Branch if Not DF       |If DF=0 LBR else LNBR|
            |LBNQ a|C9|-|Long Branch if Not Q        |If Q=0 LBR else LNBR |
            |LBNZ a|CA|-|Long Branch if D Not Zero   |If D=1 LBR else LNBR |
            |LBQ  a|C1|-|Long Branch if Q            |If Q=1 LBR else LNBR |
            |LBR  a|C0|-|Long Branch                 |p=mp                 |
            |LBZ  a|C2|-|Long Branch if D Zero       |If D=0 LBR else LNBR |
            |LDA  r|4N|-|Load advance                |D=mn,n=n+1           |
            |LDI  i|F8|-|Load Immediate              |D=mp,p=p+1           |
            |LDN  r|0N|-|Load via N (except N=0)     |D=mn                 |
            |LDX   |F0|-|Load via X                  |D=mx                 |
            |LDXA  |72|-|Load via X and Advance      |D=mx,x=x+1           |
            |LSDF  |CF|-|Long Skip if DF             |If DF=1 LSKP else NOP|
            ----------------------------------------------------------------

            AS1802 ASSEMBLER                                        PAGE V-7
            1802 INSTRUCTION SET

            ----------------------------------------------------------------
            |Mnem. |Op|F|Description                 |Notes                |
            |------+--+-+----------------------------+---------------------|
            |LSIE  |CC|-|Long Skip if IE             |If IE=1 LSKP else NOP|
            |LSKP  |C8|-|Long Skip                   |See NLBR             |
            |LSNF  |C7|-|Long Skip if Not DF         |If DF=0 LSKP else NOP|
            |LSNQ  |C5|-|Long Skip if Not Q          |If Q=0 LSKP else NOP |
            |LSNZ  |C6|-|Long Skip if D Not Zero     |If D=1 LSKP else NOP |
            |LSQ   |CD|-|Long Skip if Q              |If Q=1 LSKP else NOP |
            |LSZ   |CE|-|Long Skip if D Zero         |If D=0 LSKP else NOP |
            |MARK  |79|-|Push X,P to stack  (T={X,P})|m2={X,P},X=P,r2=r2-1 |
            |NBR   |38|-|No short Branch (see SKP)   |p=p+1                |
            |NLBR a|C8|-|No Long Branch (see LSKP)   |p=p+2                |
            |NOP   |C4|-|No Operation                |Continue             |
            |OR    |F1|*|Logical OR                  |D={mx}vD             |
            |ORI  i|F9|*|Logical OR Immediate        |D={mp}vD,p=p+1       |
            |OUT  d|6N|-|Output (N=d=1-7)            |Bus=mx,x=x+1,Nlines=d|
            |PLO  r|AN|-|Put Low register N          |nl=D                 |
            |PHI  r|BN|-|Put High register N         |nh=D                 |
            |REQ   |7A|-|Reset Q                     |Q=0                  |
            |RET   |70|-|Return                      |{X,P}=mx,x=x+1,IE=1  |
            |RSHL  |7E|*|Ring Shift Left             |See SHLC             |
            |RSHR  |76|*|Ring Shift Right            |See SHRC             |
            |SAV   |78|-|Save                        |mx=T                 |
            |SDB   |75|*|Subtract D with Borrow      |{DF,D}=mx-D-DF       |
            |SDBI i|7D|*|Subtract D with Borrow Imm. |{DF,D}=mp-D-DF,p=p+1 |
            |SD    |F5|*|Subtract D                  |{DF,D}=mx-D          |
            |SDI  i|FD|*|Subtract D Immediate        |{DF,D}=mp-D,p=p+1    |
            |SEP  r|DN|-|Set P                       |P=N                  |
            |SEQ   |7B|-|Set Q                       |Q=1                  |
            |SEX  r|EN|-|Set X                       |X=N                  |
            |SHL   |FE|*|Shift Left                  |{DF,D}={DF,D,0}<-    |
            |SHLC  |7E|*|Shift Left with Carry       |{DF,D}={DF,D}<-      |
            |SHR   |F6|*|Shift Right                 |{D,DF}=->{0,D,DF}    |
            |SHRC  |76|*|Shift Right with Carry      |{D,DF}=->{D,DF}      |
            |SKP   |38|-|Short Skip                  |See NBR              |
            |SMB   |77|*|Subtract Memory with Borrow |{DF,D}=D-mx-{~DF}    |
            |SMBI i|7F|*|Subtract Mem with Borrow Imm|{DF,D}=D-mp-~DF,p=p+1|
            |SM    |F7|*|Subtract Memory             |{DF,D}=D-mx          |
            |SMI  i|FF|*|Subtract Memory Immediate   |{DF,D}=D-mp,p=p+1    |
            |STR  r|5N|-|Store via N                 |mn=D                 |
            |STXD  |73|-|Store via X and Decrement   |mx=D,x=x-1           |
            |XOR   |F3|*|Logical Exclusive OR        |D={mx}.D             |
            |XRI  i|FB|*|Logical Exclusive OR Imm.   |D={mp}.D,p=p+1       |
            |      |  |-|Interrupt action            |T={X,P},P=1,X=2,IE=0 |
            |------+--+-+--------------------------------------------------|
            |      |??| |8-bit hexadecimal opcode                          |
            |      |?N| |Opcode with register/device in low 4/3 bits       |
            |      |  |-|DF flag unaffected                                |
            |      |  |*|DF flag affected                                  |
            ----------------------------------------------------------------

            AS1802 ASSEMBLER                                        PAGE V-8
            1802 INSTRUCTION SET

            ----------------------------------------------------------------
            |Arguments  |                     Notes                        |
            |-----------+--------------------------------------------------|
            | mn        |Register addressing                               |
            | mx        |Register-indirect addressing                      |
            | mp        |Immediate addressing                              |
            | R( )      |Stack addressing (implied addressing)             |
            |-----------+--------------------------------------------------|
            | D         |Data register (accumulator, 8-bit)                |
            | DF        |Data Flag (ALU carry, 1-bit)                      |
            | I         |High-order instruction digit (4-bit)              |
            | IE        |Interrupt Enable (1-bit)                          |
            | N         |Low-order instruction digit (4-bit)               |
            | P         |Designates Program Counter register (4-bit)       |
            | Q         |Output flip-flop (1-bit)                          |
            | R         |1 of 16 scratchpad Registers(16-bit)              |
            | T         |Holds old {X,P} after interrupt (X high, 8-bit)   |
            | X         |Designates Data Pointer register (4-bit)          |
            |-----------+--------------------------------------------------|
            | mn        |Memory byte addressed by R(N)                     |
            | mp        |Memory byte addressed by R(P)                     |
            | mx        |Memory byte addressed by R(X)                     |
            | m?        |Memory byte addressed by R(?)                     |
            | n         |Short form for R(N)                               |
            | nh        |High-order byte of R(N)                           |
            | nl        |Low-order byte of R(N)                            |
            | p         |Short form for R(P)                               |
            | pl        |Low-order byte of R(P)                            |
            | r?        |Short form for R(?)                               |
            | x         |Short form for R(X)                               |
            |-----------+--------------------------------------------------|
            | R(N)      |Register specified by N                           |
            | R(P)      |Current program counter                           |
            | R(X)      |Current data pointer                              |
            | R(?)      |Specific register                                 |
            ----------------------------------------------------------------

            AS1802 ASSEMBLER                                        PAGE V-9
            1802 INSTRUCTION SET

            ----------------------------------------------------------------
            |Arguments  |                     Notes                        |
            |-----------+--------------------------------------------------|
            | a         |Address expression                                |
            | d         |Device number (1-7)                               |
            | i         |Immediate expression                              |
            | n         |Expression                                        |
            | r         |Register (hex digit or an R followed by hex digit)|
            |-----------+--------------------------------------------------|
            | +         |Arithmetic addition                               |
            | -         |Arithmetic subtraction                            |
            | *         |Arithmetic multiplication                         |
            | /         |Arithmetic division                               |
            | &         |Logical AND                                       |
            | ~         |Logical NOT                                       |
            | v         |Logical inclusive OR                              |
            | .         |Logical exclusive OR                              |
            | <-        |Rotate left                                       |
            | ->        |Rotate right                                      |
            | { }       |Combination of operands                           |
            | ?         |Hexadecimal digit (0-F)                           |
            | -->       |Input pin                                         |
            | <--       |Output pin                                        |
            | <-->      |Input/output pin                                  |
            ----------------------------------------------------------------

                                       APPENDIX W

                                    AS61860 ASSEMBLER

            W.1  ACKNOWLEDGMENT

                 Thanks  to  Edgar  Puehringer  for  his contribution of the
            AS61860 cross assembler.

                    Edgar Peuhringer
                    edgar_pue at yahoo dot com

            W.2  61860 REGISTER SET

            The  SC61860  from  Sharp has 96 bytes of internal RAM which are
            used as registers and hardware stack.  The last  four  bytes  of
            the  internal  RAM  are  special  purpose registers (I/O, timers
            ...).  Here is a list of the 61860 registers:

                    Reg     Address         Common use
                    ---     -------         ----------
                    i, j    0, 1            Length of block operations
                    a, b    2, 3            Accumulator
                    xl, xh  4, 5            Pointer for read operations
                    yl, yh  6, 7            Pointer for write operations
                    k - n   8 - 0x0b        General purpose (counters ...)
                      -     0x0c - 0x5b     Stack
                    ia      0x5c            Inport A
                    ib      0x5d            Inport B
                    fo      0x5e            Outport F
                    cout    0x5f            Control port

            AS61860 ASSEMBLER                                       PAGE W-2
            61860 REGISTER SET

                 Other  parts  of  the  61860 are the 16 bit program counter
            (pc) and 16 bit data pointer (dp).  The ALU has a carry flag (c)
            and  a  zero  flag  (z).   There is an internal register d which
            can't be accessed with machine instructions.  It is filled  from
            i or j when executing block operations.

                 In  addition  there  are  three 7 bit registers p, q, and r
            which are used to address the  internal  RAM  (r  is  the  stack
            pointer, p and q are used for block operations).

            W.3  PROCESSOR SPECIFIC DIRECTIVES

                 The  AS61860 cross assembler has two (2) processor specific
            assembler directives which are used for the etc mnemonic  (which
            is a kind of a built-in switch/case statement):

                    .default        A 16 bit address (same as .dw)
                    .case           One byte followed by a 16 bit address

            Here is an example how this should be used (cut from a lst
            file)::

               022B 7A 05 02 18         614         PTC     0x05,   CONT16
               022F 69                  615         DTC
               0230 4C 01 25            616         .CASE   0x4C,   SLOADI
               0233 4D 01 2F            617         .CASE   0x4D,   SMERGI
               0236 51 01 D2            618         .CASE   0x51,   QUITI
               0239 53 00 CD            619         .CASE   0x53,   LLISTI
               023C 56 01 D5            620         .CASE   0x56,   VERI
               023F 01 D1               621         .DEFAULT        CONT9

            W.4  61860 INSTRUCTION SET

                 The following tables list all 61860 family mnemonics recog-
            nized by the AS61860 assembler.  Most of the mnemonics are  con-
            verted  into  8  bit  machine instructions with no argument or a
            one- or two-byte argument.  There are some exceptions for this:

                    Mnemonic        Description
                    --------        -----------
                    jp              2 bit instruction, 6 bit argument
                    cal             3 bit instruction, 13 bit argument
                    ptc *)          1 byte instruction, 3 byte argument
                    dtc *)          1 byte instruction, n bytes argument

                    *) Not mentioned in the CPU specification from Sharp

            AS61860 ASSEMBLER                                       PAGE W-3
            61860 INSTRUCTION SET

            W.4.1  Load Immediate Register

                    LII n           (n --> I)
                    LIJ n
                    LIA n
                    LIB n
                    LIP n
                    LIQ n
                    LIDP nm
                    LIDL n          (DL is the low byte of DP)
                    LP              (One byte version of LIP)
                    RA              (Same as LIA 0, but only one byte)
                    CLRA            (synonym for RA)

            W.4.2  Load Accumulator

                    LDP             (P --> A)
                    LDQ
                    LDR
                    LDM             ((P) --> A)
                    LDD             ((DP) --> A)

            W.4.3  Store Accumulator

                    STP             (A --> P)
                    STQ
                    STR
                    STD             (A --> (DP))

            W.4.4  Move Data

                    MVDM            ((P) --> (DP))
                    MVMD            ((DP) --> (P))

            AS61860 ASSEMBLER                                       PAGE W-4
            61860 INSTRUCTION SET

            W.4.5  Exchange Data

                    EXAB            (A <--> B)
                    EXAM            (A <--> (P))

            W.4.6  Stack Operations

                    PUSH            (R - 1 --> R, A --> (R))
                    POP             ((R) --> A, R + 1 --> R)
                    LEAVE           (0 --> (R))

            W.4.7  Block Move Data

                    MVW             ((Q) --> (P), I+1 bytes)
                    MVB             ((Q) --> (P), J+1 bytes)
                    MVWD            ((DP) --> (P), I+1 bytes)
                    MVBD            ((DP) --> (P), J+1 bytes)
                    DATA            ((B,A) --> (P), I+1 bytes,
                                    reads CPU ROM also)

            W.4.8  Block Exchange Data

                    EXW             ((Q) <--> (P), I+1 bytes)
                    EXB             ((Q) <--> (P), J+1 bytes)
                    EXWD            ((DP) <--> (P), I+1 bytes)
                    EXBD            ((DP) <--> (P), J+1 bytes)

            AS61860 ASSEMBLER                                       PAGE W-5
            61860 INSTRUCTION SET

            W.4.9  Increment and Decrement

                    INCP            (P + 1 --> P)
                    DECP
                    INCI
                    DECI
                    INCJ
                    DECJ
                    INCA
                    DECA
                    INCB
                    DECB
                    INCK
                    DECK
                    INCL
                    DECL
                    IX              (X + 1 --> X, X --> DP)
                    DX
                    IY
                    DY
                    INCM *)
                    DECM *)
                    INCN *)
                    DECN *)

                    *) Not mentioned in the CPU specification from Sharp

            W.4.10  Increment/Decrement with Load/Store

                    IXL             (Same as IX plus LDD)
                    DXL
                    IYS             (Same as IY plus STD)
                    DYS

            W.4.11  Fill

                    FILM            (A --> (P), I+1 bytes)
                    FILD            (A --> (DP), I+1 bytes)

            AS61860 ASSEMBLER                                       PAGE W-6
            61860 INSTRUCTION SET

            W.4.12  Addition and Subtraction

                    ADIA n          (A + n --> A)
                    SBIA n
                    ADIM n          ((P) + n --> (P))
                    SBIM n
                    ADM n           ((P) + A --> (P))
                    SBM n
                    ADCM n          ((P) + A --> (P), with carry)
                    SBCM
                    ADB             (like ADM, but 16 bit)
                    SBB
                    ADN             (like ADM, BCD addition, I+1 bytes)
                    SBN
                    ADW             ((P) + (Q) --> (P), BCD, I+1 bytes)
                    SBW

            W.4.13  Shift Operations

                    SRW             (shift I+1 bytes in (P) 4 bits right)
                    SLW
                    SR              (shift A 1 bit, with carry)
                    SL
                    SWP             (exchange low and high nibble of A)

            W.4.14  Boolean Operations

                    ANIA n          (A & n --> A)
                    ORIA n
                    ANIM n          ((P) & n --> (P))
                    ORIM n
                    ANID n          ((DP) & n --> (DP))
                    ORID n
                    ANMA            ((P) & A --> (P))
                    ORMA

            AS61860 ASSEMBLER                                       PAGE W-7
            61860 INSTRUCTION SET

            W.4.15  Compare

                    CPIA n          (A - n --> c,z)
                    CPIM n          ((P) - n --> c,z)
                    CPMA            ((P) - A --> c,z)
                    TSIA n          (A & n --> z)
                    TSIM n          ((P) & n --> z)
                    TSID n          ((DP) & n --> z)
                    TSIP            ((P) & A --> z)

            W.4.16  CPU Control

                    SC              (Set carry)
                    RC
                    NOPW            (no op)
                    NOPT
                    WAIT n          (wait 6+n cycles)
                    WAITJ           (wait 5+4*I cycles)
                    CUP             (synonym for WAITJ)

            W.4.17  Absolute Jumps

                    JP nm
                    JPZ nm          (on zero)
                    JPNZ nm
                    JPC nm
                    JPNC nm
                    PTC/DTC         (see 'Processor Specific Directives')
                    PTJ/DTJ         (synonym for PTD/DTC)
                    CPCAL/DTLRA     (synonym for PTC/DTC)
                    CASE1/CASE2     (synonym for PTC/DTC)
                    SETT/JST        (synonym for PTC/DTC)

            AS61860 ASSEMBLER                                       PAGE W-8
            61860 INSTRUCTION SET

            W.4.18  Relative Jumps

                 These  operations  handle a jump relative to PC forward and
            back with  a  maximum  distance  of  255  byte.   The  assembler
            resolves 16 bit addresses to to 8 bit relative adresses.  If the
            target address is to far away, an error will be generated.  Note
            that relative jumps need 1 byte less than absolute jumps.

                    JRP nm
                    JRZP nm
                    JRNZP nm        (jump relative non zero plus direction)
                    JRCP nm
                    JRNCP nm
                    JRM nm
                    JRZM nm
                    JRNZM nm
                    JRCM nm         (jump relative on carry minus direction)
                    JRNCM nm
                    LOOP nm         (decrements (R) and makes a JRNCM)

            W.4.19  Calls

                    CALL nm
                    CAL nm          (nm must be <= 0x1fff,
                                    1 byte less code than CALL)
                    RTN

            W.4.20  Input and output

                    INA             (IA --> A)
                    INB
                    OUTA
                    OUTB
                    OUTF            (A --> FO)
                    OUTC            (control port)
                    TEST n          (timers, pins & n --> z)

            AS61860 ASSEMBLER                                       PAGE W-9
            61860 INSTRUCTION SET

            W.4.21  Unknown Commands

                    READ            ((PC+1) -> A)
                    READM           ((PC+1) -> (P))
                    WRIT            (???)

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