ABSTRACT

	LSIRT IS A MULTITASKING OPERATING SYSTEM FOR THE LSI/11, WITHOUT
MEMORY MANAGEMENT.  IT IS THE EXECUTIVE THAT DETERMINES WHEN TASKS ARE
EXECUTED; VIA REAL TIME SCHEDULING, PROGRAMMED SEQUENCIAL ORDER, OPERATOR
COMMANDS, AND/OR EVENTS(INTERRUPT DRIVEN).
	IT IS MEANT TO BE USED IN CONTROL APPLICATIONS, WHERE DEVELOPMENT
SYSTEM ABILITIES AND THE ASSOCIATED HARDWARE ARE NOT NEEDED.  THIS
PACKAGE IS ROMABLE.
	THE COMPLETE SOFTWARE PACKAGE CONSISTS OF THE ROM SECTION OF LSIRT
(LSIRT.MAC),THE RAM SECTION OF LSIRT(LSIRAM.MAC),THE FLOATING POINT PACKAGE
(FPPAK.MAC),AND A MACRO LIBRARY(MACLIB.MLB).
	FPPAK AND MACLIB ALLOW FOR I/O OPERATIONS AND FLOATING POINT FUNCTIONS
TO BE IMPLEMENTED EASILY VIA MACROS.  MACLIB ALSO CONTAINS MANY OTHER USEFUL 
MACROS, SUCH AS 16 JUMP ON CONDITION MACROS. THE FLOATING POINT PACKAGE IS ALSO
A SEPARATE ENTRY TO THE LIBRARY, ALLOWING MORE GREATER FLEXIBILITY IN ITS USE.


				DOCUMENTATION

				SUMMARY

	THIS DOCUMENTATION IS INTENDED TO ILLUSTRATE HOW TO USE THE LSIRT
SOFTWARE PACKAGE, AND HOW IT FUNCTIONS.  IN ADDITION TO SOURCE LISTINGS
OF LSIRT.MAC, LSIRAM.MAC, AND FPPAK.MAC, .LST VERSIONS OF LSIRT AND LSIRAM
WILL BE INCLUDED FOR REFERENCE.  LABELS REFERENCED IN THIS DOCUMENTATION
WILL HAVE THE : SUFFIX.  X IS THE VARIABLE FOR CHANNEL #. MACROS THAT GENERATE
1 INSTRUCTION, LIKE 'CALL', WILL BE CALLED INSTRUCTIONS.


				CONTENTS

1)	THE BEGINNING
	1.1)	ASSEMBLER DIRECTIVES
	1.2)	SERIAL CHANNEL ASSIGNMENTS
	1.3)	TAPE BLOCK SIZE
	1.4)	INTERRUPT VECTORS
	1.5)	START UP
2)	BASE LEVEL
	2.1)	SCHEDULING APPARATUS
	2.2)	CODE IMPLEMENTATION
	2.3)	BASE TASK FORM
	2.4)	MACHINE USAGE FEATURE
3)	CLOCK LEVEL
	3.1)	CLOCK LEVEL MONITOR
	3.2)	CLOCK TASK RULES
	3.3)	TIME OF DAY CLOCK
	3.4)	MARK TIME
4)	SERIAL I/O
	4.1)	OUTPUT
		4.11)	QUEIO$C MACRO
		4.12)	DYNAMICS OF QUEIO$C
		4.13)	OUTPUT DRIVER DELAY FEATURE
		4.14)	MAG TAPE DRIVER
	4.2)	INPUT
		4.21)	INPUT DRIVER
		4.22)	ECHO ROUTINES
		4.23)	DRIVER PROPERTIES
		4.24)	INPUT MONITOR
5)	TRAPS
	5.1)	TRAP INSTRUCTION HANDLER
	5.2)	FORCED TRAPS
	5.3)	BREAK POINTS
6)	AUDITS AND DIAGNOSTICS
	6.1)	BASE TASK AUDIT
	6.2)	LOAD SHARING
7)	MACRO LIBRARY
	7.1)	SYSTEM MACROS
	7.2)	MNEMONIC SUBSTITUTIONS
	7.3)	JUMP ON CONDITION
	7.4)	FLOATING POINT MACROS
	7.5)	NUMERIC FORMATTING
	7.6)	PFOR

1	THE BEGINNING - GETTING STARTED

	LOOKING AT THE BEGINNING OF LSIRT.LST(INCLUDES LSIRAM), THE CONTENTS
OF THE SOURCE FILE WILL BE EXPLAINED.

1.1	ASSEMBLER DIRECTIVES

	THE FIRST PART OF LSIRT CONTAINS  THE ASSEMBLER DIRECTIVES.  DIRECTIVES
ARE PRESENT TO ENABLE SYMBOL TABLE, CROSS REFERENCE LISTING, ABSOLUTE ADDRESS-
ING MODE DEFAULT, INHIBIT MACRO EXPANSIONS, AND AN .MCALL TO ALL THE MACROS
THAT EXIST IN MACLIB.  ABSOLUTE ADDRESSING MODE IS VERY USEFUL IN THE DEBUGGING
PHASE, AND CAN BE ELIMINATED IN THE FINAL VERSION OF YOUR SOFTWARE PACKAGE
FOR ADDITIONAL SPEED.
	THE .PSECT DIRECTIVE AND THE METHOD OF ASSIGNING THE PC VIA ADDITIONS
(EG .=.+4) ARE NECESSARY TO PRODUCE A BOOTABLE FILE, VIA THE TASK BUILDING
COMMAND FILE -

FILE/-HD=FILE
/
STACK=0
UNITS=0
CORSIZ=14
//

	THE CORSIZ TASK BUILDING DIRECTIVE IS THE AMOUNT OF K WORDS IN THE
TOTAL RESULTING BOOTABLE FILE.  CORSIZ ALSO INCLUDES THE RAM AREA IF RAM IS
NOT INITIALIZED BY THE CODE.

1.2	SERIAL CHANNEL ASSIGNMENTS

	THE SERIAL CHANNELS EXPECTED TO BE USED ARE OF THE DLV11 CONFIGURATION.
THE DLV11 CONFIGURATION CAN BE REFERENCED IN THE 'MEMORYS AND PERIPHERALS' HAND-
BOOK, OF THE MICROCOMPUTER HANDBOOK SERIES.
	IMMEDIATELY AFTER THE ASSEMBLER DIRECTIVES, AT THE BEGINNING OF
LSIRT, ARE THE SERIAL CHANNEL ASSIGNMENTS.  EACH REGISTER IS REPRE-
SENTED BY A 5 CHARACTER NAME.  THE FIRST 4 CHARACTERS ARE THE SAME DES-
IGNATION AS USED BY THE HANDBOOK, AND THE LAST CHARACTER IS THE CHANNEL
NUMBER.  THE FIRST 2 REGISTERS, WITH THE CHANNEL NUMBER 'T', ARE THE
TRAP OR ALARM MESSAGE CHANNEL.  THE TRAP CHANNEL IS THE CHANNEL THAT
THE ALARM MESSAGES(SEE SECTION 5) ARE OUTPUT ON.  IT MAY BE SEPARATE, OR
THE SAME AS ANY ONE OF THE OTHER CHANNELS.
	THE ASSIGNMENTS ARE SIMPLY THE ADDRESSES OF THE SERIAL REGISTERS AS
THEY APPEAR IN YOUR CONFIGURATION.

1.3	TAPE BLOCK ASSIGNMENTS

	THE LITERAL 'RECLEN' IS THE RECORD LENGTH OR BLOCK SIZE OF THE
MAG TAPE BLOCKS, FOR THE OUTPUT TAPE DRIVER.(SEE 4.14)

1.4	INTERRUPT VECTORS

	THE NEXT PART OF LSIRT IS THE INTERRUPT VECTOR ASSIGNMENTS. THIS IS
STRAIGHT FORWARD, EXCEPT THAT,  AS STATED EARLIER, PC ASSIGNMENTS MUST BE DONE
VIA AN ADDITION TO THE PRESENT PC VALUE.

1.5	START UP

	EXECUTION BEGINS AT STA:.  STA: RESETS THE MACHINE, ASSIGNS THE
STACK POINTER, INITIALIZES RAM, AND JUMPS TO BEGIN:, WHICH IS THE INITIALIZA-
TION ROUTINE OF THE APPLICATION CODE(SEE BEGIN.MAC FOR AN EXAMPLE).  BEGIN:
ENDS ITS EXECUTION BY JUMPING TO BASEL:(SEE 2.3).
	THE STACK ASSIGNMENT IN STA: IS USER DEPENDENT, AS IS THE LOCATION
OF STA: AND THE REST OF THE CODE.

2	BASE LEVEL

2.1	SCHEDULING APPARATUS


	THE BASIC SCHEDULING APPARATUS OF LSIRT IS THE BASE LEVEL STATUS ARRAY,
WHICH IS A BIT ARRAY THAT DETERMINES THE PRIORITY AND EXECUTION STATUS OF 
THE BASE LEVEL(NON-INTERRUPT LEVEL) TASKS.  AT PRESENT THE BASE LEVEL STATUS
IS 48 BITS(TASKS), BUT IS EASILY EXPANDABLE.
	EACH BIT IN THE BASE LEVEL STATUS ARRAY(BSTAT:) CORRESPONDS TO A TASK
VECTOR IN THE BASE LEVEL TASK VECTOR TABLE(BTSK:).  BY PLACING THE ADDRESS OF
OF A TASK IN ONE OF THE TASK VECTOR SLOTS IN BTSK:, IT WILL BE SCHEDULED 
FOR EXECUTION BY SETTING THE CORRESPONDING BIT IN BSTAT:.  THE TASK VECTOR
SLOTS ARE NUMBERED 1 THRU 48, AS ARE THE BITS IN BSTAT:.  A TASK VECTOR IS
LOADED INTO BTSK: VIA THE INSTAL$ MACRO, AND IS ACTIVATED VIA THE ACTBT$
MACRO.  FOR EXAMPLE:
	INSTAL$	ECOV3,10.	;INSTALLS ECOV3 AS TASK 10.
;
	ACTBT$	10.		;ACTIVATES TASK FOR EXECUTION
;
	THE DEFAULT VECTOR IN BTSK: IS THE VECTOR OFT:, WHICH SIMPLY POINTS
TO A RETURN INSTRUCTION. THEREFORE, ACTIVATING A NON INSTALLED TASK WILL
DO NOTHING.
	THE INSTAL$ MACRO IS RELEVANT FOR A BASE LEVEL TASK VECTOR TABLE
IN THE RAM PART OF MEMORY, WHICH ADDS A DIMENSION OF SOFTWARE FLEXIBILITY
(SEE 4.24 FOR AN EXAMPLE). HOWEVER, THERE IS NO REASON TO AVOID PUTTING BTSK:
IN ROM AND ELIMINATING THE NEED FOR THE INSTAL$ MACRO.
	THE PRIORITY OF A TASK IS DETERMINED BY ITS TASK #, WITH 1 BEING
THE HIGHEST PRIORITY AND 48 THE LOWEST.  AFTER A TASK IS EXECUTED, BASES:
AGAIN SCANS BSTAT: STARTING WITH THE FIRST BIT(BIT # 1).  SO A TASK ISN'T
EXECUTED UNTIL NONE OF THE TASKS OF HIGHER PRIORITY ARE ACTIVE.
	LSIRT, BEING A REAL TIME OPERATING SYSTEM, EXECUTES A BASE LEVEL TASK
COMPLETELY BEFORE RESCANNING BASE LEVEL STATUS. BASE LEVEL TASKS ARE INTER-
RUPTED ONLY BY HARDWARE IINTERRUPTS, OR BY CLOCK LEVEL TASKS.

2.2	CODE IMPLEMENTATION

	THE CODE THAT IMPLEMENTS THE EXECUTION OF THE BASE LEVEL TASKS IS
FOUND IN BASE LEVEL LOOP(BASEL:) AND BASE LEVEL SEARCH AND EXECUTE(BASES:).
BASEL: IS A COUNTING LOOP THAT LOOKS AT BSTAT: BY TESTING ENTIRE WORDS TO
SEE IF ANY BITS ARE SET(ANY TASKS AWAITING EXECUTION). IF A SET BIT IS
FOUND IN ONE OF THE BSTAT: WORDS, THE SUBROUTINE BASES: IS CALLED.  BASES:
SCANS ALL BITS STARTING WITH BIT #1 AND CONTINUES THRU ALL THE BITS IN
BSTAT:.  EVERYTIME A SET BIT IS FOUND, IT IS RESET AND THE CORRESPONDING TASK
IS EXECUTED, VIA A CALL(JSR PC).
	THE PURPOSE OF BASEL: IS TO KEEP A REFERENCE OF HOW OFTEN THE MACHINE
IS IDLE(OR BUSY).  SECTION 2.4 EXPLAINS HOW BASEL: IS UTILIZED.

2.3	BASE TASK FORM

	A BASE LEVEL TASK HAS 1 RESTRICTION IN THE WAY IN WHICH IT IS
IMPLEMENTED, THE STACK MUST BE IN ITS ENTRY CONDITION UPON EXITING. HOWEVER,
REGISTERS NEED NOT BE SAVED, AND ANY MACROS CAN BE USED,OR SUBROUTINES 
CALLED.  EXECUTION IS TERMINATED VIA A RET(RTS PC) INSTRUCTION.
	LSIRT USES ONE STACK, WHICH REQUIRES THE NEED FOR STACK INTEGRITY
THROUGHOUT ALL TASKS.  MORE SOPHISTICATED OPERATING SYSTEMS, LIKE RSX,
RESERVE A REGISTER IMAGE BUFFER AND A STACK AREA FOR EACH TASK. BUT
WHAT ONE GAINS IN SOPHISTICATION, ONE LOSES IN SPEED AND SIMPLIICITY.
	THE TERM 'TASK' AS USED IN LSIRT REFERS TO A SINGLE STEP IN A
OPERATION COMPOSED OF MANY SEQUENTIAL STEPS.  THE STEPS OF AN OPERATION
ARE LINKED TOGETHER WITH THE ACTBT$ MACRO.  THE COMMON DATA IS SIMPLY
A COMMON AREA OF MEMORY, OR GLOBAL VARIABLE.
	ONCE A BASE TASK BEGINS EXECUTION, IT OWNS THE CPU IN BASE LEVEL
UNTIL IT IS COMPLETED AND RETURNS TO THE EXECUTIVE(BASES:). THEREFORE,
BASE TASKS SHOULD BE CODED TO EXECUTE RAPIDLY, SAY WITHIN 50 MILLI SEC.
ITERATIVE TASKS SHOULD BE EXECUTED ONE ITERATION AT A TIME, THE LOOP
SHOULD BE COMPLETED VIA THE ACTBT$ MACRO. UPON COMPLETION OF ALL THE
ITERATIONS, DO NOT EXECUTE THE ACTBT$, IN OTHER WORDS, USE ACTBT$ TO CLOSE
LARGE LOOPS INSTEAD OF JUMPS.
	THE 50 MSEC LIMIT IS JUST AN ARBITRARY SUGGESTION, BASED ON THE
FACT THAT ECHOING CHARACTERS REQUIRES EXECUTION OF A BASE TASK(SEE 4.22).
WHATEVER MAXIMUN TASK EXECUTION TIME DEEMED OK BY THE DESIGNER, IS OK.
THE BASE TASK AUDIT(SEE 6.1) CAN BE USED TO DETERMINE THE LENGTH OF YOUR
MAXIMUM TASK IN TICKS. TASKS WITH TOO LARGE A RUN TIME CAN BE SPLIT INTO
2 OR MORE TASKS.

2.4	MACHINE USAGE FEATURE

	TO IMPLEMENT THIS FEATURE, EXECUTE LSIRT FOR EXACTLY 1 HOUR, WITH-
OUT ANY INTERRUPTS ENABLED OR ANY TASKS RUNNING AT ALL.  AT THE END OF THE
HOUR, RECORD THE NUMBER AT LOCATION USAGE:+2, AND INSERT IT IN BASE 10
FORM AT LOCATION FREE:, BEHIND THE .FLT2 DIRECTIVE.
	ONCE THE PROPER VALUE OF FREE: HAS BEEN DETERMINED FOR A PARTICULAR
MACHINE, THE PERCENTAGE OF TIME THE MACHINE WAS BUSY CAN BE DETERMINED
EVERY HOUR WITH THE CODE CONTAINED AT 25$: IN THE FOLLOWING TIMCH: TASK
EXAMPLE.  THIS CODE COULD BE EXECUTED IN TIMCH:, OR AS A CLOCK LEVEL
ROUTINE.
;
;	SAMPLE BASE LEVEL TASK
;
;	TIMCH - TIME CHECK
;	CUSTOM APPLICATION CODE TO ACTIVATE TASKS, OR SEQUENCE
;	OF TASKS(AN OPERATION), ON A TIME OF DAY BASIS.
;	TIMCH IS ACTIVATED ONCE EVERY SECOND BY THE CLOCK LEVEL MONITOR
;
TIMCH:	TST	BSEC		;SEC=0?
	JNE	10$		;NO, BYE
	MOV	BMIN,R1		;6 MIN BOUNDRY?
	SXT	R0
	DIV	#6,R0
	TST	R1
	JNE	10$		;NO
;
;	6 MINUTE BOUNDRY
;
	ACTBT$	20.		;MODEM AUDIT
	INSTAL$	OFT,2		;SHUT SELF OFF
	BIT	#1,R0		;EVEN OR ODD?
	BEQ	1$		;EVEN
	MOV	#G16,P61
	MOV	#FP6BOD,P62
	MOV	#FP6+5,R3
	BR	3$
1$:	MOV	#G16E,P61
	MOV	#FP6BE,P62
	MOV	#FP6E+5,R3
3$:	MOV	#DELAY,ALLK	;TURN ON CLOCK LEVEL ROUTINE, 16.6 MS SLOT
	CLR	J24V1		;INITIALIZE CYCLE VARIABLES
	CLR	J24V2
	CLR	J23V1
	CLR	J23V2
	CLR	NSTAT
	MOV	#DAY,R0		;POINTER
	MOV	#12.,R1		;COUNTER
	MOV	#BCDASC+5,R2	;BCD
20$:	MOVB	(R0),(R2)+
	MOVB	(R0)+,(R3)+
	SOB	R1,20$
;
	TST	BMIN		;HOUR BOUNDRY?
	BNE	10$		;NO
;
;	HOUR BOUNDRY
;
25$:	FLT$	USAGE+2,FPBUF	;CALCULATES MACHINE USAGE
	CLR	USAGE
	CLR	USAGE+2
	SUBF$	FREE,FPBUF
	NEGF$	FPBUF,FPBUF
	DIVF$	FREE,FPBUF
	MULF$	FPHUN,FPBUF
	FTOA$	FPBUF,FPCHB
	MOV	#AVLB+17.,R3	;POINTER FOR TRANSF$
	TRANSF$	4,1
;
	MOV	#17,HOURF
	CLR	J22V1
	CLR	J22V2
	MOV	#DAY,R0
	MOV	#12.,R1
	MOV	#FPHRHD+5,R4
4$:	MOVB	(R0)+,(R4)+
	SOB	R1,4$
10$:	RET
;
	TO HAVE THE RESULT OUTPUT, INSERT THE FOLLOWING MACRO EITHER
DIRECTLY IN TIMCH: OR VIA OPERATOR COMMAND IN A COMMAND INTERPRETER.
;
	QUEIO$C	3,#AVLB,#AVLBE	;FOR CHANNEL # 3
;

3	CLOCK LEVEL

3.1	CLOCK LEVEL MONITOR

	LSIRT CONTAINS A VERY SIMPLE BUT USEFUL CLOCK LEVEL MONITOR(CLK:),
WHICH IS THE LINE TIME CLOCK INTERRUPT SERVICE ROUTINE.
	CLK: IS DIVIDED INTO SEVERAL SLOTS OF DIFFERENT PEROIDS OF
OCCURANCE.  THE PRESENT SLOTS OF CLK OCCUR AT 16.6 MS,100 MS, 1 SEC,
3 SEC, AND 15 SEC.  THE TASKS CORRESPONDING TO A GIVEN TIME SLOT ARE
EXECUTED VIA AN INDIRECT CALL(JSR PC) THRU THE CLOCK LEVEL VECTOR TABLE.
	AS WITH BTSK:, THE CLOCK LEVEL VECTOR TABLE IS IN THE RAM PART
OF LSIRT(LSIRAM), BUT WOULD WORK FINE IN ROM AS LONG AS IT WAS NOT MEANT
TO BE DYMANIC.  IF DYNAMIC, TASKS ARE ENTERED INTO THE CLOCK LEVEL VECTOR
TABLE VIA THE MOV INSTRUCTION(SEE 3$: OF SAMPLE IN SECTION 2.4).

3.2	CLOCK TASK RULES

	SINCE CLK: ITSELF IS THE INTERRUPT ROUTINE, THE SPECIFIC CLOCK
LEVEL TASKS END EXECUTION VIA THE RET(RTS PC) INSTRUCTION.  CONSEQUENTLY,
CLOCK LEVEL TASKS, LIKE THE BASE LEVEL TASKS, CAN BE WRITTEN WITHOUT
PRESERVING REGISTER STATUS.
	THE PURPOSE, OF CLOCK LEVEL TASKS, IS PRIMARILY FOR THE SCHEDULING OF
BASE LEVEL TASKS, OR POLLING DEVICES, ON A SPECIFIC INCREMENTAL BASIS.  DATA
OR I/O ANALYSIS AND CONVERSIONS ARE MEANT TO BE EXECUTED IN BASE LEVEL. AFTER
ALL, CLOCK LEVEL IS ENTERED EVERY 16.6 MS, NOT VERY MUCH TIME FOR A FOURIER
TRANSFORM. HOWEVER, IF ONE FINDS IT IMPERATIVE TO DO A FLOATING POINT CALCU-
LATION IN CLOCK OR OTHER INTERRUPT LEVEL, IBUF:,FPBUF:, ICHB:, AND FPCHB: MUST
HAVE THEIR VALUES SAVED AND RESTORED. ***QUEIO$C MUST NEVER BE EXECUTED
IN ANY INTERRUPT LEVEL, UNLESS YOU WANT GRIEF.

3.3	TIME OF DAY CLOCK

	LSIRT CONTAINS ONE SYSTEM CLOCK LEVEL TASK, THE REAL TIME CLOCK
(RTCLK:).  RTCLK'S VECTOR IS IN THE 1 SEC SLOT(UNOS:) OF CLK.  RTCLK
KEEPS THE TIME AS DAYS IN JULIAN FORMAT, AND THE HOURS,MINUTES, AND
SECONDS IN 24 HOUR CLOCK FORMAT.  
	RTCLK ACTIVATES 2 BASE TASKS, REFRESH CLOCK(RFCLK:) AND TIME
CHECK(TIMCH:).  RFCLK: CONVERTS THE BINARY FORMATTED TIME
IT TO ASCII FORMAT.  THE BINARY TIME IS IN BDAY,BHR,BMIN, AND BSEC,
AND THE ASCII TIME IS IN DAY,HR,MIN,SEC.
	TIMCH: IS AN APPLICATIION TASK USED TO ACTIVATE OTHER TASKS
ON A PARTICULAR TIME OF DAY BASIS.  FOR EXAMPLE, DATA MEANT TO BE READ
EVERY 6 MINUTES ON 6 MINUTE TIME OF DAY BOUNDRYS COULD HAVE ITS TASK
ACTIVATED BY TIMCH:(SEE 2.4).  IF TIMCH: IS NOT RELEVANT, THEN THE ACTIVATING
OF A NON-INSTALLED TASK(TIMCH:), BY RTCLK:, WILL DO NOTHING.

3.4	MARK TIME

	A MARK TIME MACRO DOES NOT EXIST, TRANSPARENT IMPLEMENTATION WOULD
ERODE THE SPEED AND SIMPLICITY FOR WHICH LSIRT WAS INTENDED(SEE 2.3).  HOWEVER,
A MARK TIME CAN BE EASILY IMPLEMENTED BY THE APPLICATION PROGRAMMER IN THE
FOLLOWING WAY -
	STEP 1) AT THE POINT IN THE BASE TASK WHERE THE MARK TIME IS DESIRED,
		SUSPEND EXECUTION OF THE TASK VIA THE RET INSTRUCTION.  CARE
		MUST BE TAKEN TO INSURE THE STACK IS IN ITS ENTRY CONDITION
		AND ANY RELEVANT VALUES IN THE REGISTERS WILL BE ABLE TO
		BE REFRESHED WHEN THE TASK IS REENTERED.
	STEP 2) INSTALL(INSTAL$ MACRO, SEE 2.1) THE LOCATION WHERE THE TASK IS
		TO BE REENTERED IN APPROPRIATE SLOT.
	STEP 3)	INITIATE EXECUTION(MOV ENTRY TO SLOT VECTOR) OF A CLOCK LEVEL
		TASK TO COUNT DOWN THE PERIOD OF TIME OF THE DESIRED DELAY.
		WHEN THE CLOCK TASK COUNTS DOWN, HAVE THE CLOCK TASK REMOVE
		ITSELF FROM THE CLOCK LEVEL VECTOR SLOT AND ACTIVATE THE
		BASE TASK USING THE ACTBT$ MACRO.
	STEP 4) BACK IN THE BASE TASK, THE TASK SHOULD REINSTALL ITSELF
		TO ITS ORIGINAL ENTRY POINT(UNLESS ANOTHER MARK TIME IS
		DESIRED).

	AN EXAMPLE OF THE STEP WISE APPROACH IS -
;
;	TO IMPLEMENT A 5 SECOND DELAY IN A TASK(MARK TIME)
;
	MOV	#5,COUNT	;INITIALIZE COUNTER
	MOV	#MARKT,UNOS+4	;USING 3RD SLOT OF 1 SEC TASKS
	INSTAL$	ENTRY2,25.	;THIS IS TASK 25.
	RET			;SUSPEND
;
ENTRY2:	INSTAL$ ENTRY1,25.	;ORIGINAL ENTRY POINT
	NOP			;CONTINUE REST OF TASK
;
;	THE CLOCK ROUTINE MARKT: WOULD BE
;
MARKT:	DEC	COUNT
	BEQ	1$		;COUNTED DOWN
	RET
1$:	MOV	#OFT,UNOS+4	;REMOVE SELF
	ACTBT$	25.		;REACTIVATE BASE TASK
	RET
;

	PLEASE NOTE THAT THE ACCURACY OF THE TIME DELAY IS WITHIN THE
THE UNIT OF THE CLOCK LEVEL SLOT USED.  IN THE EXAMPLE, THE DELAY WOULD
BE BETWEEN 5 AND 6 SECONDS.  IF MORE ACCURACY IS DESIRED, USE A SMALLER
UNIT TIME SLOT.  PUTTING 50 IN COUNT AND INSERTING THE MARKT: ROUTINE
IN A HUNM: SLOT, THE TIME DELAY WOULD BE BETWEEN 5.0 AND 5.1 SECONDS.
	IT IS CLEARER AND LESS MESSY TO HAVE SEPARATE TASKS FOR EACH ENTRY 
POINT.  SO EACH PHASE OF AN OPERATION, SEPARATED BY TIME DELAYS(MARK TIMES),
WOULD ACTUALLY BE A SEPARATE TASK.

4	SERIAL I/O

	AS STATED IN SECTION 1.2, SERIAL I/O IS EXPECTED TO BE IMPLEMENTED
VIA THE DLV11 SERIES INTERFACES.  OTHER INTERFACES WILL PROBABLY REQUIRE
MODIFICATION TO THE SOFTWARE.

4.1	OUTPUT

4.11	QUEIO$C MACRO

	SERIAL OUTPUT IS ACCOMPLISHED VIA THE QUEIO$C MACRO (WHICH CAN ONLY
BE EXECUTED BY A BASE LEVEL TASK).
	THE FORMAT OF THE QUEIO$C MACRO IS:
;
	QUEIO$C	CHANNEL NUMBER,ADDRESS FIRST CHAR,ADDRESS LAST CHAR
;
	FOR EXAMPLE:
;
	QUEIO$C	2,#INFO,#INFOE
;
	WOULD QUEUE UP THE ASCII STRING STARTING A INFO: AND ENDING AT
INFOE: FOR SERIAL OUTPUT FROM CHANNEL 2.  

4.12	DYNAMICS OF QUEIO$C

	THE QUEUEING PROCESS(INSRT:) PLACES A TASK TO INITIATE THE OUTPUT
OF THE STRING(D:, SEE MACRO EXPANSION) IN A LINKED LIST.IF THE OUTPUT
DRIVER IS NOT BUSY, THE PROCESS TO LOAD THE OUTPUT DRIVER(EXCX:) IS
ACTIVATED.  IF THE OUTPUT DRIVER IS BUSY, THE ACTIVATION OF EXCX:
(X IS CHANNEL NUMBER) WILL BE DONE BY OUTPUT DRIVER UPON COMPLETION
OF OUTPUTTING THE STRING IT IS CURRENTLY OUTPUTTING.

	THE STRINGS BEING OUTPUTED ARE NOT DOUBLE BUFFERED, WHICH
GIVES GREATER SPEED AND SIMPLICITY, BUT CAN CAUSE A PROBLEM IF THE
PROGRAMMER WISHES TO RELOAD THE STRING BUFFER AS SOON AS POSSIBLE.
THE PROGRAMMER CAN EITHER USE REAL TIME SCHEDULING, VIA ESTIMATING
HOW LONG IT WILL TAKE FOR THE MESSAGE TO BE OUTPUT, OR HE CAN ADD
A FEATURE TO EXECUTE A TASK UPON COMPLETION OF THE QUEIO$C.
	TO EXECUTE A TASK UPON COMPLETION OF A QUEIO$C, AN ARRAY, OF 16
ELEMENTS, CAN BE ADDED TO CORRESPOND TO THE 16 LINKS IN THE LINKED LIST.
THE ELEMENTS OF THIS ARRAY WOULD CONTAIN A TASK NUMBER TO BE ACTIVATED
UPON COMPLETION OF THE QUEIO. SO, EXC:, THE ROUTINE THAT ACTIVATES THE
THE ROUTINE IN THE PARTICULAR QUEIO(D:), WOULD HAVE A WORD THAT WOULD STORE
THE TASK NUMBER OF THE PREVIOUS TASK. UPON ENTRY TO EXC:, THE TASK NUMBER
IN THE WORD WOULD BE ACTIVATED VIA ACTBT$, AND BEFORE EXITING EXC: WOULD
RELOAD THE WORD WITH THE TASK NUMBER ASSOCIATED WITH THE CURRENT QUEIO ACTIVE.
THIS TASK NUMBER WOULD BE IN THE TASK NUMBER ARRAY, HAVING BEEN PUT THERE
BY INSRT:. THE QUEIO$C MACRO ITSELF WOULD NEED MODIFICATION TO PASS THE TASK
NUMBER PARAMETER TO INSRT:, ALONG WITH MODIFIICATIONS TO INSRT: AND EXC:.

4.13	OUTPUT DRIVER DELAY FEATURE

	PLEASE NOTE THE OUTPUT DRIVERS(OUT0: THRU OUT3:).  OUT2: IS
IN THE FORM OF ADDING 8 NULLS AFTER A <CR>, FOR THE OLDER PRINTERS
THAT MAY NEED THIS FEATURE.  OUT2: CAN BE CHANGED TO BE LIKE THE
OTHERS, OR ONE OR ALL OF THE OTHERS CAN BE CHANGED TO BE LIKE OUT2:.

4.14	MAG TAPE DRIVER

	LSIRT CONTAINS A MAG TAPE DRIVER FOR THE TC-130, OR EQUIVILANT, TYPE
TAPE DRIVE.  THE DRIVER CAN QUEUE UP TO 4 BLOCKS(SIZE DEFINED BY RECLEN)
WITHOUT LOSING INFORMATION.  THE DRIVER IS WRITE ONLY.
	THE ROUTINE TFIND: SEARCHES FOR AN AVAILABLE RECORD BUFFER. IF THE
SEARCH IS SUCCESSFUL, TFIND: RETURNS TO THE RETURN ADDRESS WITH THE LINK #
IN R2. THEN THE CORRESPONDING BUFFER, WHOSE ADDRESS IS FOUND AT TBUFP(R2),
CAN BE LOADED WITH THE RECORD. TASK #15 CAN THEN BE ACTIVATED(ACTBT$	15.)
TO WRITE THE RECORD.
	IF NO LINKS ARE AVAILABLE, TFIND: SKIPS THE RETURN ADDRESS. THEREFORE,
A CALL TO THE TFIND: SHOULD LOOK:
;
	CALL	TFIND		;GET A LINK
	BR	7$		;SUCCESSFUL RETURN
	RET			;NO LINKS, ALARM MESSAGE OUTPUT BY TFIND
;
7$:	ACTBT$	15.		;TURN ON TDO:
	MOV	TBUFP(R2),R0	;R0 IS POINTER TO BUFFER
	ETC.			;LOAD THE BUFFER
;
	TASK #15 MUST BE INSTALLED OF COURSE, TO WORK.
	THE MAG TAPE DRIVER HAS 3 ALARMS ALLOCATED(SEE 5.1).

4.2	INPUT

	THERE EXISTS NO QUEIO$C MACRO FOR INPUT.  INPUT QIO'S ARE ONLY
RELEVANT FOR SOME KIND OF FILE HANDLING,
4.21	INPUT DRIVER

	INPUT IS RECEIVED THRU THE INPUT DRIVERS(INP0: THRU INP3:).
THE INPUT DRIVERS(HEREIN REFERRED TO AS INPX:) RECEIVE THE CHARACTERS
FROM THE INPUT DEVICE(PROBABLY A KEYBOARD) AND PLACE THEM IN THE 
BUFFER INPBX:.

4.22	ECHO ROUTINES

	AFTER THE RECEPTION OF EACH CHARACTER, THE TASK TO ECHO THE
CHARACTER IS ACTIVATED(IN BTSK:,TASK ECHO X).  2 DIFFERENT ECHO
ROUTINES EXIST IN LSIRT FOR EACH CHANNEL(ECOTX: & ECOVX:). ECOTX:
IS FOR A LINE ORIENTED DEVICE, LIKE A TELETYPE, IT QUEUES FOR OUT-
PUT THE LAST CHARACTER RECEIVED.  ECOVX: IS FOR A POSITION ORIENTED
VIDEO SCREEN, IT QUEUES POSITIONAL COMMANDS AND THE ENTIRE COMMAND
LINE(CURRENTLY 20 CHARACTERS) TO THE SCREEN.  THE ECHO TASK DESIRED
IS THE ONE INSTALLED AT THE APPROPRIATE TASK SLOT.  FOR EXAMPLE:
;
	INSTAL$	ECOV2,9.	;INSTALLS ECHO FOR CHANNEL 2
;

4.23	DRIVER PROPERTIES

	INPX: RECOGNIZES BOTH THE <BACKSPACE> AND THE <RUBOUT> AS
DELETE PREVIOUS CHARACTER COMMANDS, AND THE <CR> AS THE END OF THE
LINE COMMAND.  UPON RECEIVING THE <CR>, IPNX: ACTIVATES THE TASK
TO INTERPERET THE COMMAND, OR RESPONSE(IN BTSK:, THE TASK MARKED 
MONITOR X).

4.24	INPUT MONITOR

	THE TASK SLOTTED AS MONITOR X CAN EITHER BE A COMMAND INTERPERETER,
OR A RECEIVER OF EXPECTED REPLYS.  RECEIVING REPLYS IS A GOOD EXAMPLE OF WHERE
THE PROGRAMMER MIGHT WISH TO INSTALL DIFFERENT TASKS IN THE SAME BASE LEVEL
SLOT DEPENDING UPON THE SITUATION AT THE TIME.  AS STATED IN 4.22, THE COMMAND
(OR REPLY) LINE IS CURRENTLY 20 CHARACTERS.  AN EXAMPLE OF AN INPUT
MONITOR(MON.MAC) IS INCLUDE FOR REFERENCE.

5	TRAPS

5.1	TRAP INSTRUCTION HANDLER

	LSIRT CONTAINS THE TRAP ROUTINE TP: TO DEAL WITH THE TRAP
INSTRUCTION.  TP: WAS DESIGNED TO USE THE TRAP INSTRUCTION AS A SOFTWARE
ERROR HANDLER.  IT PRINTS AN ALARM MESSAGE TO THE CHANNEL ASSIGNED TO
THE TRAP CHANNEL(SEE 1.2).  FOR EXAMPLE -
;
	TRAP	66	;WOULD GENERATE
;
*** ALARM # 6 198 09:38:23
;
IF IT WAS DAY 198 AND TIME 09:38:23, WITH RTCLK: AND RFCLK: FUNCTIONING.
	THE ALARM MESSAGE IS PRINTED VIA POLLING THE OUTPUT DEVICE, SO IF
THE LINKED LIST FOR QUEUING IS THRASHED, IT WILL STILL WORK.
	IN LSIRT, FOR EXAMPLE, AN ALARM #1 MESSAGE IS OUTPUT IF NO
AVAILABLE LINKS ARE FOUND WHILE TRYING TO QUEUE A SERIAL OUTPUT.
	ALARMS #1 THRU #5 & #8 ARE RESERVED.  THEY ARE:

	#1	NO LINKS AVAIILABLE FOR A SERIAL OUTPUT QUEIO$C.
		MESSAGE LOST.

	#2	LINKED LIST FOR OUTPUT QUEIO'S IS SCREWED UP.

	#3	MAG TAPE LINKED LIST FOR QUEUEING IIS SCREWED UP.

	#4	NO AVAILABLE LINKS IN MAG TAPE LINKED LIST.

	#5	TAPE DRIVE OFF LINE WHILE ATTEMPTING A WRITE.

	#8	NO WRITE RING ON TAPE REEL.


5.2	FORCED TRAPS

	FOR THE FORCED TRAPS(TIMEOUT,ILLEGAL INSTRUCTION, ETC.), THE
ROUTINE DUMP: IS USED TO PRINT THE CONTENTS OF THE REGISTERS AND THE
TOP 8 POSITIONS OF THE STACK. FOR EXAMPLE, AN FIS TRAP GENERATED:
;
*** ALARM # F 198 07:04:33
014662	;R0
021476	;R1
010606	;R2
001736	;R3
000000	;R4
061322	;R5
001710	;R6 AT THE TIME
005454	;IGNORE
010610	;TRAPPED PC COUNTER
000012	;TRAPPED PSW
036243	;TOP OF STACK BEFOR TRAP
163006
001520
160725
007554
000000
000000
000000
	;NOTE, IT DID NOT GENERATE THE COMMENTS
;
	IN THIS PARTICULAR CASE, THE TRAP OCCURED IN THE FPPAK
PACKAGE, WHICH USES R6 FOR ITS DATA STACK AND STORES THE LOCATION
OF THE RETURN OF THE ROUTINE THAT CALLED IT(VIA EMT) IN R5.  SO
IT WAS DISCOVERED THAT UNDERFLOW OCCURED WHILE DOING A TAYLOR
EXPANSION SERIES.  THE FORM OF LSIRT INCLUDES THE CODE THAT DEALT
WITH THIS SITUATION, BY ADJUSTING THE STACK TO KEEP THE ORIGINAL
DESTINATION THE RESULTING DESTINATION AND SETTING A FLAG(FPTPF:,
IN LSIRAM) TO TELL THE EXPANSION ROUTINE TO IGNORE ANY MORE ELEMENTS.

5.3	BREAK POINTS

	THE CODE TO HANDLE A BREAK POINT TRAP IS VERY SIMILAR TO
THE FIS TRAP, EXCEPT THE STACK IS LEFT IN ORIGINAL FORM. ***PLEASE
NOTE THAT BPT INSTRUCTIONS MUST BE INSERTED IN SOURCE FORM AND
BE ASSEMBLED INTO THE OBJECT CODE, OVERLAPPING INSTRUCTIONS WITH
BPT'S WILL NOT WORK.  HOWEVER, BY INSERTING NOP INSTRUCTIONS THRUOUT
THE CODE DURING THE DEBUGGING PHASE, ONE CAN OVERLAP ANY NOP WITH A BPT.

	THE CODE IN THE ROUTINES TO HANDLE THE FORCED TRAPS(BPT
INCLUDED) IS NOT MEANT TO BE RIGID.  IT IS INTENDED THAT THE USER WILL
MODIFY THEM TO THE FORM THAT BEST SUITS HIS NEEDS. A SIMPLE EXAMPLE
WOULD BE TO PUSH CERTAIN MEMORY LOACTIONS OF INTEREST IN BPT: BEFORE
DUMP: IS CALLED SO THEY CAN BE EXAMINED AUTOMATICALLY(DON'T FORGET TO
POP THEM).  OR, MODIFYING THE NUMBER OF STACK ELEMENTS LISTED(IN DUMP:).

6	AUDITS AND DIAGNOSTICS
	
	THE SPARE TIME THE CPU HAS CAN BE USED FOR AUDITS AND ON LINE
DIAGNOSTICS.  ON LINE DIAGNOSTICS ARE SELF EXPLANITORY, AUDITS ARE A
SIMPLE TECHNIQUE THAT CAN SPOT TROUBLE BEFORE IT CAUSES SIGNIFIGANT
DAMAGE.
	AUDITS ARE LOW PRIORITY TASKS(EXECUTED ONLY WHEN CPU WOULD BE
IDLE) THAT CONTINOUSLY VERIFY THE INTEGRITY OF THE SYSTEM DATA STRUCTURES.
A PRIME EXAMPLE WOULD BE AN AUDIT OF THE LINKED STRUCTURE USED TO QUEUE
THE SERIAL OUTPUT REQUESTS(QUEIO$C). INSTEAD OF WAITING UNTIL AN ALARM #2
(SEE 5.1) TO FIND OUT THE LINKED STRUCTURE IS FAULTY, AN AUDIT COULD
DISCOVER IT AND CORRECT IT BEFORE ANOTHER MESSAGE IS LOST. (A MESSED UP
LINKED STRUCTURE IS PROBABLY A SIGN OF A QUEIO$C EXECUTED IN AN INTERRUPT
LEVEL).
	A SIMPLE EXAMPLE OF AN AUDIT IS TO LOOK AT WORDS, OR BYTES, THAT
ARE MEANT STORE VALUES WITHIN SPECIFIC RANGES.  IF A WORD IS USED TO
STORE THE NUMBER OF ACTIVE SOLENOIDS IN SYSTEM THAT HAS 56 TOTAL, A VALUE
IN THAT WORD OF 2045 WOULD OBVIOUSLY BE AN ERROR.
	AUDITS CAN HELP FIND SUBTLE LITTLE PROBLEMS(USUALLY SOFTWARE) THAT
MIGHT NOT SHOW UP IMMEDIATELY, OR AT ALL, EXCEPT FOR UNDETECTED ERRONEOUS
RESULTS.
	AS STATED IN SECTION 2.3, ALL TASKS SHOULD EXECUTED RAPIDLY. AUDITING
THE ENTIRE SYSTEM COULD BE A NUMBER OF TASKS, WHERE EACH TASK COULD BE ITERA-
TIVE IN NATURE.
	AUDITS CAN ALSO SHOW THE SYSTEM BOTTLENECKS, SO SITUATIONS CAN BE
MODIFIED BEFORE DISASTER STRIKES.  AN EXAMPLE OF A BOTTLENECK IS A
MODEM SERIAL CHANNEL.  UNLIKE 'NORMAL' TERMINAL CHANNELS, MODEMS CHANNELS
CANNOT TRANSMIT WITHOUT THE PROPER ENABLING SIGNAL.  IF THAT SIGNAL GETS
HUNGUP BECAUSE OF HARDWARE, OR SOME BOZO REQUESTING INFORMATION OVER THE
PHONE LINE AND THEN HANGING-UP, AS SOON AS THAT LINE BECOMES ENABLED, A
SERIES OF MESSAGES WILL UNLOAD. AN EXAMPLE OF AN AUDIT THAT DEALS WITH THIS
PROBLEM IS:
;
;	MODEM CHANNEL AUDIT
;
MAUD:	MOV	#17,R0		;MASK FOR MORE THAN 12 MESSAGES QUEUED
	PUSH	LAVL2		;LINKS AVAILABLE
	BIC	#177760		;DON'T CARE ABOUT UP TO 12
	XOR	R0,(SP)+	;CHECK IT
	BNE	1$		;OVER 12 QUEUED
	RET			;EVERYTHING COOL
;
1$:	TRAP	67		;PRINT ALARM MESSAGE
	CLR	FPM6		;CLEAR FLAGS THAT GENERATE MESSAGES
	CLR	BCDM6
	MOV	#177777,LAVL2	;CLEAR OUT LINKED STRUCTURE
	MOV	#HEAD2,HEAD2
	MOV	#TAIL2,HEAD+2
	MOV	#HEAD2,TAIL+2
	MOV	#TAIL2,TAIL2
	RET
;
	A SIMILIAR AUDIT COULD BE USED ON ANY CHANNEL JUST FOR ANALYSIS.
POSSIBLY AFTER BEING IN OPERATION FOR A PERIOD OF TIME, AUDITS MIGHT
SHOW THAT THE LINKED STRUCTURE NEEDS TO BE BIGGER.  IN THE SAME MANNER
ANY DATA STRUCTURE THAT ALLOCATES SYSTEM RESOURCES CAN BE AUDITED AND
ANALYZED, TO HELP THE SYSTEM DESIGNER HAVE A BETTER UNDERSTANDING OF THE
SYSTEM.

6.1	BASE TASK AUDIT

	THE BASE TASK AUDIT, BAUD:, IS A CLOCK LEVEL TASK EXECUTED FROM
THE ALLK:+2 SLOT OF THE VECTOR TABLE. IT DETERMINES IF ANY BASE TASKS ARE
EXECUTING LONGER THAN SOME PREDETERMINED NUMBER OF TICKS.  IF A TASK TIMES-
OUT, A MESSAGE TO THAT EFFECT IS QUEUED ON CHANNEL 3, STATING:
;
TASK #23 TIMEOUT
;
IF TASK # 23 WAS THE CULPRIT.
	BAUD: IS ACTIVATED BY PUTTING THE TICK LIMIT IN MAXTSK:, AND INSERTING
IT VECTOR IN ALLK:+2:
;
	MOV	#BAUD,ALLK+2
;
	IF A TASK TIMSOUT, BAUD: PRINTS THE MESSAGE AND DEACTIVATES ITSELF.

6.2	LOAD SHARING

	THE MOST SEEMINGLY FOOLPROOF SYSTEM IS A MULTIPROCESSER CONFIGURATION
WITH 3 OR MORE PROCESSERS RUNNIING IN REDUNDANCY.  ANY DISAGREEMENT BETWEEN
PROCESSERS WILL BE DEALT WITH VIA MAJORITY RULES.
	TRIPLE REDUNDANCY, FROM THE HARDWARE POINT OF VIEW, IS EXPENSIVE. UN-
LESS ERRONIOUS OPERATIONS CANNOT BE TOLLERATED OVER A FEW MICROSECONDS, IT IS
ALSO UNNECESSARY.
	FROM THE SOFTWARE POINT OF VIEW, TRIPLE REDUNDANCY MEANS TRIPLE CRASH,
IF A FATAL BUG OCCURS. LOAD SHARING CAN BE AN ATTRACTIVE ALTERNATIVE.
	LOAD SHARING IS MULTIPROCESSER CONFIGURATION WHERE EACH PROCESSER
DOES PART OF THE WORK, OR 'SHARES' THE SYSTEM LOAD.  EACH CPU CAN SPEND A
SIGNIFIGANT PART OF ITS 'FREE' TIME DOING DIAGNOSTICS AND AUDITS ON THE
OTHER CPUS.  POSSIBLY, A QUICK LITTLE AUDIT WILL BE GIVEN HIGHEST PRIORITY
BY EACH CPU TO VERIFY THE NO OTHER CPU HAS CRASHED.  BY LIMITING ANY TASK
TO A SPECIFIC INTERVAL, USING THE BASE TASK AUDIT, THE MAXIMUM INTERVAL OF
ERRONIOUS OPERATION OF ANY CPU IS DETERMINED.  AUDITS FOR MORE SUBTLE
DISCREPENCIES SHOULD BE LOW PRIORITY.
	UPON SENSING THE FAILURE OF ANOTHER CPU, THE PROCESSER CAN RESTORE
SANITY TO THE SYSTEM, BY ELIMINATING THE CULPRIT, OR RESTARTING HIM.
	THE BIG ADVANTAGE TO LOAD SHARING IS THAT A FATAL SOFTWARE ERROR
WILL NOT TOTALLY CRASH THE SYSTEM. EVEN THO ALL THE CPUS MAY ENCOUNTER THE
BUG AT ONE TIME OR ANOTHER, AS LONG AS THE DIFFERENT CPUS DON'T ENCOUNTER
IT AT THE SAME TIME, THE SYSTEM SHOULD SURVIVE. IN SOME VERY COMPLEX SYSTEMS,
FATAL BUGS MAY LIE DORMANT FOR WEEKS.
	THE OTHER OBVIOUS ADVANTAGE TO LOAD SHARING OVER REDUNDANCY IS IN-
CREASED UTILITY OF THE HARDWARE. THE MAXIMUM INTERVAL OF ERRONIOUS OPERATION
TOLLERABLE OF MOST SYSTEMS IS MILLISECONDS, WELL WITHIN THE CAPABILITIES OF 
LOAD SHARING.

7	MACROS

	THE MACROS IN MACLIB WILL BE BRIEFLY DISCUSSED.  FOR FURTHER
ANALYSIS USE THE /EX:MACRO SWITCH IN LBR TO GENERATE A LISTING OF THE
MACRO.

7.1	SYSTEM MACROS

	ACTBT$,INSTAL$, AND QUEIO$C ARE LSIRT SYSTEM MACROS, AND HAVE
ALREADY BEEN DISCUSSED.

7.2	INSTRUCTION SUBSTITUTION

	'OR, PUSH, POP, CALL,' & 'RET' ARE MACROS THAT GENERATE ONE
INSTRUCTION, BUT ARE MORE SELF DESCRIPTIVE THAN THE DEC MNEMONICS
FOR THE COORESPENDING INSTRUCTIONS.
	'AND' IS A MACHINE INSTRUCTION TO MOST COMPUTERS.  FOR THE
PDP/11, IT IS A MULTI-INSTRUCTION MACRO.

7.3	JUMP ON CONDITION

	16 JUMP ON CONDITION MACROS EXIST IN MACLIB.  THERE PURPOSE IS
TO BE USED IN SITUATIONS WHERE THE RANGE(128 WORDS) OF THE BRANCH ON
CONDITION INSTRUCTIONS IS INADEQUATE.  THE JUMP ON CONDITION
HAS THE SAME MNEMONIC FORM AS THE BRANCH ON CONDITION, EXCEPT A 'J'
IS PUT IN PLACE OF THE 'B'.

7.4	FLOATING POINT MACROS

	21 MACROS TO IMPLEMENT FLOATING POINT OPERATIONS VIA THE FLOAT-
ING POINT PACKAGE(FPPAK) EXIST IN MACLIB.  THE MNEMONIC FORM OF THE
MACROS MAKES THEM SELF EXPLANATORY, BUT IF CONFUSION ARISES, REFERENCE
THE FIRST PAGE OF THE SOURCE LISTING OF FPPAK.
	PLEASE NOTE THAT FPPAK EXPECTS TO USE THE FIS INSTRUCTIONS. FPPAK
WILL NOT WORK ON A MACHINE WITHOUT FIS CAPABILITY.
	PLEASE ALSO NOTE THAT THE DISCUSSED MACROS ONLY USE THE STRAIGHT
FORWARD SOURCE-DESTINATION MODE OF ADDRESSING OF FPPAK.  OTHER ADDRESSING
MODES EXIST IN FPPAK(SEE SOURCE LISTING).
	FINALLY, NOTICE THAT FPPAK USES THE EMT INSTRUCTION, SO AN EMT
CANNOT BE USED FOR ANYTHING ELSE.
	AS STATED ABOVE, THE MACROS USE THE SOURCE-DESTINATION MODE OF
ADDRESSING.  FOR SIMPLICITY, IT IS RECOMMENDED THAT THE LOCATIONS IBUF:,
FPBUF:,ICHB:, AND FPCHB: ARE USED WITH THE FP MACROS. FOR EXAMPLE -
;
	MOV	R0,IBUF		;PUT # IN INTEGER BUFFER
	FLT$	IBUF,FPBUF	;FLOAT #
	MULF$	FP077,FPBUF	;FP MULTIPLY
	FTOA$	FPBUF,FPCHB	;FORM ASCII
;
FP077:	.FLT2	.077
;
	IF THE INTEGER TO BE MADE FLOATING POINT IS IN MEMORY LOCATION,
IT IS OK TO USE THE FLT$ MACRO DIRECTLY(FLT$	X,FPBUF).
	THE CHARACTER BUFFERS, ICHB: AND FPCHB:, HAVE TO BE USED IF THE
FORMATTING MACROS ARE TO BE USED.

7.5	NUMERIC FORMATTING

	TRANSF$ NAD TRANSI$ ARE THE FORMATTING MACROS.  THEY USE THE
SAME PARAMETERS AS THE 'I' AND 'F' DESIGNATIONS IN THE FORTRAN FORMAT
INSTRUCTION. THE DEFAULT EXPECTAIONS OF THE MACROS ARE -

	A)	THE POINTER TO THE LOCATION OF THE FORMATTED ASCII
		NUMBER(THE OUTPUT) IS IN R3.

	B)	THE UNFORMATTED ASCII INPUT, IS EXPECTED TO BE IN
		ICHB: IF AN INTEGER(TRANSI$), OR FPCHB: IF FLOATING
		POINT(TRANSF$).

	FOR EXAMPLE, CONTINUING FROM THE CODE IN SECTION 7.4 -
;
	FTOA$	FPBUF,FPCHB	;FORM ASCII(CONT')
	MOV	#RESULT,R3	;RESULT IS ASCII BUFFER FOR OUTPUT
	TRANSF$	7,3		;SAME AS F7.3 FORMAT
	QUEIO$C	3,#RESULT,#RESULT+6	;OUTPUTS FORMATTED ASCII OUTPUT
					;TO CHANNEL 3
;
	OR, IN THE CASE OF INTEGERS -
;
	MOV	R1,IBUF		;INTERGER IS R1
	ITOA$	IBUF,ICHB	;FORM ASCII
	MOV	#RESULT,R3	;POINTER TO R3
	TRANSI$	5		;SAME AS I5 FORMAT
	QUEIO$C	3,#RESULT,#RESULT+4	;OUTPUTS FORMATTED ASCII OUTPUT
					;TO CHANNEL 3
;
	ALSO NOTE, THAT -
;
	ADD	#3,R3
;
	IS THE SAME AS THE X3 FORMAT, PROVIDING THE ASCII BUFFER HAS BEEN
INITIALIZED WITH BLANKS.
7.6	PFOR

	PFOR IS 'POSITION OF FIRST ONE & RESET'.  IT IS USED TO SCAN WORDS
FOR SET BITS, IT RETURNS THE COLUMN #(LEFT TO RIGHT SCAN) OF THE FIRST SET
BIT, RESETS THE BIT, AND SKIPS A WORD.  IF NO SET BITS ARE FOUND, THEN
PFOR DOES NOT SKIP THE NEXT WORD(EXPECTED TO BE A BRANCH INSTRUCTION).  IN
OTHER WORDS, IT IS A SOFTWARE PRIORITY ENCODER.