The 16-Bit Myth The most severe perceived fault of a PDP-11 is its 16-bit address. However, the LSI-11/2 was the last computer DIGITAL built which limited applications to only 16 bits. There is a world of difference between a 16-bit virtual versus physical address limit. This series of articles looks at various techniques RSX programmers may use to map 16-bits of virtual address space to 4 million bytes of memory. This month's column covers standard task builder features which let you build large programs. Future columns will cover the Program Logical Address Space (PLAS) executive directives and how data flow analysis and proper task design can solve problems with 16-bit addresses. One obvious solution to the 16-bit address is upgrading from a PDP-11 to a VAX system. Indeed, VAX systems are the best solution if you have open-ended applications. VMS is far superior to RSX as a general-purpose, departmental computer system. But VAX systems are not the most cost effective solution to all problems. RSX is just as good or better then VMS for solving dedicated applications which require large address space. The cost of the additional RSX programming needed to match VMS virtual address capabilities is more than offset by the lower hardware and operating system costs, especially when a system will be replicated several times. Before looking at solutions to the 16-bit address, you need to understand the problem. A PDP-11 CPU uses 16-bit memory addresses. The PDP-11 memory unit is an 8-bit byte, thus a PDP-11 CPU can read and write 65,536 bytes of memory. This total is more commonly expressed as 64KB (64 times 1024 bytes). Early PDP-11 CPU's placed 16-bit addresses directly on the UNIBUS (and later the Q-Bus). By convention, memory would respond to addresses 0 to 160000(8) and I/O devices would listen to any references in the 160000 to 177777 range. This later 8KB region is known as the I/O page. This architecture limited user programs to 56KB minus whatever space was permanently occupied by the operating system. The PDP-11/40 and 11/45 added a level of abstraction between CPU and memory addresses. The UNIBUS was actually designed with 18 address lines. The high two lines were unused in the original CPU's. PDP-11/40 and 11/45 systems have an optional memory management unit which maps the 16-bit CPU address to an 18-bit memory address. Figure 1 shows how the calculation is performed. The memory management unit splits the 16-bit CPU address into three parts: the Active Page Field (APF), Block Number (BN), and Displacement in Block (DIB). The APF (bits 15-13) selects one of eight memory management registers. This register's contents are added to the Block Number (bits 12-6) to form a 12-bit physical block number. The DIB (bits 5-0) is joined with the physical block number to yield a true 18-bit physical address to place on the Unibus. The APF field actually selects two registers. The Page Address Register (PAR) mention above supplies the Block Number base address. The Page Descriptor Register (PDR) contains information related to memory protection. One field in the PDR determines if no access, read-only, or read-write access is allowed. The high byte of the PDR determines how many 64 byte blocks are mapped by the PAR base address. PDP-11 memory management allows a RSX program to manipulate its virtual 64KB address space to map a much larger physical address space. There are several key relationships which result from the memory management mechanism. The 3-bit APF selects one of eight memory management registers, thus virtual address space is divided into eight 8KB pages. The 6-bit DIB field means memory management registers have a resolution of 64 bytes. RSX always allocates physical memory in 64 byte blocks chunks. The I/O page is still the top 8KB of the physical address space. The memory management registers are located in the I/O page at standard addresses. The RSX operating system simply uses MOV instructions to point PAR registers at different parts of physical memory and change PDR lengths. Starting with the PDP-11/70 processor, memory management units translate 16-bit CPU addresses into 22-bit memory addresses. The new memory management registers use a full 16-bit Block Number. The PDP-11/70 uses a separate memory bus to circumvent the limit of 18 Unibus address lines. Another logic unit, the Unibus Mapping Registers or UMR, is used to map 18-bit Unibus addresses to 22-bit memory addresses. UMR's are managed by the operating system and can be ignored at the application level. The Q-Bus was designed with 22 address lines, so separate memory bus and UMR logic are not needed, although the PDP-11/83 uses a Private Memory Interconnect (PMI) for performance improvements. The PDP-11/23, PDP-11/24, PDP-11/34, and PDP-11/40 memory management units provide two sets of memory management registers: kernel and user. The Processor Status Word state flags determine which set to use to resolve CPU memory addresses. Kernel is the most privilege mode and is used by the RSX executive to map itself. User mode is used by all tasks. Current PDP-11 systems have 6 sets of memory management registers. The CPU executes in three different states: kernel, supervisor, and user. Each state has separate memory management registers for access to instructions versus data. This feature is commonly known as I/D space. The additional memory management capabilities are not exploited by RSX-11M. RSX-11M-Plus, however, provides user programs full access to the various features of the memory management unit. Any techniques which involve supervisor mode or I/D space apply only to RSX-11M-Plus or Micro/RSX. Other material applies to all versions of RSX. The 16-bit problem is solved by making virtual addresses perform multiple jobs. Tasks manipulate the user-mode memory management registers using the Program Logical Address Space directives (PLAS) to change the mapping of virtual addresses. In one instance, virtual address 160100 could be an entry into a resident library. After the appropriate RSX directives, address 160100 could reference an array in some resident common. In many cases, no special programming is needed to manage virtual address space. The following are five standard task builder features which increase the virtual address space available for your task: I/D space, overlays, resident libraries with memory-resident overlays, cluster libraries, and supervisor-mode libraries. The easiest method to gain both code and data space is to separate a task's instructions from data and take advantage of the user mode I/D space memory management registers. The task now has a virtual 64KB instruction and 64KB data address space. Creating an I/D space task is simple. Macro-11 programmers must use the .PSECT directive to define whether code is instructions or data. No special work is needed for high-level languages. The various PDP-11 language compilers output object code with program sections already marking instructions and data. An I/D space task is built by using the TKB /ID switch on the task image file. The task builder collects instructions and data program sections into the correct format needed by RSX-11M-Plus to run the task using both the user I-space and D-space memory management registers. Overlays are the traditional method for linking large programs. An RSX overlay is a tree-like structure which divides conventional tasks into segments of one or more object modules. Tasks can exceed 64KB because overlay segments at the same level in the tree occupy the same virtual address space. When a lower level references a routine in a particular segment, the overlay run-time system loads and maps the entire segment. This mechanism requires segments at the same level be logically independent, that is, the modules in one segment cannot reference any routines in another segment with which it shares virtual address space. RSX supports two overlay mechanisms: disk and memory-resident. Overlay segments are loaded from disk in the first case, so segments share both virtual and physical memory. Memory-resident overlays load all code into physical memory and update the memory management registers to reference different segments. Disk overlays use virtual memory much more efficiently than the memory-resident technique. A disk overlay can start on any word boundary while PDP-11 memory management unit requires all memory-resident overlays to begin 8KB boundaries in the virtual address space. A 100 byte memory-resident overlay segment occupies 8KB of virtual address space. Disk overlays are thus preferred to memory-resident overlays. Exception to this rule are resident libraries with memory-resident overlays and when the overhead of disk I/O used to load overlay segments becomes a substantial performance factor. The main disadvantages of overlays is increased overhead from loading or mapping overlay segments and problems designing overlay tree structures. Overlay tasks also take noticeably longer to link. The final three TKB features involve different versions of resident libraries. RSX uses resident libraries to save physical memory by sharing common code between two or more tasks. The common code is linked as a normal task, except there is no task header. A symbol table file also produced. The symbol table or STB file defines the various entry points into the resident library task image. Tasks link to the library by referring to the symbol table file using the LIBR or RESLIB option statements. When you run a task linked to a resident library, memory management registers are used to map the resident library into the task virtual address space. Using a normal, flat resident library always costs a task virtual address space. Each memory management register used to map a resident library takes 8KB of virtual address space. A 7KB library occupies 8KB virtual address space. Furthermore, it is very rare for a task to reference all routines in a resident library. If a task uses 6KB of routines in the 7KB library mentioned above, 2KB of virtual address space is effectively wasted. Many applications never even come close to using the entire 64KB virtual address space and thus do not have to be concerned about any wasted space from using resident libraries. If a task does grow too large, simply stop linking to the resident library. Standard flat resident libraries save physical memory, but not virtual memory. Three special versions of resident libraries can to both. The first is a resident library built with memory-resident overlays. Such libraries allow multiple overlay segments to be mapped with a single memory management register. For instance, a resident library with 6Kb and 7KB overlay segments has a total of 13KB code using only 8KB of virtual address space. Each task linked with these libraries uses the standard overlay run-time system to map the called overlay segment. Cluster libraries allow multiple resident libraries to all use the same virtual address space, even if one library makes references to another! Cluster libraries uses the same mechanism as resident libraries with memory-resident overlays, only now the overlay run-time system will switch between resident libraries as needed. Cluster libraries are most widely used when a single task must use multiple RSX options such as FMS, RMS, and language run-time systems. Supervisor-mode libraries increase available instruction space by moving code from user I-space to supervisor I-space. There are very rigid rules for creating supervisor-mode libraries. It is probably not worth the effort to move user-written code to a supervisor-mode library. However, Digital supplies a supervisor-mode library of the File Control Services (FCS) and other common routines which can be linked using the task builder SUPLIB=FCSFSL:SV option. Programs which use the Record Management Services (RMS) to do I/O can link to LB:[3,54]RMSRES as a supervisor-mode library. See Chapter 8 of the RMS-11 User's Guide for further information. Thus far we have looked at five different task builder features which can help expand virtual address space. Creating I/D space tasks on systems with the necessary hardware simply involves using the TKB /ID switch. Disk overlays save both physical and virtual address space, but add overhead and can be difficult to setup. Check with your system manager to find out if any standard resident libraries with memory-resident overlays, cluster libraries, or supervisor-mode libraries are available. All of these features are documented in the RSX Task Builder manual. Next month's column will cover how the Program Logical Address Space (PLAS) directives are used. An example of a subroutine package for managing a 32-bit address space will show how PLAS directives can make it simple to work with large sets of data.