.TITLE qaPREF ; ; prefix file for qa driver to implement dr-11w driver ; ; .mcall ucbdf$ ; EQUATED SYMBOLS ; ;deb=0 ; conditional for debugging okdma=1 ; dma transfer conditional q$$a11=1 ; one device LD$qa=0 ; DEFINE LOADABLE DRIVER CNTBL=1 ; SINGLE UNIT CONTROLLER DRWCR=-4 ; CSR BASE. WORD COUNT REGISTER DRBAR=-2 ; BUS ADDRESS REGISTER DRCSR=0 ; CSR/ERROR REGISTER DRIDR=2 ; INPUT/OUTPUT REGISTER ; ; csr bit definitions ; qaGO=000001 ; GO BIT FUNCT1=000002 ; FUNCTION 1 FUNCT2=000004 ; FUNCTION 2 FUNCT3=000010 ; FUNCTION 3 qaBA=60 ; EXTENDED ADDRESS BITS qaIE=000100 ; INTERRUPT ENABLE READY=000200 ; READY BIT qacycl=000400 ; cycle bit qasta1=001000 ; status bit 1 qasta2=002000 ; status bit 2 qasta3=004000 ; status bit 3 qamain=010000 ; maintenance bit qaATTN=020000 ; ATTENTION BIT qaNEX=040000 ; non existent memory qaERR=100000 ; error bit set to read eir qafnt=16 ; function bit mask; ; ; unit control block extension ; ucbdf$ ; u.exp=u.cnt+4 ; interrupt expected storage u.csr=u.cnt+6 ; csr storage u.bar=u.cnt+10 ; bar register u.Eir=U.cnt+12 ; error register storage .if ne okdma u.wcr=u.cnt+14 ; ucb extension for word count reg .iff u.idr=u.cnt+14 ; i/o register .endc ; qaexp=000001 ;interrupt expected bit ;used to flag extra interrupt ; local macros ; .macro dsabl ,pr mfps -(sp) ;save old value mtps #pr ;set pr level .endm ; .macro enabl mtps (sp)+ .endm ; .macro delay ,n ,?l mov r0,-(sp) ;save r0 mov #n,r0 ;get delay count l: dec r0 ;decrement bgt l ;loop until done mov (sp)+,r0 ;restore r0 .endm ; .macro reset ; enter with csr base in r2 dsabl pr5 ;disable interrupts movb #,drcsr+1(r2) ;set maintenance bit clrb drcsr+1(r2) ;clear maintenance bit delay 11 ;approx 10 microsecond delay mov #qaie,drcsr(r2) ;set interrupt enable enabl ;enable interrupt .endm ; ; DRIVER SUBFUNCTIONS ; IO.RES=4 ;io reset subfunction IO.SFT=2 ;io set function code IO.STO=10 ;io set time out