DL Device CSRs



	Author:	Richard Neitzel
		312 Laveta Pass
		Golden, CO 80401









	As you know, DL devices, especially the DLV-11J, now the 
     DLVJ-1, have a problem in losing interrupts when the interrupt enable 
     bit in the receive control status register (rcsr) is cleared. This 
     hardware flaw means that your DL line suddenly goes dead for input. If 
     like us you are using it for serial communications this is a serious 
     problem, since normally the only recourse is to reboot. Fortunately, 
     you can directly access the rcsr and test the interrupt enable bit 
     (ieb). If it is zero, the ieb can be set to restart the line.

	Unfortunately, it must be remembered that the operating system 
     has no knowledge of the DL locking up, which in turn means that your 
     program gets no indication of the problem either. As result, you must 
     be very careful. Issuing a Fortran read or a qiow directive means that 
     the program will sit forever waiting on the DL. The qiow directive can 
     specifiy a time out, but you won't know why it occured. Similarly, a 
     qio will continue to show an I/O status of zero forever, so testing 
     the status as a means of determining completion is risky. Use time outs
     again. When a time out occurs, in order to determine what happened the 
     easiest thing to do is to spawn a program similar to CSET.MAC, which 
     returns a status that tells if the interrupt bit was set. If it was 
     not then you know why the time out occurred and can act accordingly.

	The routines supplied to 'diddle' the ieb are as follows:
		set.mac - Set the ieb.
		clr.mac - Clear the ieb.
		cset.mac - Check ieb, set if clear and return status.
		conset.mac - Continuously check and set ieb if clear.
     They all are coded for the system console, but it's trival to change 
     them to work for any other terminal. Have fun!