.DSABL GBL ; ; MACRO DEFINITIONS FOR MIOP PROGRAM ASSEMBLY ; ; INSTRUCTIONS: ; MV,INM,DEM,AD,SB,IOR,EOR,AND,BCT,BCF,ST,LD ; ; REGISTERS: ; T,ILR,FCNA,WCR,TMP4,QCNT,XCNT,BADD,BSIZ,PSR(PC),MDR,BDL,BDH ; PDR,MAR(ISR),BAR(SWR) ; ; MODIFIERS: ; RDH,RDR,WTR,BRR,BRW,BRC,BGL,EXM,EXC,EXT,INT,CLRC,WTH,BREQ, ; IMM ; ; TEST CONDITIONS: ; DCD,BRD,O,N,Z,BZ,C,Q,X,B10,B11,B12,B13,B14,B15 ; .NLIST ; ; Register definitions ; T = 0 ; TEMPORARY REGISTER ILR = 1 ; INSTRUCTION LOGIC REGISTER (GETS COMMANDS) FCNA = 2 ; THIS REGISTER HOLDS FCNA WCR = 3 ; WORD COUNT REGISTER TMP4 = 4 ; REGISTER 4 QCNT = 5 ; Q ERROR COUNTER REGISTER XCNT = 6 ; COUNTS NUMBER OF X ERRORS BADD = 7 ; Current buffer address BSIZ = 10 ; Currrent buffer size PSR = 11 ; PROGRAM STATUS REGISTER MDR = 12 ; MEMORY DATA REGISTER BDL = 13 ; BRANCH DATA LO REGISTER (16 LO BITS 0-15) BDH = 14 ; BRANCH DATA HI (BITS 16-23) PDR = 15 ; PROGRAM DATA REGISTER ISR = 16 ; INTERNAL STATUS REGISTER (CHAN #) (source) MAR = 16 ; MEMORY ADDRESS REGISTER (destination only) SWR = 17 ; SWITCH REGISTER (source only) BAR = 17 ; Branch address register (destination) ; ; Instruction definitions ; NOP = 0 ; NO,OPERATION INSTRUCTION PUTS ZERO IN T RTN = 120000 ; RETURN INSTRUCTION NO S ALLOWED IMM = 7400 ; IMMEDIATE RH BYTE = SOURCE SLL = 150000 ; SHIFT LEFT LOGICAL SRL = 154000 ; SHIFT RIGHT LOGICAL SLLD = 151000 ; SHIFT LEFT LOGICAL DOUBLE SRLD = 155000 ; SHIFT RIGHT LOGICAL DOUBLE SLR = 152000 ; SHIFT LEFT ROTATE SRR = 156000 ; SHIFT RIGHT ROTATE SLRD = 153000 ; Shift left rotate double SRRD = 157000 ; Shift rigth rotate double ; ; Test functions ; DCD = 400 ; TEST DATA CHAN DONE BRD = 1000 ; TEST BRANCH DONE O = 1400 ; TEST NO OVERFLOW N = 2000 ; TEST CONDITION NEGATIVE Z = 2400 ; TEST CONDITION ZERO ZB = 3000 ; TEST CONDITION BYTE ZERO 0-7 BITS C = 3400 ; TEST CONDITION CARRY OCCURRED (NO CARRY ON SB) Q = 4000 ; TEST CONDITION Q RESPONSE X = 4400 ; TEST BRANCH X RESPONSE B10 = 5000 ; TEST BIT # 12 B11 = 5400 ; TEST BIT # 11 B12 = 6000 ; TEST BIT # 12 B13 = 6400 ; TEST BIT # 13 B14 = 7000 ; TEST BIT # 14 B15 = 7400 ; TEST BIT # 15 ; ; Control functions ; RDH = 400 ; READ + HOLD RDR = 1000 ; READ BUS WTR = 1400 ; WRITE BRR = 2000 ; BRANCH READ BRW = 2400 ; BRANCH WRITE BRC = 3000 ; BRANCH EXECUTE CONTROL FUNCTION BGL = 3400 ; BRANCH GL CYCLE EXM = 4000 ; EXIT WITH QUICK RETURN , MIOP EXIT EXC = 4400 ; EXIT + WAIT FOR LAM, CAMAC RETURN EXT = 5000 ; EXIT NO RETURN INT = 5400 ; INTERRUPT CLRC = 6000 ; CLEAR CARRY WTH = 6400 ; WRITE + HOLD BREQ = 7000 ; BRANCH REQUEST IMM = 7400 ; IMMEDIATE MODE, DATA = LOW BYTE ; ; DEFINE ALL OF THE INSTRUCTIONS ; .MACRO MV ,S,D,F ; MOVE INSTRUCTION .IF NB F .WORD 0+F++D .IFF .WORD 0++D .ENDC .ENDM MV ; .MACRO INM ,S,D,F ; INCREMENT REGISTER .IF NB F .WORD 10000+F++D .IFF .WORD 10000++D .ENDC .ENDM INM ; .MACRO DEM ,S,D,F ; DECREMENT REGISTER .IF NB F .WORD 20000+F++D .IFF .WORD 20000++D .ENDC .ENDM DEM ; .MACRO AD ,S,D,F ; ADD INSTRUCTION .IF NB F .WORD 30000+F++D .IFF .WORD 30000++D .ENDC .ENDM AD ; .MACRO SB ,S,D,F ; SUBTRACT INSTRUCTION .IF NB F .WORD 40000+F++D .IFF .WORD 40000++D .ENDC .ENDM SB ; .MACRO IOR ,S,D,F ; INCLUSIVE OR INSTRUCTION .IF NB F .WORD 50000+F++D .IFF .WORD 50000++D .ENDC .ENDM IOR ; .MACRO EOR ,S,D,F ; EXCLUSIVE OR INSTRUCTION .IF NB F .WORD 60000+F++D .IFF .WORD 60000++D .ENDC .ENDM EOR ; .MACRO AND ,S,D,F ; LOGICAL AND INSTRUCTION .IF NB F .WORD 70000+F++D .IFF .WORD 70000++D .ENDC .ENDM AND ; .MACRO BCT ,D,F ; BRANCH ON CONDITION TRUE INSTRUCTION .WORD 100000+F+</2> .ENDM BCT ; .MACRO BCF ,D,F ; BRANCH IF CONDITION FALSE INSTRUCTION .WORD 110000+F+</2> .ENDM BCF ; .MACRO ST ,D ; STORE INSTRUCTION .WORD 130000+</2> .ENDM ST ; .MACRO LD ,D ; LOAD INSTRUCTION (T = CONTENTS OF MEMORY) .WORD 140000+</2> .ENDM LD ; .MACRO STP ,D ; STORE PDR .WORD 134000+</2> .ENDM STP ; .MACRO LDP ,D ; LOAD PDR .WORD 144000+</2> .ENDM LDP .LIST