INTRODUCTION The purpose of the coreload is to determine the functions performed by the MBD. In essence the coreload determines what the MBD can do. This described coreload is designed for the RICE prototype MBD (MIOP) and may be used as only a guide in constructing loads for other devices. In essence this load converts the MBD into a special purpose computer which examines instructions in the PDP-11 memory and executes them to perform I/O. Since the MBD is fairly simple, the I/O computer it emulates is of necessity also simple. It looks like a register machine with 2 16 bit general purpose registers, a PC (program counter), DMA address and DMA counter. The 2 general purpose regs. are used for dual purposes. They may be used for simple calculations, and they contain the error count after general bulk DMA operations. In other words the general purpose regs. can have data placed into them, then this data may be transferred to the PDP-11 memory or merely tested to determine the next course of action. When DMA transfers from CAMAC to memory are performed the general purpose regs. keep track of the number of errors (lack of Q or X response). The DMA address and counter may be manipulated in a simple fashion by adding a constant to the address, and reducing the counter by the same amount. This allows skipping over data areas. The counter may be tested to check how much space remains for data transfers. Bulk data transfers cause automatic checking of the counter. If not enough space is available the bulk transfer is aborted before it begins. A special class of tranfers corresponding to a Q scan are available. This type of transfer proceeds till the buffer is full or a specified limit is reached. Only CAMAC devices that give Q are transferred. In general arithmetic operations on data have been excluded from the instruction set since the MBD is intended as a data transfer device rather than an analysis device. Limited masking (logical and) and testing operations have been designed. The following description assumes familiarity with the operation of the MBD or MIOP. The boldface terms refer to the program MBLOAD. Since the program MBLOAD is the actual MBD program this document is best understood by using it as a guide to MBLOAD. RICE MBD vs BiRa MBD a brief comparison The MBD memory must be loaded with a series of programs or microcode before the device handler may be used. The device handler may not even be loaded as that implies the microcode is available. Anyone may modify existing microcode as long as it has been designed to interact with the device handler properly. The current microcode assumes a RICE protototype MBD with only 256. words of memory. The prototype has 16 channels and lacks the multiple bit shift/rotate instruction. It has 8 general purpose registers rather than 7 in the BiRa MBD. It also has no GLR (Graded lam register). Interrupts are declared by a single instruction and interrupts remain pending till serviced. The Rice MBD has no knowledge of how many interrupts are pending, and up to 24 could be pending corresponding to the 16 MBD channels and 8 direct interrupts. These are serviced in order of priority. Certain nomenclature differs from the BiRa-LAMPF nomenclature. The PSR is the same as the PCR. A slight difference shows up here also. The Rice MBD can test bits 10 to 15 in its PSR while the BiRa version tests bits 12 to 15. In practice the bit 15 is always on in the Rice MBD as bits 10 to 15 are loaded only by move instructions when the source has bit 15 set on. The register names have the following definitions: REG# Name LAMPF Name Usage 0 T (ATR?) source of 0 1 ILR ILR Instruction location in CLIST 2 FCNA (DAR) Next CAMAC FCNA to execute 3 WCR WCR Word Count - number of transfers 4 TMP4 CCR Temporary register 5 QCNT CTR Q error count (number of errors) 6 XCNT GP1 X error count (number of errors) 7 R7 Buffer address 8 R8 Buffer word count (remaining count) 9 PSR Prog. stat reg. (same as LAMPF PCR) 10 MDR Memory data register 11 BDL Branch data low 12 BDH Branch data high 13 PDR Program data register (contains param list address) 14 MAR Memory address register(UNIBUS address) 15 BAR Branch address (CAMAC FCNA) These assignments are arbitrary for registers 1 to 8 but determined by hardware for 9 to 15. Certafor conventions have been determined in register usage. The buffer address and Instruction location are the next address - 1. This means that the address must be incremented before being used. The buffer word count contains the number of words available in the buffer. If zero no words are available. GENERAL PROGRAM DESCRIPTION The microcode makes the following assumptions about PSR bits 10-15. BIT# Action 14 No waits are executed (FAST) 13 Wait for LAM is executed 12 Multiple FCNA are expected (RANDOM) 11 Double word transfers are executed 10 ADD data to Buffer rather than MOVE to Buffer The meaning of bits 13&14 are the same for all functions. Bit 12&11 apply only to data transfer modes, while 10 applies only to CAMAC read functions. The requested action is performed if the bit is set. B13 takes precedence over B14, except when the action or function involves some repetitive action, then B14 takes precedence on each repeat. FAST means that the current channel will not exit till a STOP function is encountered. The CLIST is a set of instructions which tell the MBD what to do. The next word -1 in the CLIST is pointed to by the ILR. The CLIST consists of an instruction (single word) followed by 1 or more modifiers. The number of modifiers is determined by the instruction or function. When a given channel of the MBD is started the microcode begins execution at the label INIT:. The code following INIT takes the ISR (CCL in LAMPF nomenclature) multiplies it by 4 and adds on the PDR to find the correct spot in the parameter table. The BUFFER address, SIZE, and CLIST address are loaded into R7,R8, and the ILR. If the BUFFER address is zero it is not loaded and instead the program skips to END to execute the end of CLIST sequence. Next RETURN: is executed. RETURN is the segment which processes a new CLIST instruction. All CLIST instructions are assumed to have the following format. Bit 15 is set, Bits 10 to 14 are loaded into the PSR bits 10 to 14 , bits 0 to 2 contain the op code, bits 3 to 11 are reserved. If bit 15 is zero the program skips to END to execute the end sequence. Op codes then are in the range 0 to 7 with 5 modifiers (bits 10 to 14). The instruction is ored with octal 377 and the result is put into the PSR. After exectuion of a RTN control transfers to memory locations 370-377. These locations contain branches down to appropriate routines to execute the op code. The modifier bits were set by the transfer to the PSR. TABLE OF ROUTINES vs OP CODE Op code Routine What the routine does 0 INIT Used to restart the CLIST at beginning orreinitialize the buffer address and count 1 WRITE Write data to CAMAC 2 READ Read data from CAMAC 3 CTRL Execute CAMAC control functions 4 ERROR Put Error data into buffer or fixed constants, or saved data into buffer 5 CHAIN Transfer control to other part of CLIST depending on stored data. 6 C1 Transfer data to or from XCNT,QCNT 7 SCAN Perform Q scan , or multiway chain or unconditional chain. Certain routines in the microcode are used by a variety of other routines to load registers R1 to R4. These are LOAD4,LOAD3,LOAD2, RWSET, and RWSET2. These are executed by incrementing the PC program counter into the PSR to setup a return to the next instruction +1. Then a branch to the routine is executed. When through the routine either executes a RTN or an exit. Control is returned to the instruction following the branch. This is an effective way to implement subroutines, but no nesting is allowed. This is necessary because the RICE MBD has only 256 words of memory. The description of the MBD microcode is intended only a guide to reading the microcode. Detailed comments within the microcode should be sufficient to understand it. Since it is only 256 words long, it should be reasonably transparent. From the point of view of the user the CLIST is the important object. It contains the necessary instructions to be able to do CAMAC IO. The following discussion will divide the CLIST into several parts. First will be a discussion of READ,WRITE,CONTROL. Then other op codes or functions will be discussed. This order is designed to explain first the most useful codes and also the most regular codes. READ, WRITE, CONTROL (1,2,3) The general format of these instructions is: Word 1 Instruction Word 2 Count Word 3 FCNA Word 1 contains the Op code + modifiers. Word 2 contains the number of times it is to be executed. while word 3 contains the FCNA to be executed. The count must always be greater than zero. PS bits 10 to 14 modify the action of these instructions as has been already pointed out. IF bit 13 is set then a wait for lam will happen before each time the FCNA is executed. If bit 14 alone is set no waits (exits) occurr so that the transfer takes place at maximum speed with no interference from other channels. If both bits 13+14 are set then a wait for LAM will occurr only once, then the FCNAs are executed with no waits. If bit 12 is set the format changes to the following: Word 1 Instruction Word 2 Count = N Word 3 FCNA 1 Word 4 FCNA 2 .................... Word N+2 FCNA N Word N+3 0 (zero) This modifies the Instruction to mean execute N different FCNAs which follow the Count rather than executing the same one N times. Bits 10 and 11 have different meanings depending on the op code. BIT 11 when set for READ or WRITE means transfer 2 words of data per FCNA. This enables full 24 bit transfers rather than 16 bits. Bit 10 set for read means add the data to the buffer instead of moving it to the buffer. For Write it means add the count to the buffer address, but perform no transfer. This is equivalent to a dummy transfer or a change of address within the buffer Bit 10 may not be combined with bit 11 or 12 for WRITE. For CONTROL Bit 11 drastically changes the execution. The FCNA is only executed once, and then the Count is treated as an offset pointing to another segment of the CLIST. Execution of the CLIST will occurr at the other segment if Bit 10 is 0 and Q is False after the FCNA has executed or if Bit 10 is 1 and Q is True. This allows testing the results of the function. When either READ or WRITE functions are executed the microcode first checks to see if the buffer contains enough room for execution. If insufficient room is available then the END1 routine is executed to return an error code to the parameter table. The CLIST is then terminated and the appropriate end parameters are put into the parameter table. The MB driver routine inside the 11 will return the error code IE.DAO (data overrun). Of course no checking is necessary for CONTROL functions. Also the XCNT,QCNT registers are zeroed at the beginning of the READ,WRITE,CONTROL Instructions. Every time an FCNA fails to return a Q=True QCNT is incremented. Also if Q=False then X is tested and if it is False then XCNT is also incremented. STORE (4) STORE is an Instruction similar to READ except that no CAMAC transfers are involved, and the QCNT,XCNT registers are put into the buffer when B12=1. If B12=0 then it executes like WRITE, except that the XCNT is transferred to WCR rather than from the command list.  Word 1 Instruction Word 2 Count = N Word 3 0 The QCNT,XCNT registers are treated as a 24 bit word and are transferred to the Buffer N times. If Bit 11=0 then only the low order 16 bits (QCNT only) are transferred. Bits 10 + 11 modify the STORE op code in the same way they modify READ. The 24 bit data can be added to the buffer or it may be transferred as 16 bit data. INIT (0) This function is designed to reinitialize the command list. It can restart the command list or reinitialize the buffer word count and address to the original value. If B12=0 then only the buffer word count and address are reloaded. If B12=1 then the whole CLIST is restarted. CHAIN (5) This subroutine is designed to test data and transfer to another part of the CLIST depending on the value tested. The 2 types of data tested are either the word count or R5&R6. The following sequence is needed in the CLIST: 1 BRANCH = 5 + PSR bits 2 DATALO (16 bits) 3 DATAHI (8 bits) If negative test only low 16 bits 4 OFFSET to branch location The following sequence of PS bits are used: B12 = 0 BRANCH on word count B12 = 1 BRANCH on R5,R6 treated as a 2 word 24 bit integer, with the least sig. bits in R5. R5,R6 are treated as a positive integer. B10 B11 result 0 0 branch when DATA .EQ. test value 0 1 branch when DATA .GE. test value 1 0 branch when DATA .NE. test value 1 1 branch when DATA .LT. test value Normally R5,R6 are the Q,X error count, but the C1 subroutine allows them to be loaded from CAMAC by a test value. The BRANCH function is then very useful for deciding either how much data space (buffer space) is left, how many errors were committed during the last, READ,WRITE,CTRL or what to do next depending on the data available. As noted before if the DATAHI is negative only the low 16 bits (R5) are tested. C1 (6) This routine is a grab bag of several functions all of which involve transfers to or from XCNT,QCNT treated as a single 32 bit register. The form of the instruction is: 1. 6 + status bits 2. DATALO 3. DATAHI 4. FCNA If B11=1 then C1 reads from CAMAC and then forms the logical and of the CAMAC data and the DATA in the command list. The result is left in XCNT,QCNT (R5,R6). If B11=0 B10=0 then the logical and of QCNT,XCNT with the DATALI,DATAHI is formed and the result is in XCNT,XCNT. If B11=0, B10=1 then the DATALO,DATAHI are transferred to XCNT,QCNT. If B12=1 then in addition to the preceeding the data in XCNT,QCNT is written to CAMAC using the FCNA specified. read and incremented. B10 is used in a special manner in this routine. If B10=0 the DMI operation is repeated again. B10=0 causes the routine to wait for LAM at the end of the first DMI and then the operation is repeated again and again until the DMI operation causes an overflow in a buffer memory location. B10=1 terminates the DMI operation after 1 pass. SCAN (7) This is another mixed bag of operations. The operations are divided into 2 classes, BRANCH and Q scan. This BRANCH operations include unconditional BRANCH and computed BRANCH similar to the FORTRAN computed GO TO. a) BRANCH unconditonal 1. 7 + B10=1,B11=1,B12=? 2. OFFSET This routine will transfer control to the section of CLIST specified by the OFFSET. An OFFSET of zero will transfer control to the next word after the OFFSET. An OFFSET of -2 will transfer control 2 words back to the beginning of the BRANCH instruction, thus causing an infinite loop. This instruction is always FAST. b) BRANCH computed multiway 1. 7 + B10=0,B11=0,B12=1 2. DATAOFF 3. MULTIPLICITY=N 4. OFFSETN 5. OFFSETN-1 ....... N+2. OFFSET2 N+3. OFFSET1 An index is formed by subtracting the DATAOFF from the data in R5 (QCNT) and if the result is zero,negative, or greater than the MULTIPLICITY then control returns following the BRANCH command. If the index is greater than zero or less than or equal to the MULTIPLICITY then the program will start executing at the location indicated by the appropriate offset. Each offset is relative to itself. In other words if the index is 2 and OFFSET2 is zero then execution will continue at the word following OFFSET2 (probably not the correct place). c) Q scan set up This function starts a Q scan by setting the correct starting FCNA, and the COUNT which determines the maximum number of CAMAC reads. 1. 7 + B10=1,B11=0,B12=0 2. COUNT 3. FCNA d) Q scan continuation This routine is designed to do a multiple transfer either until the input buffer is full, the limit WCR is zero, or there is no Q response. The transfer can either occurr from a single fixed FCNA or a series of FCNA's. When a fixed FCNA is used the transfer terminates when there is no Q response. If a series of FCNA's are used the FCNA is incremented, then CAMAC is read. If no Q occurrs, the data is ignored and the next FCNA is tried. This continues until the COUNT is exhausted or the buffer is full. The instruction format is: 1. 7 + B10=1,B12=X 2. 0 3. 0 Fixed Q scan is requested when B12=0, and multiple Q scan when B12=1. B11 is the same as for READ,WRITE and it determines whether 1 or 2 word tranfers occurr. Q scan can not be used to add CAMAC data to the data buffer. The buffer is filled as follows. First a 1 word count is put into the buffer denoting the number of words that follow, then the data words. If there is no data the count is 0 and if the Q scan overflows the buffer the count is -1.